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Fixes needed to write DEF from certain layout cells #371

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RTimothyEdwards opened this issue Nov 8, 2022 · 0 comments · May be fixed by #370
Open

Fixes needed to write DEF from certain layout cells #371

RTimothyEdwards opened this issue Nov 8, 2022 · 0 comments · May be fixed by #370
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PnR Gate level verilog and/or layout changed

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@RTimothyEdwards
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(1) The chip_io_prep.sh script has errors preventing it from correctly generating a DEF file of chip_io and chip_io_alt.
(2) The gpio_signal_buffering layout has two power supplies labeled vccd9 and vssd9` which interferes with running the resulting DEF file through static timing analysis.

These errors have been fixed in PR #370
@RTimothyEdwards RTimothyEdwards added the PnR Gate level verilog and/or layout changed label Nov 8, 2022
@RTimothyEdwards RTimothyEdwards self-assigned this Nov 8, 2022
@RTimothyEdwards RTimothyEdwards linked a pull request Nov 8, 2022 that will close this issue
Fixes for enabling correct DEF generation. #370
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Fixes for enabling correct DEF generation. efabless/caravel
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