From ca4a54f5f155f177fa29da4f797a3acbbae7a7f2 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 30 Oct 2023 09:03:18 -0700 Subject: [PATCH] revert clock to be assigned to anything so iverilog will not remove it --- verilog/rtl/toplevel_cocotb.v | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/verilog/rtl/toplevel_cocotb.v b/verilog/rtl/toplevel_cocotb.v index 2ffd3c50..183db3f7 100644 --- a/verilog/rtl/toplevel_cocotb.v +++ b/verilog/rtl/toplevel_cocotb.v @@ -153,6 +153,8 @@ caravel uut ( ); `endif // CPU_TYPE_ARM `else // ! openframe + wire dummy_wire_clk; // iverilog ignores clock_tb if it's not assigned + assign dummy_wire_clk = clock_tb; caravel_openframe uut ( .vddio (vddio_tb), .vssio (vssio_tb), @@ -171,6 +173,14 @@ caravel uut ( .gpio (mprj_io_tb), .resetb (resetb_tb) ); + + + assign gpio_tb = 0; + assign vddio_2_tb = 0; + assign vssio_2_tb = 0; + assign vdda1_2_tb = 0; + assign vssa1_2_tb = 0; + `endif // ! openframe `ifdef USE_USER_VIP