From 082e52c41d9370413c09ec5ac372dc2aa9381f00 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 12 Jun 2023 09:28:56 -0700 Subject: [PATCH 1/5] Fix power guards --- verilog/rtl/chip_io.v | 2 ++ verilog/rtl/pads.v | 4 ++-- verilog/rtl/simple_por.v | 15 +++++++++++---- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v index a9626868..34b4c3e8 100644 --- a/verilog/rtl/chip_io.v +++ b/verilog/rtl/chip_io.v @@ -276,8 +276,10 @@ module chip_io( wire [6:0] vssd_const_zero; // Constant value for management pins constant_block constant_value_inst [6:0] ( + `ifdef USE_POWER_PINS .vccd(vccd), .vssd(vssd), + `endif // USE_POWER_PINS .one(vccd_const_one), .zero(vssd_const_zero) ); diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v index 623fc818..aad49243 100644 --- a/verilog/rtl/pads.v +++ b/verilog/rtl/pads.v @@ -45,7 +45,7 @@ `define MGMT_ABUTMENT_PINS \ .AMUXBUS_A(analog_a),\ - .AMUXBUS_B(analog_b),\ + .AMUXBUS_B(analog_b), `ifdef USE_POWER_PINS \ .VSSA(vssa),\ .VDDA(vdda),\ .VSWITCH(vddio),\ @@ -55,7 +55,7 @@ .VCCD(vccd),\ .VSSIO(vssio),\ .VSSD(vssd),\ - .VSSIO_Q(vssio_q), + .VSSIO_Q(vssio_q), `endif `else `define USER1_ABUTMENT_PINS `define USER2_ABUTMENT_PINS diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v index 0521c656..67f12b36 100644 --- a/verilog/rtl/simple_por.v +++ b/verilog/rtl/simple_por.v @@ -44,12 +44,19 @@ module simple_por( // down. Note that this is sped way up for verilog simulation; the // actual circuit is set to a 15ms delay. - always @(posedge vdd3v3) begin + `ifdef USE_POWER_PINS + always @(posedge vdd3v3) begin + `else + initial begin + `endif #500 inode <= 1'b1; end - always @(negedge vdd3v3) begin - #500 inode <= 1'b0; - end + + `ifdef USE_POWER_PINS + always @(negedge vdd3v3) begin + #500 inode <= 1'b0; + end + `endif // Instantiate two shmitt trigger buffers in series From cd9fbc8aadcfca66307d06502e3eba4d27acc55e Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 12 Jun 2023 16:43:17 +0000 Subject: [PATCH 2/5] Apply automatic changes to Manifest and README.rst --- manifest | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/manifest b/manifest index 96d619cf..e86384de 100644 --- a/manifest +++ b/manifest @@ -20,7 +20,7 @@ fa26aa34b4b382aacad9b7ac07a36b17172a401f verilog/rtl/caravel.v 1bbaa93405d4cb51429eacea4da40014231b11ed verilog/rtl/caravel_motto.v ae07f0d87e69f4dd2026ed841e3a962facac847b verilog/rtl/caravel_openframe.v d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v -bc1e961e41d1d3a383a018279a08bf4108911f53 verilog/rtl/chip_io.v +66cd4cc70097aa0a0666d0105712affa140a3977 verilog/rtl/chip_io.v f2242e1f295ee5efeacea51698f706a2cfd97c28 verilog/rtl/chip_io_alt.v 09740344da1a9bb76438165247c49b4795b94b9b verilog/rtl/chip_io_openframe.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v @@ -48,9 +48,9 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v 5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v 33c8fc54298e5425875aaab8c139074ec7d0e9e9 verilog/rtl/openframe_netlists.v -4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v +51f7c21d36076958a145a1ff8f4947b147e54fd4 verilog/rtl/pads.v 669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v -739ca5ed63a513d2e4c9bf3ecfad32d9fa527518 verilog/rtl/simple_por.v +83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d verilog/rtl/simple_por.v b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v 8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v 256190717faa72005cf7656d8443c4c0693b3f78 scripts/set_user_id.py From 7414a481877f10c8303623f013de00b97c4cb9cc Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 13 Jun 2023 00:09:17 -0700 Subject: [PATCH 3/5] Fix power guards for caravan and openframe --- verilog/rtl/chip_io_alt.v | 2 ++ verilog/rtl/chip_io_openframe.v | 12 ++++++++---- verilog/rtl/pads.v | 8 ++++---- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v index dde702f4..ff58ff21 100644 --- a/verilog/rtl/chip_io_alt.v +++ b/verilog/rtl/chip_io_alt.v @@ -345,8 +345,10 @@ module chip_io_alt #( wire [6:0] vssd_const_zero; // Constant value for management pins constant_block constant_value_inst [6:0] ( + `ifdef USE_POWER_PINS .vccd(vccd), .vssd(vssd), + `endif // USE_POWER_PINS .one(vccd_const_one), .zero(vssd_const_zero) ); diff --git a/verilog/rtl/chip_io_openframe.v b/verilog/rtl/chip_io_openframe.v index 9b5b5a3b..b689a114 100644 --- a/verilog/rtl/chip_io_openframe.v +++ b/verilog/rtl/chip_io_openframe.v @@ -262,8 +262,10 @@ module chip_io_openframe #( // These are exported to the user project for direct loopback if needed. constant_block constant_value_inst [`OPENFRAME_IO_PADS-1:0] ( - .vccd(vccd), - .vssd(vssd), + `ifdef USE_POWER_PINS + .vccd(vccd), + .vssd(vssd), + `endif // USE_POWER_PINS .one(gpio_loopback_one), .zero(gpio_loopback_zero) ); @@ -275,8 +277,10 @@ module chip_io_openframe #( wire xres_loopback_zero; constant_block constant_value_xres_inst ( - .vccd(vccd), - .vssd(vssd), + `ifdef USE_POWER_PINS + .vccd(vccd), + .vssd(vssd), + `endif // USE_POWER_PINS .one(xres_loopback_one), .zero(xres_loopback_zero) // (unused) ); diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v index aad49243..a7f813ea 100644 --- a/verilog/rtl/pads.v +++ b/verilog/rtl/pads.v @@ -17,7 +17,7 @@ `ifndef TOP_ROUTING `define USER1_ABUTMENT_PINS \ .AMUXBUS_A(analog_a),\ - .AMUXBUS_B(analog_b),\ + .AMUXBUS_B(analog_b),`ifdef USE_POWER_PINS\ .VSSA(vssa1),\ .VDDA(vdda1),\ .VSWITCH(vddio),\ @@ -27,11 +27,11 @@ .VCCD(vccd),\ .VSSIO(vssio),\ .VSSD(vssd),\ - .VSSIO_Q(vssio_q), + .VSSIO_Q(vssio_q),`endif `define USER2_ABUTMENT_PINS \ .AMUXBUS_A(analog_a),\ - .AMUXBUS_B(analog_b),\ + .AMUXBUS_B(analog_b),`ifdef USE_POWER_PINS\ .VSSA(vssa2),\ .VDDA(vdda2),\ .VSWITCH(vddio),\ @@ -41,7 +41,7 @@ .VCCD(vccd),\ .VSSIO(vssio),\ .VSSD(vssd),\ - .VSSIO_Q(vssio_q), + .VSSIO_Q(vssio_q),`endif `define MGMT_ABUTMENT_PINS \ .AMUXBUS_A(analog_a),\ From e90895bca60888505cd671654a05d8c296728563 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 13 Jun 2023 00:11:33 -0700 Subject: [PATCH 4/5] fix indentation --- verilog/rtl/chip_io.v | 4 ++-- verilog/rtl/chip_io_alt.v | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v index 34b4c3e8..f5f80649 100644 --- a/verilog/rtl/chip_io.v +++ b/verilog/rtl/chip_io.v @@ -277,8 +277,8 @@ module chip_io( constant_block constant_value_inst [6:0] ( `ifdef USE_POWER_PINS - .vccd(vccd), - .vssd(vssd), + .vccd(vccd), + .vssd(vssd), `endif // USE_POWER_PINS .one(vccd_const_one), .zero(vssd_const_zero) diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v index ff58ff21..18350b2b 100644 --- a/verilog/rtl/chip_io_alt.v +++ b/verilog/rtl/chip_io_alt.v @@ -346,11 +346,11 @@ module chip_io_alt #( constant_block constant_value_inst [6:0] ( `ifdef USE_POWER_PINS - .vccd(vccd), - .vssd(vssd), + .vccd(vccd), + .vssd(vssd), `endif // USE_POWER_PINS - .one(vccd_const_one), - .zero(vssd_const_zero) + .one(vccd_const_one), + .zero(vssd_const_zero) ); // Management clock input pad From 5e12ca04ba7cd042a7b10fe56b5b22da86f3d6d2 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 13 Jun 2023 07:24:45 +0000 Subject: [PATCH 5/5] Apply automatic changes to Manifest and README.rst --- manifest | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/manifest b/manifest index e86384de..3095103d 100644 --- a/manifest +++ b/manifest @@ -20,9 +20,9 @@ fa26aa34b4b382aacad9b7ac07a36b17172a401f verilog/rtl/caravel.v 1bbaa93405d4cb51429eacea4da40014231b11ed verilog/rtl/caravel_motto.v ae07f0d87e69f4dd2026ed841e3a962facac847b verilog/rtl/caravel_openframe.v d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v -66cd4cc70097aa0a0666d0105712affa140a3977 verilog/rtl/chip_io.v -f2242e1f295ee5efeacea51698f706a2cfd97c28 verilog/rtl/chip_io_alt.v -09740344da1a9bb76438165247c49b4795b94b9b verilog/rtl/chip_io_openframe.v +e54c181033aa019f0edcaed5ffc71e54c3888970 verilog/rtl/chip_io.v +1088531d6a69d82b976d4aca7ae923423680a715 verilog/rtl/chip_io_alt.v +e293e138c6e6f5df76db78bdaa34a35003f6ba5f verilog/rtl/chip_io_openframe.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v 941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v 58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v @@ -48,7 +48,7 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v 5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v 33c8fc54298e5425875aaab8c139074ec7d0e9e9 verilog/rtl/openframe_netlists.v -51f7c21d36076958a145a1ff8f4947b147e54fd4 verilog/rtl/pads.v +b53c154e6acaf44e858c936c8027d0229608676e verilog/rtl/pads.v 669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v 83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d verilog/rtl/simple_por.v b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v