diff --git a/chapters/grading/grading.md b/chapters/grading/grading.md index 278b926..9eee539 100644 --- a/chapters/grading/grading.md +++ b/chapters/grading/grading.md @@ -8,11 +8,11 @@ - 10p Tema (bonus) ### Promovare: - - minim 25p laborator - - minim 25p examen final + - Minim 25p Laborator + - Minim 50p Total ### Test circuite combinaționale - - Materia necesară: laborataorele 1,2 și 3 + - Materia necesară: laboratoarele 1,2 și 3 - Durată: 60 de minute - Când: la începutul laboratorului 4 - Strcutură: 3 exerciții practice de implementat în verilog @@ -20,7 +20,7 @@ - Platformă: Calculator Laborator - Safe Exam Browser - Moodle - VPL ### Test circuite secvențiale - - Materia necesară: laborataorele 4,5 și 6 + - Materia necesară: laboratoarele 4,5 și 6 - Durată: 60 de minute - Când: la începutul laboratorului 7 - Strcutură: 3 exerciții practice de implementat în verilog @@ -28,7 +28,7 @@ - Platformă: Calculator Laborator - Safe Exam Browser - Moodle - VPL ### Colocviu final calculator didactic - - Materia necesară: toate laborataorele + - Materia necesară: toate laboratoarele - Durată: 120 de minute - Când: la ultimul laborator - Strcutură: @@ -41,6 +41,7 @@ - Durată: Întreg semestrul cu termen limită începutul ultimii săptămâni de laborator - Platformă: Moodle - VPL - Punctaj: Se va adăuga punctajului de laborator (nu se ia în considerare la punctajul minim) + - Punctaj: Punctajul total de laborator se trunchează la 50 de puncte. ### Examen Final (AB) - Platformă: Moodle - VPL/Quiz diff --git a/chapters/guides/docker/linux/README.md b/chapters/guides/docker/linux/README.md new file mode 100644 index 0000000..f5520d8 --- /dev/null +++ b/chapters/guides/docker/linux/README.md @@ -0,0 +1,33 @@ +# Utilizare imagine docker Linux + +## Cerințe necesare + +## Rulare + +### Opțiunea 1 din Visual Studio Code + +1. Deschideți directorul repo-ului în Visual Studio Code. +```bash +code computer-architecture +``` + +2. Instalați extensia [Dev Containers](https://marketplace.visualstudio.com/items?itemName=ms-vscode-remote.remote-containers). + +3. După veți avea opțiunea "Dev Containers: Reopen in container" (`CTRL+SHIFT+P`). + +### Opțiunea 2 prin docker + +1. Descărcați imaginea cu docker +```bash +docker pull gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0 +``` + +2. Rulați un container cu imaginea +```bash +docker run --rm -it -v /dev:/dev gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0 /bin/bash +``` + +3. Rulați vivado din imagine +```bash +vivado +``` diff --git a/chapters/guides/docker/media/installxlaunch1.png b/chapters/guides/docker/media/installxlaunch1.png new file mode 100644 index 0000000..c2a1248 Binary files /dev/null and b/chapters/guides/docker/media/installxlaunch1.png differ diff --git a/chapters/guides/docker/media/installxlaunch2.png b/chapters/guides/docker/media/installxlaunch2.png new file mode 100644 index 0000000..900e0ff Binary files /dev/null and b/chapters/guides/docker/media/installxlaunch2.png differ diff --git a/chapters/guides/docker/media/installxlaunch3.png b/chapters/guides/docker/media/installxlaunch3.png new file mode 100644 index 0000000..bc20cb3 Binary files /dev/null and b/chapters/guides/docker/media/installxlaunch3.png differ diff --git a/chapters/guides/docker/media/installxlaunch4.png b/chapters/guides/docker/media/installxlaunch4.png new file mode 100644 index 0000000..43ef460 Binary files /dev/null and b/chapters/guides/docker/media/installxlaunch4.png differ diff --git a/chapters/guides/docker/media/installxlaunch5.png b/chapters/guides/docker/media/installxlaunch5.png new file mode 100644 index 0000000..e3bc3bd Binary files /dev/null and b/chapters/guides/docker/media/installxlaunch5.png differ diff --git a/chapters/guides/docker/media/installxlaunch6.png b/chapters/guides/docker/media/installxlaunch6.png new file mode 100644 index 0000000..4bb6f2a Binary files /dev/null and b/chapters/guides/docker/media/installxlaunch6.png differ diff --git a/chapters/guides/docker/media/installxlaunch7.png b/chapters/guides/docker/media/installxlaunch7.png new file mode 100644 index 0000000..74d43f7 Binary files /dev/null and b/chapters/guides/docker/media/installxlaunch7.png differ diff --git a/chapters/guides/docker/media/installxlaunch8.png b/chapters/guides/docker/media/installxlaunch8.png new file mode 100644 index 0000000..e41d0b2 Binary files /dev/null and b/chapters/guides/docker/media/installxlaunch8.png differ diff --git a/chapters/guides/docker/media/runxlaunch1.png b/chapters/guides/docker/media/runxlaunch1.png new file mode 100644 index 0000000..a5fcc7f Binary files /dev/null and b/chapters/guides/docker/media/runxlaunch1.png differ diff --git a/chapters/guides/docker/media/runxlaunch2.png b/chapters/guides/docker/media/runxlaunch2.png new file mode 100644 index 0000000..41f49d9 Binary files /dev/null and b/chapters/guides/docker/media/runxlaunch2.png differ diff --git a/chapters/guides/docker/media/runxlaunch3.png b/chapters/guides/docker/media/runxlaunch3.png new file mode 100644 index 0000000..5ca6f01 Binary files /dev/null and b/chapters/guides/docker/media/runxlaunch3.png differ diff --git a/chapters/guides/docker/media/runxlaunch4.png b/chapters/guides/docker/media/runxlaunch4.png new file mode 100644 index 0000000..172c1b2 Binary files /dev/null and b/chapters/guides/docker/media/runxlaunch4.png differ diff --git a/chapters/guides/docker/windows/README.md b/chapters/guides/docker/windows/README.md new file mode 100644 index 0000000..14dd589 --- /dev/null +++ b/chapters/guides/docker/windows/README.md @@ -0,0 +1,116 @@ +# Utilizare imagine docker Windows + +## Cerințe necesare + +### WSL + +1. Deschideți meniul Start și tastați "Windows features" în bara de căutare și faceți clic pe "Turn Windows Features On or Off". + +2. Bifați casetele "Windows Subsystem for Linux" și "Virtual Machine Platform" și apăsați butonul "OK". + +3. Când operațiunea este completă, vi se va cere să reporniți computerul. + +4. Instalați distribuția dorită din command prompt: +```bash +wsl --install -d Ubuntu-22.04 +``` + +Alt tutorial [Ubuntu](https://linuxconfig.org/ubuntu-22-04-on-wsl-windows-subsystem-for-linux) + +### Docker Desktop + +Instalare [Docker Desktop](https://www.docker.com/products/docker-desktop/). + +### Instalre XLaunch + +1. Descărcați [Xming X Server](http://www.straightrunning.com/XmingNotes/) - Public Domain Releases + +![installxlaunch1](../media/installxlaunch1.png) + +2. Deschideți installer-ul și apăsați butonul "Next". + +![installxlaunch2](../media/installxlaunch2.png) + +3. Apăsați butonul "Next". + +![installxlaunch3](../media/installxlaunch3.png) + +4. Apăsați butonul "Next". + +![installxlaunch4](../media/installxlaunch4.png) + +5. Apăsați butonul "Next". + +![installxlaunch5](../media/installxlaunch5.png) + +6. Selectați "Create a desktop icon for XLaunch" și apăsați butonul "Next". + +![installxlaunch6](../media/installxlaunch6.png) + +7. Apăsați butonul "Install". + +![installxlaunch7](../media/installxlaunch7.png) + +8. Apăsați butonul "Finish". + +![installxlaunch8](../media/installxlaunch8.png) + +### Visual Studio Code + +Descărcați și instalați [Visual Studio Code](https://code.visualstudio.com/download) + +### Clonați repo-ul materiei + +```bash +git clone https://github.com/cs-pub-ro/computer-architecture.git +``` + +## Rulare + +### Porniți XLaunch +1. Deschideți XLaunch (Desktop sau Start Menu) + +2. Selectați opțiunile pentru Disaply și apăsați butonul "Next". + +![runxlaunch1](../media/runxlaunch1.png) + +3. Selectați "Start no client" și apăsați butonul "Next". + +![runxlaunch2](../media/runxlaunch2.png) + +4. Selectați "No access control" și apăsați butonul "Next". + +![runxlaunch3](../media/runxlaunch3.png) + +5. Apăsați butonul "Finish". + +![runxlaunch4](../media/runxlaunch4.png) + + +### Opțiunea 1 din Visual Studio Code + +1. Deschideți directorul repo-ului în Visual Studio Code. +```bash +code computer-architecture +``` + +2. Instalați extensia [Dev Containers](https://marketplace.visualstudio.com/items?itemName=ms-vscode-remote.remote-containers). + +3. După veți avea opțiunea "Dev Containers: Reopen in container" (`CTRL+SHIFT+P`). + +### Opțiunea 2 prin docker + +1. Descărcați imaginea cu docker +```bash +docker pull gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0 +``` + +2. Rulați un container cu imaginea +```bash +docker run --rm -it -v /dev:/dev gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0 /bin/bash +``` + +3. Rulați vivado din imagine +```bash +vivado +``` diff --git a/chapters/intro/.gitignore b/chapters/intro/.gitignore new file mode 100644 index 0000000..e69de29 diff --git a/chapters/intro/soc/media/app-os-cpu-interaction.svg b/chapters/intro/soc/media/app-os-cpu-interaction.svg new file mode 100644 index 0000000..72136f3 --- /dev/null +++ b/chapters/intro/soc/media/app-os-cpu-interaction.svg @@ -0,0 +1,4 @@ + + + +
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HardwareText is not SVG - cannot display \ No newline at end of file diff --git a/chapters/intro/soc/media/cpu-internals.jpg b/chapters/intro/soc/media/cpu-internals.jpg new file mode 100644 index 0000000..15ef468 Binary files /dev/null and b/chapters/intro/soc/media/cpu-internals.jpg differ diff --git a/chapters/intro/soc/reading/README.md b/chapters/intro/soc/reading/README.md new file mode 100644 index 0000000..0331196 --- /dev/null +++ b/chapters/intro/soc/reading/README.md @@ -0,0 +1,24 @@ +# Template Chapter + +This is an instance of a lab placeholder. +This will be used to showcase the different highlights of the syntax. + +This is another sentence + +In order to use links to to outside resources, you can add them as [such](http://example.com). + +This is a list of all the best cuisines in the world +- Indian +- Italian +- French + +In order to make emphasize keywords, you can use **bold** words. +To suggest a more metaphorical and less literal meaning of a phrase, you can use _italic_ words. + +## Section the first + +For each skill learned in the lab, you will use a subsection which will touch up on new concepts. + +For integrating figures, you will use `![Example SVG](../media/app-os-cpu-interaction.svg)`. + +![Example SVG](../media/app-os-cpu-interaction.svg) diff --git a/chapters/intro/soc/slides/.gitignore b/chapters/intro/soc/slides/.gitignore new file mode 100644 index 0000000..421b540 --- /dev/null +++ b/chapters/intro/soc/slides/.gitignore @@ -0,0 +1,3 @@ +/slides.md +/_site/ +/media/ diff --git a/chapters/intro/soc/slides/Makefile b/chapters/intro/soc/slides/Makefile new file mode 100644 index 0000000..602ba9e --- /dev/null +++ b/chapters/intro/soc/slides/Makefile @@ -0,0 +1,35 @@ +RVMD = reveal-md +MDPP = markdown-pp +FFMPEG = ffmpeg + +SLIDES ?= slides.mdpp +SLIDES_OUT ?= slides.md +MEDIA_DIR ?= ../media +SITE ?= _site +OPEN ?= xdg-open + +.PHONY: all html clean videos + +all: videos html + +html: $(SITE) + +$(SITE): $(SLIDES) + $(MDPP) $< -o $(SLIDES_OUT) + $(RVMD) $(SLIDES_OUT) --static $@ + +videos: + test -z $(TARGETS) || for TARGET in $(TARGETS); do \ + $(FFMPEG) -framerate 0.5 -f image2 -y \ + -i "$(MEDIA_DIR)/$$TARGET/$$TARGET-%d.svg" -vf format=yuv420p $(MEDIA_DIR)/$$TARGET-generated.gif; \ + done + +open: $(SITE) + $(OPEN) $ + +### Cuprins materie + +0. Introducere +1. Structură Calculator Numeric +2. Reprezentarea și prelucrarea informației +3. Memorii +4. UAL +5. Arhitectura Calculatorului Didactic +6. Limbaje de asamblare +7. Subsistem intrare/ieșire +8. Întreruperi +9. Microprogramare + +--- + +### Obiectivele materiei + + - Cultură generală despre arhitectura calculatoarelor + - Reprezentarea informației + - Memorii + - Seturi de instrucțiuni + - Codificare instrucțiuni + - Limbaj de asamblare + - Întreruperi de procesor + - Descriere hardware a unui procesor prin limbajul Verilog diff --git a/chapters/intro/soc/slides/slides.mdpp b/chapters/intro/soc/slides/slides.mdpp new file mode 100644 index 0000000..f30388f --- /dev/null +++ b/chapters/intro/soc/slides/slides.mdpp @@ -0,0 +1,15 @@ +--- +title: "Computer Architecture: 0 Introduction" +revealOptions: + background-color: 'white' + transition: 'none' + slideNumber: true + autoAnimateDuration: 0.0 +--- + +!INCLUDE "intro.md" + +--- + +!INCLUDE "content.md" + diff --git a/chapters/verilog/basic/drills/README.md b/chapters/verilog/basic/drills/README.md index 64145f4..687d9a2 100644 --- a/chapters/verilog/basic/drills/README.md +++ b/chapters/verilog/basic/drills/README.md @@ -1,5 +1,34 @@ -# Practice: Basic structural - - Simulați un **sumator elementar complet**, utilizând sumatoare elementare parțiale. - - Simulați un **sumator pe 4 biți**, cu două intrări și două ieșiri. Verificați corectitudinea sumatorului vizualizând semnalele în baza 10. - - Simulați un **sumator pe 6 biți**, cu două intrări și o ieșire. - - Simulați un **comparator** pe un bit. Acesta are două intrări și 3 ieșiri (pentru mai mic, egal și mai mare). \ No newline at end of file +# Practică: + +## 1. **Sumator elementar complet**, utilizând sumatoare elementare parțiale. + Soluția se află în repo-ul materiei [GitHub](https://github.com/cs-pub-ro/computer-architecture/tree/main/chapters/verilog/basic/drills/tasks/fulladder). Implementarea unui sumatoar elementar parțial se poate găsi în fișierul `halfadder.v`, iar sumator elementar complet în `fulladder.v`. Observați modul în care sunt declarate sumatoarele elementare partțiale. + ```verilog + halfadder l_m_halfadder_0( .o_w_s(l_w_s0), .o_w_cout(l_w_c0), .i_w_a(i_w_a), .i_w_b(i_w_b) ); + halfadder l_m_halfadder_1( .o_w_s(o_w_s), .o_w_cout(l_w_c1), .i_w_a(i_w_cin), .i_w_b(l_w_s0) ); + ``` + Pentru a crea proiectul putem folosi comanda ```make build```. Pentru simulare ```make simluation``` și pentru a deschide întreg proiectul în vivado și a avea posibilitatea de a încărca pe FPGA ```make vivado```. + +## 2. **Sumator pe 4 biți**, cu două intrări și două ieșiri. + Soluția se află în repo-ul materiei [GitHub](https://github.com/cs-pub-ro/computer-architecture/tree/main/chapters/verilog/basic/drills/tasks/adder_4bits). Rulați simulare (```make simluation```) și verificați corectitudinea sumatorului vizualizând semnalele în baza 10. + +## 3. **Sumator pe 6 biți**, cu două intrări și o ieșire. + Soluția se află în repo-ul materiei [GitHub](https://github.com/cs-pub-ro/computer-architecture/tree/main/chapters/verilog/basic/drills/tasks/adder_6bits). Încărcați programul pe FPGA (```make vivado```), urmărind ghidul. + +## 4. **Comparator** pe un bit. + Acesta are două intrări și 3 ieșiri (pentru mai mic, egal și mai mare). Soluția se află în repo-ul materiei [GitHub](https://github.com/cs-pub-ro/computer-architecture/tree/main/chapters/verilog/basic/drills/tasks/comparator). Simulați și încărcați pe FPGA. + +## Test + Aveți următorul tabel de adevăr: + + | a | b | c | f | + | - | - | - | - | + | 0 | 0 | 0 | 1 | + | 0 | 0 | 1 | 0 | + | 0 | 1 | 0 | 0 | + | 0 | 1 | 1 | 0 | + | 1 | 0 | 0 | 1 | + | 1 | 0 | 1 | 1 | + | 1 | 1 | 0 | 1 | + | 1 | 1 | 1 | 0 | + + Intrările sun `a`, `b`, `c` iar ieșirea este `f`. Implementați modulul verilog este definit de acest tabel de adevăr. \ No newline at end of file diff --git a/chapters/verilog/basic/drills/tasks/task1/Makefile b/chapters/verilog/basic/drills/tasks/adder_4bits/Makefile similarity index 100% rename from chapters/verilog/basic/drills/tasks/task1/Makefile rename to chapters/verilog/basic/drills/tasks/adder_4bits/Makefile diff --git a/chapters/verilog/basic/drills/tasks/adder_4bits/adder_4bits.v b/chapters/verilog/basic/drills/tasks/adder_4bits/adder_4bits.v new file mode 100644 index 0000000..ce55671 --- /dev/null +++ b/chapters/verilog/basic/drills/tasks/adder_4bits/adder_4bits.v @@ -0,0 +1,16 @@ +module adder_4bits( + output wire [3:0] o_w_s, + output wire o_w_cout, + input wire [3:0] i_w_a, + input wire [3:0] i_w_b, + input wire i_w_cin +); + + //TODO 1.1: Implement with 4 full-adders + wire [3:0] l_w_carry; + fulladder l_m_fulladder_0 ( .o_w_s(o_w_s[0]), .o_w_cout(l_w_carry[0]), .i_w_a(i_w_a[0]), .i_w_b(i_w_b[0]), .i_w_cin(i_w_cin) ); + fulladder l_m_fulladder_1 ( .o_w_s(o_w_s[1]), .o_w_cout(l_w_carry[1]), .i_w_a(i_w_a[1]), .i_w_b(i_w_b[1]), .i_w_cin(l_w_carry[0]) ); + fulladder l_m_fulladder_2 ( .o_w_s(o_w_s[2]), .o_w_cout(l_w_carry[2]), .i_w_a(i_w_a[2]), .i_w_b(i_w_b[2]), .i_w_cin(l_w_carry[1]) ); + fulladder l_m_fulladder_3 ( .o_w_s(o_w_s[3]), .o_w_cout(o_w_cout), .i_w_a(i_w_a[3]), .i_w_b(i_w_b[3]), .i_w_cin(l_w_carry[2]) ); + +endmodule \ No newline at end of file diff --git a/chapters/verilog/basic/drills/tasks/task2/task2.xdc b/chapters/verilog/basic/drills/tasks/adder_4bits/adder_4bits.xdc similarity index 91% rename from chapters/verilog/basic/drills/tasks/task2/task2.xdc rename to chapters/verilog/basic/drills/tasks/adder_4bits/adder_4bits.xdc index b44c0a6..6c41dce 100644 --- a/chapters/verilog/basic/drills/tasks/task2/task2.xdc +++ b/chapters/verilog/basic/drills/tasks/adder_4bits/adder_4bits.xdc @@ -9,15 +9,15 @@ ##Switches -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[0] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[1] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[2] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[3] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { i_w_cin }]; #IO_L24N_T3_34 Sch=sw[8] #set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] #set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] @@ -27,11 +27,11 @@ #set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] ## LEDs -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { o_w_cout }]; #IO_L7P_T1_D09_14 Sch=led[4] #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] #set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] #set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] diff --git a/chapters/verilog/basic/drills/tasks/adder_4bits/tcl_files/build.tcl b/chapters/verilog/basic/drills/tasks/adder_4bits/tcl_files/build.tcl new file mode 100644 index 0000000..066a854 --- /dev/null +++ b/chapters/verilog/basic/drills/tasks/adder_4bits/tcl_files/build.tcl @@ -0,0 +1,8 @@ +create_project build build_project -part xc7a100tcsg324-1 -force +import_files -force -fileset sources_1 -norecurse ../fulladder/fulladder.v ../fulladder/halfadder.v adder_4bits.v +import_files -force -fileset sim_1 -norecurse test_adder_4bits.v +import_files -force -fileset constrs_1 -norecurse adder_4bits.xdc +set_property top adder_4bits [get_fileset sources_1] +set_property top test_adder_4bits [get_fileset sim_1] +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 diff --git a/chapters/verilog/basic/drills/tasks/task0/tcl_files/run.tcl b/chapters/verilog/basic/drills/tasks/adder_4bits/tcl_files/run.tcl similarity index 100% rename from chapters/verilog/basic/drills/tasks/task0/tcl_files/run.tcl rename to chapters/verilog/basic/drills/tasks/adder_4bits/tcl_files/run.tcl diff --git a/chapters/verilog/basic/drills/tasks/task0/tcl_files/simulation.tcl b/chapters/verilog/basic/drills/tasks/adder_4bits/tcl_files/simulation.tcl similarity index 100% rename from chapters/verilog/basic/drills/tasks/task0/tcl_files/simulation.tcl rename to chapters/verilog/basic/drills/tasks/adder_4bits/tcl_files/simulation.tcl diff --git a/chapters/verilog/basic/drills/tasks/task1/test_task1.v b/chapters/verilog/basic/drills/tasks/adder_4bits/test_adder_4bits.v similarity index 95% rename from chapters/verilog/basic/drills/tasks/task1/test_task1.v rename to chapters/verilog/basic/drills/tasks/adder_4bits/test_adder_4bits.v index ea54520..53c5cee 100644 --- a/chapters/verilog/basic/drills/tasks/task1/test_task1.v +++ b/chapters/verilog/basic/drills/tasks/adder_4bits/test_adder_4bits.v @@ -1,5 +1,5 @@ `timescale 1ns / 1ps -module test_task1; +module test_adder_4bits; //Inputs reg [3:0] l_r_a; reg [3:0] l_r_b; @@ -13,7 +13,7 @@ module test_task1; integer i,j,k; //Module initialization - task1 l_m_task1( + adder_4bits l_m_adder_4bits( .o_w_s(l_w_s), .o_w_cout(l_w_cout), .i_w_a(l_r_a), diff --git a/chapters/verilog/basic/drills/tasks/task2/Makefile b/chapters/verilog/basic/drills/tasks/adder_6bits/Makefile similarity index 100% rename from chapters/verilog/basic/drills/tasks/task2/Makefile rename to chapters/verilog/basic/drills/tasks/adder_6bits/Makefile diff --git a/chapters/verilog/basic/drills/tasks/adder_6bits/adder_6bits.v b/chapters/verilog/basic/drills/tasks/adder_6bits/adder_6bits.v new file mode 100644 index 0000000..e5d558e --- /dev/null +++ b/chapters/verilog/basic/drills/tasks/adder_6bits/adder_6bits.v @@ -0,0 +1,12 @@ +module adder_6bits( + output wire [6:0] o_w_s, + input wire [5:0] i_w_a, + input wire [5:0] i_w_b +); + + //TODO 3.1: Implement using + wire [1:0] l_w_carry; + adder_4bits l_m_adder_4bits ( .o_w_s(o_w_s[3:0]), .o_w_cout(l_w_carry[0]), .i_w_a(i_w_a[3:0]), .i_w_b(i_w_b[3:0]), .i_w_cin(1'b0) ); + fulladder l_m_fulladder_0 ( .o_w_s(o_w_s[4]), .o_w_cout(l_w_carry[1]), .i_w_a(i_w_a[4]), .i_w_b(i_w_b[4]), .i_w_cin(l_w_carry[0]) ); + fulladder l_m_fulladder_1 ( .o_w_s(o_w_s[5]), .o_w_cout(o_w_s[6]), .i_w_a(i_w_a[5]), .i_w_b(i_w_b[5]), .i_w_cin(l_w_carry[1]) ); +endmodule \ No newline at end of file diff --git a/chapters/verilog/basic/drills/tasks/task3/task3.xdc b/chapters/verilog/basic/drills/tasks/adder_6bits/adder_6bits.xdc similarity index 88% rename from chapters/verilog/basic/drills/tasks/task3/task3.xdc rename to chapters/verilog/basic/drills/tasks/adder_6bits/adder_6bits.xdc index b44c0a6..d86638d 100644 --- a/chapters/verilog/basic/drills/tasks/task3/task3.xdc +++ b/chapters/verilog/basic/drills/tasks/adder_6bits/adder_6bits.xdc @@ -9,31 +9,31 @@ ##Switches -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[0] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[1] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { i_w_b[2] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { i_w_b[3] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[4] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[5] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] #set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] #set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] #set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] #set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] ## LEDs -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { o_w_s[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] #set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] #set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] #set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] diff --git a/chapters/verilog/basic/drills/tasks/adder_6bits/tcl_files/build.tcl b/chapters/verilog/basic/drills/tasks/adder_6bits/tcl_files/build.tcl new file mode 100644 index 0000000..3597391 --- /dev/null +++ b/chapters/verilog/basic/drills/tasks/adder_6bits/tcl_files/build.tcl @@ -0,0 +1,8 @@ +create_project build build_project -part xc7a100tcsg324-1 -force +import_files -force -fileset sources_1 -norecurse adder_6bits.v ../adder_4bits/adder_4bits.v ../fulladder/fulladder.v ../fulladder/halfadder.v +import_files -force -fileset sim_1 -norecurse test_adder_6bits.v +import_files -force -fileset constrs_1 -norecurse adder_6bits.xdc +set_property top adder_6bits [get_fileset sources_1] +set_property top test_adder_6bits [get_fileset sim_1] +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 diff --git a/chapters/verilog/basic/drills/tasks/task1/tcl_files/run.tcl b/chapters/verilog/basic/drills/tasks/adder_6bits/tcl_files/run.tcl similarity index 100% rename from chapters/verilog/basic/drills/tasks/task1/tcl_files/run.tcl rename to chapters/verilog/basic/drills/tasks/adder_6bits/tcl_files/run.tcl diff --git a/chapters/verilog/basic/drills/tasks/task1/tcl_files/simulation.tcl b/chapters/verilog/basic/drills/tasks/adder_6bits/tcl_files/simulation.tcl similarity index 100% rename from chapters/verilog/basic/drills/tasks/task1/tcl_files/simulation.tcl rename to chapters/verilog/basic/drills/tasks/adder_6bits/tcl_files/simulation.tcl diff --git a/chapters/verilog/basic/drills/tasks/task2/test_task2.v b/chapters/verilog/basic/drills/tasks/adder_6bits/test_adder_6bits.v similarity index 94% rename from chapters/verilog/basic/drills/tasks/task2/test_task2.v rename to chapters/verilog/basic/drills/tasks/adder_6bits/test_adder_6bits.v index d4fffc9..4870606 100644 --- a/chapters/verilog/basic/drills/tasks/task2/test_task2.v +++ b/chapters/verilog/basic/drills/tasks/adder_6bits/test_adder_6bits.v @@ -1,5 +1,5 @@ `timescale 1ns / 1ps -module test_task2; +module test_adder_6bits; //Inputs reg [5:0] l_r_a; reg [5:0] l_r_b; @@ -11,7 +11,7 @@ module test_task2; integer i,j,k; //Module initialization - task2 l_m_task2( + adder_6bits l_m_adder_6bits( .o_w_s(l_w_s), .i_w_a(l_r_a), .i_w_b(l_r_b) diff --git a/chapters/verilog/basic/drills/tasks/task3/Makefile b/chapters/verilog/basic/drills/tasks/comparator/Makefile similarity index 100% rename from chapters/verilog/basic/drills/tasks/task3/Makefile rename to chapters/verilog/basic/drills/tasks/comparator/Makefile diff --git a/chapters/verilog/basic/drills/tasks/task3/task3.v b/chapters/verilog/basic/drills/tasks/comparator/comparator.v similarity index 94% rename from chapters/verilog/basic/drills/tasks/task3/task3.v rename to chapters/verilog/basic/drills/tasks/comparator/comparator.v index 1839ba3..b45c6a0 100644 --- a/chapters/verilog/basic/drills/tasks/task3/task3.v +++ b/chapters/verilog/basic/drills/tasks/comparator/comparator.v @@ -1,4 +1,4 @@ -module task3( +module comparator( output wire o_w_lt, output wire o_w_gt, output wire o_w_eq, diff --git a/chapters/verilog/basic/drills/tasks/task1/task1.xdc b/chapters/verilog/basic/drills/tasks/comparator/comparator.xdc similarity index 97% rename from chapters/verilog/basic/drills/tasks/task1/task1.xdc rename to chapters/verilog/basic/drills/tasks/comparator/comparator.xdc index b44c0a6..692f377 100644 --- a/chapters/verilog/basic/drills/tasks/task1/task1.xdc +++ b/chapters/verilog/basic/drills/tasks/comparator/comparator.xdc @@ -9,8 +9,8 @@ ##Switches -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { i_w_a }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { i_w_b }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] #set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] #set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] #set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] @@ -27,9 +27,9 @@ #set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] ## LEDs -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { o_w_lt }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { o_w_gt }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { o_w_eq }]; #IO_L17N_T2_A25_15 Sch=led[2] #set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] #set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] diff --git a/chapters/verilog/basic/drills/tasks/comparator/tcl_files/build.tcl b/chapters/verilog/basic/drills/tasks/comparator/tcl_files/build.tcl new file mode 100644 index 0000000..85de406 --- /dev/null +++ b/chapters/verilog/basic/drills/tasks/comparator/tcl_files/build.tcl @@ -0,0 +1,8 @@ +create_project build build_project -part xc7a100tcsg324-1 -force +import_files -force -fileset sources_1 -norecurse comparator.v +import_files -force -fileset sim_1 -norecurse test_comparator.v +import_files -force -fileset constrs_1 -norecurse comparator.xdc +set_property top comparator [get_fileset sources_1] +set_property top test_comparator [get_fileset sim_1] +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 diff --git a/chapters/verilog/basic/drills/tasks/task2/tcl_files/run.tcl b/chapters/verilog/basic/drills/tasks/comparator/tcl_files/run.tcl similarity index 100% rename from chapters/verilog/basic/drills/tasks/task2/tcl_files/run.tcl rename to chapters/verilog/basic/drills/tasks/comparator/tcl_files/run.tcl diff --git a/chapters/verilog/basic/drills/tasks/task2/tcl_files/simulation.tcl b/chapters/verilog/basic/drills/tasks/comparator/tcl_files/simulation.tcl similarity index 100% rename from chapters/verilog/basic/drills/tasks/task2/tcl_files/simulation.tcl rename to chapters/verilog/basic/drills/tasks/comparator/tcl_files/simulation.tcl diff --git a/chapters/verilog/basic/drills/tasks/task3/test_task3.v b/chapters/verilog/basic/drills/tasks/comparator/test_comparator.v similarity index 95% rename from chapters/verilog/basic/drills/tasks/task3/test_task3.v rename to chapters/verilog/basic/drills/tasks/comparator/test_comparator.v index f62e571..08d01b3 100644 --- a/chapters/verilog/basic/drills/tasks/task3/test_task3.v +++ b/chapters/verilog/basic/drills/tasks/comparator/test_comparator.v @@ -1,5 +1,5 @@ `timescale 1ns / 1ps -module test_task3; +module test_comparator; //Inputs reg l_r_a; reg l_r_b; @@ -13,7 +13,7 @@ module test_task3; integer i,j; //Module initialization - task3 l_m_task3( + comparator l_m_comparator( .o_w_lt(l_w_lt), .o_w_gt(l_w_gt), .o_w_eq(l_w_eq), diff --git a/chapters/verilog/basic/drills/tasks/task0/Makefile b/chapters/verilog/basic/drills/tasks/fulladder/Makefile similarity index 100% rename from chapters/verilog/basic/drills/tasks/task0/Makefile rename to chapters/verilog/basic/drills/tasks/fulladder/Makefile diff --git a/chapters/verilog/basic/drills/tasks/task0/task0.v b/chapters/verilog/basic/drills/tasks/fulladder/fulladder.v similarity index 54% rename from chapters/verilog/basic/drills/tasks/task0/task0.v rename to chapters/verilog/basic/drills/tasks/fulladder/fulladder.v index 24fe6f3..74d3be0 100644 --- a/chapters/verilog/basic/drills/tasks/task0/task0.v +++ b/chapters/verilog/basic/drills/tasks/fulladder/fulladder.v @@ -1,4 +1,4 @@ -module task0( +module fulladder( output wire o_w_s, output wire o_w_cout, input wire i_w_a, @@ -9,7 +9,7 @@ module task0( //TODO 0.2: Implement full-adder using 2 half-adders wire l_w_c0, l_w_c1; wire l_w_s0; - task01 l_m_task01_0( .o_w_s(l_w_s0), .o_w_cout(l_w_c0), .i_w_a(i_w_a), .i_w_b(i_w_b) ); - task01 l_m_task01_1( .o_w_s(o_w_s), .o_w_cout(l_w_c1), .i_w_a(i_w_cin), .i_w_b(l_w_s0) ); + halfadder l_m_halfadder_0( .o_w_s(l_w_s0), .o_w_cout(l_w_c0), .i_w_a(i_w_a), .i_w_b(i_w_b) ); + halfadder l_m_halfadder_1( .o_w_s(o_w_s), .o_w_cout(l_w_c1), .i_w_a(i_w_cin), .i_w_b(l_w_s0) ); or(o_w_cout, l_w_c0, l_w_c1); endmodule \ No newline at end of file diff --git a/chapters/verilog/basic/drills/tasks/task0/task0.xdc b/chapters/verilog/basic/drills/tasks/fulladder/fulladder.xdc similarity index 100% rename from chapters/verilog/basic/drills/tasks/task0/task0.xdc rename to chapters/verilog/basic/drills/tasks/fulladder/fulladder.xdc diff --git a/chapters/verilog/basic/drills/tasks/task0/task01.v b/chapters/verilog/basic/drills/tasks/fulladder/halfadder.v similarity index 91% rename from chapters/verilog/basic/drills/tasks/task0/task01.v rename to chapters/verilog/basic/drills/tasks/fulladder/halfadder.v index e4a67a2..7b3be65 100644 --- a/chapters/verilog/basic/drills/tasks/task0/task01.v +++ b/chapters/verilog/basic/drills/tasks/fulladder/halfadder.v @@ -1,4 +1,4 @@ -module task01 ( +module halfadder ( output wire o_w_s, output wire o_w_cout, input wire i_w_a, diff --git a/chapters/verilog/basic/drills/tasks/fulladder/tcl_files/build.tcl b/chapters/verilog/basic/drills/tasks/fulladder/tcl_files/build.tcl new file mode 100644 index 0000000..9e7defd --- /dev/null +++ b/chapters/verilog/basic/drills/tasks/fulladder/tcl_files/build.tcl @@ -0,0 +1,8 @@ +create_project build build_project -part xc7a100tcsg324-1 -force +import_files -force -fileset sources_1 -norecurse halfadder.v fulladder.v +import_files -force -fileset sim_1 -norecurse test_fulladder.v +import_files -force -fileset constrs_1 -norecurse fulladder.xdc +set_property top fulladder [get_fileset sources_1] +set_property top test_fulladder [get_fileset sim_1] +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 diff --git a/chapters/verilog/basic/drills/tasks/task3/tcl_files/run.tcl b/chapters/verilog/basic/drills/tasks/fulladder/tcl_files/run.tcl similarity index 100% rename from chapters/verilog/basic/drills/tasks/task3/tcl_files/run.tcl rename to chapters/verilog/basic/drills/tasks/fulladder/tcl_files/run.tcl diff --git a/chapters/verilog/basic/drills/tasks/task3/tcl_files/simulation.tcl b/chapters/verilog/basic/drills/tasks/fulladder/tcl_files/simulation.tcl similarity index 100% rename from chapters/verilog/basic/drills/tasks/task3/tcl_files/simulation.tcl rename to chapters/verilog/basic/drills/tasks/fulladder/tcl_files/simulation.tcl diff --git a/chapters/verilog/basic/drills/tasks/task0/test_task0.v b/chapters/verilog/basic/drills/tasks/fulladder/test_fulladder.v similarity index 95% rename from chapters/verilog/basic/drills/tasks/task0/test_task0.v rename to chapters/verilog/basic/drills/tasks/fulladder/test_fulladder.v index 363ad78..10fab0b 100644 --- a/chapters/verilog/basic/drills/tasks/task0/test_task0.v +++ b/chapters/verilog/basic/drills/tasks/fulladder/test_fulladder.v @@ -1,5 +1,5 @@ `timescale 1ns / 1ps -module test_task0; +module test_fulladder; //Inputs reg l_r_a; reg l_r_b; @@ -13,7 +13,7 @@ module test_task0; integer i,j,k; //Module initialization - task0 l_m_task0( + fulladder l_m_fulladder( .o_w_s(l_w_s), .o_w_cout(l_w_cout), .i_w_a(l_r_a), diff --git a/chapters/verilog/basic/drills/tasks/task0/tcl_files/build.tcl b/chapters/verilog/basic/drills/tasks/task0/tcl_files/build.tcl deleted file mode 100644 index 84e1832..0000000 --- a/chapters/verilog/basic/drills/tasks/task0/tcl_files/build.tcl +++ /dev/null @@ -1,8 +0,0 @@ -create_project build build_project -part xc7a100tcsg324-1 -force -import_files -force -fileset sources_1 -norecurse task01.v task0.v -import_files -force -fileset sim_1 -norecurse test_task0.v -import_files -force -fileset constrs_1 -norecurse task0.xdc -set_property top task0 [get_fileset sources_1] -set_property top test_task0 [get_fileset sim_1] -update_compile_order -fileset sources_1 -update_compile_order -fileset sim_1 diff --git a/chapters/verilog/basic/drills/tasks/task1/task1.v b/chapters/verilog/basic/drills/tasks/task1/task1.v deleted file mode 100644 index f9eba46..0000000 --- a/chapters/verilog/basic/drills/tasks/task1/task1.v +++ /dev/null @@ -1,16 +0,0 @@ -module task1( - output wire [3:0] o_w_s, - output wire o_w_cout, - input wire [3:0] i_w_a, - input wire [3:0] i_w_b, - input wire i_w_cin -); - - //TODO 1.1: Implement with 4 full-adders - wire [3:0] l_w_carry; - task0 l_m_task0_0 ( .o_w_s(o_w_s[0]), .o_w_cout(l_w_carry[0]), .i_w_a(i_w_a[0]), .i_w_b(i_w_b[0]), .i_w_cin(i_w_cin) ); - task0 l_m_task0_1 ( .o_w_s(o_w_s[1]), .o_w_cout(l_w_carry[1]), .i_w_a(i_w_a[1]), .i_w_b(i_w_b[1]), .i_w_cin(l_w_carry[0]) ); - task0 l_m_task0_2 ( .o_w_s(o_w_s[2]), .o_w_cout(l_w_carry[2]), .i_w_a(i_w_a[2]), .i_w_b(i_w_b[2]), .i_w_cin(l_w_carry[1]) ); - task0 l_m_task0_3 ( .o_w_s(o_w_s[3]), .o_w_cout(o_w_cout), .i_w_a(i_w_a[3]), .i_w_b(i_w_b[3]), .i_w_cin(l_w_carry[2]) ); - -endmodule \ No newline at end of file diff --git a/chapters/verilog/basic/drills/tasks/task1/tcl_files/build.tcl b/chapters/verilog/basic/drills/tasks/task1/tcl_files/build.tcl deleted file mode 100644 index 98914d8..0000000 --- a/chapters/verilog/basic/drills/tasks/task1/tcl_files/build.tcl +++ /dev/null @@ -1,8 +0,0 @@ -create_project build build_project -part xc7a100tcsg324-1 -force -import_files -force -fileset sources_1 -norecurse ../task0/task0.v ../task0/task01.v task1.v -import_files -force -fileset sim_1 -norecurse test_task1.v -import_files -force -fileset constrs_1 -norecurse task1.xdc -set_property top task1 [get_fileset sources_1] -set_property top test_task1 [get_fileset sim_1] -update_compile_order -fileset sources_1 -update_compile_order -fileset sim_1 diff --git a/chapters/verilog/basic/drills/tasks/task2/task2.v b/chapters/verilog/basic/drills/tasks/task2/task2.v deleted file mode 100644 index a9e1629..0000000 --- a/chapters/verilog/basic/drills/tasks/task2/task2.v +++ /dev/null @@ -1,12 +0,0 @@ -module task2( - output wire [6:0] o_w_s, - input wire [5:0] i_w_a, - input wire [5:0] i_w_b -); - - //TODO 3.1: Implement using - wire [1:0] l_w_carry; - task1 l_m_task1 ( .o_w_s(o_w_s[3:0]), .o_w_cout(l_w_carry[0]), .i_w_a(i_w_a[3:0]), .i_w_b(i_w_b[3:0]), .i_w_cin(1'b0) ); - task0 l_m_task0_0 ( .o_w_s(o_w_s[4]), .o_w_cout(l_w_carry[1]), .i_w_a(i_w_a[4]), .i_w_b(i_w_b[4]), .i_w_cin(l_w_carry[0]) ); - task0 l_m_task0_1 ( .o_w_s(o_w_s[5]), .o_w_cout(o_w_s[6]), .i_w_a(i_w_a[5]), .i_w_b(i_w_b[5]), .i_w_cin(l_w_carry[1]) ); -endmodule \ No newline at end of file diff --git a/chapters/verilog/basic/drills/tasks/task2/tcl_files/build.tcl b/chapters/verilog/basic/drills/tasks/task2/tcl_files/build.tcl deleted file mode 100644 index 3f75a75..0000000 --- a/chapters/verilog/basic/drills/tasks/task2/tcl_files/build.tcl +++ /dev/null @@ -1,8 +0,0 @@ -create_project build build_project -part xc7a100tcsg324-1 -force -import_files -force -fileset sources_1 -norecurse task2.v ../task1/task1.v ../task0/task0.v ../task0/task01.v -import_files -force -fileset sim_1 -norecurse test_task2.v -import_files -force -fileset constrs_1 -norecurse task2.xdc -set_property top task2 [get_fileset sources_1] -set_property top test_task2 [get_fileset sim_1] -update_compile_order -fileset sources_1 -update_compile_order -fileset sim_1 diff --git a/chapters/verilog/basic/drills/tasks/task3/tcl_files/build.tcl b/chapters/verilog/basic/drills/tasks/task3/tcl_files/build.tcl deleted file mode 100644 index 303c38c..0000000 --- a/chapters/verilog/basic/drills/tasks/task3/tcl_files/build.tcl +++ /dev/null @@ -1,8 +0,0 @@ -create_project build build_project -part xc7a100tcsg324-1 -force -import_files -force -fileset sources_1 -norecurse task3.v -import_files -force -fileset sim_1 -norecurse test_task3.v -import_files -force -fileset constrs_1 -norecurse task3.xdc -set_property top task3 [get_fileset sources_1] -set_property top test_task3 [get_fileset sim_1] -update_compile_order -fileset sources_1 -update_compile_order -fileset sim_1 diff --git a/config.yaml b/config.yaml index 5c34af8..40fa8d6 100644 --- a/config.yaml +++ b/config.yaml @@ -12,7 +12,7 @@ make_assets: options: command: make locations: - - chapters/template-chapter/template-topic/slides + - chapters/intro/soc/slides args: - all @@ -22,7 +22,7 @@ embed_reveal: target: docusaurus extension: mdx build: - template-chapter-template-topic: template-chapter-template-topic + intro: slides/intro docusaurus: plugin: docusaurus @@ -45,6 +45,13 @@ docusaurus: - Simulare Vivado/: simulation/ - Programare FPGA Vivado/: programming/ - Rulare exemple practice/: runtasks/ + - Docker: + path: docker/ + extra: + - media/ + subsections: + - Windows/: windows/ + - Linux/: linux/ - Laboratoare: - 0 Recapitulare: - Circuite combinaționale: @@ -178,9 +185,13 @@ docusaurus: - media/ subsections: - Teorie/: reading/ + - Curs: + path: /build/embed_reveal + subsections: + - 0 Introducere: intro/intro.mdx static_assets: - - template-chapter-template-topic: /build/make_assets/chapters/template-chapter/template-topic/slides/_site + - slides/intro: /build/make_assets/chapters/intro/soc/slides/_site config_meta: title: Computer Architecture url: http://localhost/