diff --git a/chapters/verilog/behavioral/drills/tasks/alu/alu.v b/chapters/verilog/behavioral/drills/tasks/alu/alu.v
index 118d138..d6a72b6 100644
--- a/chapters/verilog/behavioral/drills/tasks/alu/alu.v
+++ b/chapters/verilog/behavioral/drills/tasks/alu/alu.v
@@ -1,4 +1,4 @@
-module task2 #(
+module alu #(
     parameter p_width = 4
 ) (
     output wire [((2*p_width)-1):0] o_w_out,
diff --git a/chapters/verilog/behavioral/drills/tasks/alu/tcl_files/build.tcl b/chapters/verilog/behavioral/drills/tasks/alu/tcl_files/build.tcl
index 43e4e2c..af8b439 100644
--- a/chapters/verilog/behavioral/drills/tasks/alu/tcl_files/build.tcl
+++ b/chapters/verilog/behavioral/drills/tasks/alu/tcl_files/build.tcl
@@ -1,8 +1,8 @@
 create_project build build_project -part xc7a100tcsg324-1 -force
-import_files -force -fileset sources_1 -norecurse adder.v task2.v ../multiplier/multiplier.v
-import_files -force -fileset sim_1 -norecurse test_task2.v
-import_files -force -fileset constrs_1 -norecurse task2.xdc
-set_property top task2 [get_fileset sources_1]
-set_property top test_task2 [get_fileset sim_1]
+import_files -force -fileset sources_1 -norecurse adder.v alu.v ../multiplier/multiplier.v
+import_files -force -fileset sim_1 -norecurse test_alu.v
+import_files -force -fileset constrs_1 -norecurse alu.xdc
+set_property top alu [get_fileset sources_1]
+set_property top test_alu [get_fileset sim_1]
 update_compile_order -fileset sources_1
 update_compile_order -fileset sim_1