How to pass Yosys defines to synthesis using symbiflow_synth flow

[carlosedp]

I have a project where I need to pass a synthesis define due to an ifdef in the code. Using Trellis it works fine but using the symbiflow_synth, symbiflow_pack, etc flow it apparently have no way to do this.

One option I tried is passing a surelog parameter using +define+PARAM=1 but this apparently uses a different plugin which fails in the symbiflow_pack afterwards.

Using the surelog flag, I get the error below in the pack command:

Message: Clock name or pattern 'pll.clki' does not correspond to any nets. To create a virtual clock, use the '-name' option.
The entire flow of VPR took 12.97 seconds (max_rss 89.9 MiB)
Traceback (most recent call last):
  File "/usr/local/envs/xc7/bin/symbiflow_pack", line 8, in <module>
    sys.exit(pack())
  File "/usr/local/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/__init__.py", line 500, in pack
    p_vpr_run(["--pack"] + extra_args, env=p_vpr_env_from_args("pack"))
  File "/usr/local/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/__init__.py", line 135, in p_vpr_run
    + args,
  File "/usr/local/envs/xc7/lib/python3.7/subprocess.py", line 363, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['/usr/local/envs/xc7/bin/vpr', '/usr/local/share/f4pga/arch/xc7a50t_test/arch.timing.xml', 'Toplevel.eblif', '--max_router_iterations', '500', '--routing_failure_predictor', 'off', '--router_high_fanout_threshold', '-1', '--constant_net_method', 'route', '--route_chan_width', '500', '--router_heap', 'bucket', '--clock_modeling', 'route', '--place_delta_delay_matrix_calculation_method', 'dijkstra', '--place_delay_model', 'delta', '--router_lookahead', 'extended_map', '--check_route', 'quick', '--strict_checks', 'off', '--allow_dangling_combinational_nodes', 'on', '--disable_errors', 'check_unbuffered_edges:check_route', '--congested_routing_iteration_threshold', '0.8', '--incremental_reroute_delay_ripup', 'off', '--base_cost_type', 'delay_normalized_length_bounded', '--bb_factor', '10', '--acc_fac', '0.7', '--astar_fac', '1.8', '--initial_pres_fac', '2.828', '--pres_fac_mult', '1.2', '--check_rr_graph', 'off', '--suppress_warnings', 'noisy_warnings-xc7a50t_test_pack.log,sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment:calculate_average_switch', '--device', 'xc7a50t-test', '--read_rr_graph', '/usr/local/share/f4pga/arch/xc7a50t_test/rr_graph_xc7a50t_test.rr_graph.real.bin', '--read_router_lookahead', '/usr/local/share/f4pga/arch/xc7a50t_test/rr_graph_xc7a50t_test.lookahead.bin', '--read_placement_delay_lookup', '/usr/local/share/f4pga/arch/xc7a50t_test/rr_graph_xc7a50t_test.place_delay.bin', '--pack']' returned non-zero exit status 1.

This doesn't happen if not using the surelog plugin.

In my project, I use the Fusesoc/Edalize tooling.