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Please provide the steps to reproduce the problem:
//>usingscala"2.13.12"//>usingdep"org.chipsalliance::chisel:6.5.0"//>usingplugin"org.chipsalliance:::chisel-plugin:6.5.0"//>usingoptions"-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"importchisel3._importchisel3.util.PriorityMux// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._import_root_.circt.stage.ChiselStageclassFooextendsModule {
vala, b, c=IO(Input(Bool()))
valfoo, bar, fizz=IO(Input(UInt(8.W)))
valout=IO(Output(UInt(8.W)))
out :=PriorityMux(Seq(a, b), Seq(foo, bar, fizz))
}
objectMainextendsApp {
println(
ChiselStage.emitSystemVerilog(
gen =newFoo,
firtoolOpts =Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
What is the current behavior?
This generates:
// Generated by CIRCT firtool-1.62.0moduleFoo(
input clock,
reset,
a,
b,
c,
input [7:0] foo,
bar,
fizz,
output [7:0] out
);
assign out = a ? foo : bar;
endmodule
What is the expected behavior?
This should either error, or function correctly because technically the last select bit is just dropped anyway. But it definitely shouldn't just incorrectly drop fizz.
Please tell us about your environment:
Other Information
What is the use case for changing the behavior?
The text was updated successfully, but these errors were encountered:
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
What is the current behavior?
This generates:
What is the expected behavior?
This should either error, or function correctly because technically the last
select
bit is just dropped anyway. But it definitely shouldn't just incorrectly dropfizz
.Please tell us about your environment:
Other Information
What is the use case for changing the behavior?
The text was updated successfully, but these errors were encountered: