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SyncReadMem ruw (ReadUnderWrite) parameter has no effect #4433
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This was never implemented in CIRCT and, hence, this always incorrectly compiles to write first. There's an old tracking issue here: llvm/circt#787 CIRCT passes should handle this if we are going to support it or the option should be dropped from Chisel. It shouldn't be that bad to just support it in CIRCT. |
I think we should remove or at least deprecate this and back port as bug fix to avoid misunderstanding. |
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Type of issue: Bug Report
Please provide the steps to reproduce the problem:
Generate verilog for the code below using different values for the last parameter (
ruw
) of theSyncReadMem
callWhat is the current behavior?
The generated verilog code always behaves as WriteFirst. If a memory entry is read and written in the same clock cycle, the read data gets the newly written value in the next cycle.
The important parts of the generated verilog code is:
What is the expected behavior?
The generated verilog should behave as specified by the
ruw
parameter, or as described in the Chisel Memories documentation whenruw
is not specified.Please tell us about your environment:
6.5
1.9.8
Other Information
What is the use case for changing the behavior?
It should be possible to simulate SRAMs with different read/write conflict behaviour without replacing the memories with vendor models.
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