Probe color should be checked for read

[dtzSiFive]

Type of issue: Bug Report

scala-cli demonstration:

//> using repository "sonatype-s01:snapshots"
//> using scala "2.13.14"
//> using dep "org.chipsalliance::chisel:7.0.0-M2+76-ecda00a5-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin:7.0.0-M2+76-ecda00a5-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.layer.{Layer, LayerConfig}
import circt.stage.ChiselStage
import chisel3.probe.{define, read, Probe, ProbeValue}

object LayerA extends Layer(LayerConfig.Extract())

class Foo extends RawModule {
  val x = IO(Output(Probe(Bool(), LayerA)))
  val xval = IO(Output(Bool()))
  val a = WireInit(Bool(), true.B)
  layer.block(LayerA) {
    define(x, ProbeValue(a))
  }

  // Should be illegal.
  xval := read(x)
}

object Main extends App {
  println(ChiselStage.emitCHIRRTL(new Foo))
  println(ChiselStage.emitSystemVerilog(new Foo))
}

What is the current behavior?

Chisel execution completes without issue, error is caught in firtool (invoked by emitSystemVerilog):

probe-read.scala:23:8: error: 'firrtl.ref.resolve' op ambient layers are insufficient to resolve reference
probe-read.scala:23:8: note: see current operation: %3 = "firrtl.ref.resolve"(%arg0) : (!firrtl.probe<uint<1>, @LayerA>) -> !firrtl.uint<1>
probe-read.scala:23:8: note: missing layer requirements: @LayerA

What is the expected behavior?

Chisel checks if safe to read from probe based on current/ambient coloring.

What is the use case for changing the behavior?

Better user experience.