为什么在声明Wire/Reg的时候需要考虑Bundle的方向?(If a bundle is declared as an IO, it is necessary to specify all directions, but is it possible to declare Wire/Reg without considering the directions?)

[qinjun-li]

下面两个是我列出来的例子(The following two examples are the ones I listed):
https://scastie.scala-lang.org/Chester-li/6jiKgO9iTSyvuW1ZAp5LEg/25
https://scastie.scala-lang.org/Chester-li/ma08XbfXSvKvmefVGnOb7Q/3

它会报错(It will report an error):

chisel3.package$MixedDirectionAggregateException: Aggregate 'TestBundle(Wire in Test)' can't have elements that are both directioned and undirectioned: Vector((UInt<10>(Wire in Test),Unspecified), (Valid(Wire in Test),Output))

按照它的报错我需要将bundle里面的成员方向全部明确, 就是改成(According to its error, I need to clarify the direction of all the members in the bundle, that is, change it to):

class TestBundle extends Bundle {
  val testValidIO: ValidIO[UInt] = Valid(UInt(4.W))
  val elseData: UInt = Output(UInt(10.W))
}

如果是将bundle声明为一个IO, 是必须要明确所有方向的, 但是在声明 Wire/Reg 的时候是不是可以不需要考虑方向?(If a bundle is declared as an IO, it is necessary to specify all directions, but is it possible to declare Wire/Reg without considering the directions?)

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Translations are directly copy&paste form DeepL.

[sequencer]

I personally think this is reasonable. cc @jackkoenig
This error is from:
https://github.com/chipsalliance/chisel3/blob/c5861176887bfa529277e686df09a42aeceb6cd7/core/src/main/scala/chisel3/Aggregate.scala#L37-L45

Maybe it will be possible to move this validation to IO?

[edwardcwang]

Can't one use something like Input() or Output() to coerce away the issue?

[sequencer]

This should work. But I think it’s just a work around which might confuse users. Why Input keyword should be appended in a Wire or Reg

[sequencer]

Copy&Paste from answer from @jackkoenig in the dev meeting:

Valid(...) is wrong, it assigns directions (Output) when it shouldn’t
Would like to fix this but it’s hard
Deprecate and remove (could add chisel3.Valid and deprecate chisel3.util.Valid)
Could add chisel3 internal way of marking “Is output but deprecated” and make Valid use it (basically tells you to wrap it in Output when used in directioned Bundles) -- basically could not have to deprecate chisel3.util.Valid but requires hacking on internals
It’s totally true that it’s weird to have to use Input/Output to coerce directions for an internal wire or reg, we could add NoDir(...) or .noDir or something
We could do this automatically for Reg or Memory but definitely should not for Wire
Should bidirectional registers be illegal (as they are?)
For internal signals, FIRRTL’s notion of “flipped” vs. “not flipped” makes more sense than our use of Input and Output, this is a bit of a regression from Chisel2 which allowed you to just .flip something