i8051_top.stx

Release 14.2 - xst P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.18 secs
 
--> Parameter xsthdpdir set to C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.18 secs
 
--> WARNING:Xst:3164 - Option "-debug" found multiple times in the command line. Only the first occurence is considered.

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/constants.vhd" in Library work.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/ext_interrupt.vhd" in Library work.
Architecture behavioral of Entity ext_interrupt is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/csadder.vhd" in Library work.
Architecture csadderbeh of Entity csadder is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/sequencer2.vhd" in Library work.
Architecture seq_arch of Entity sequencer2 is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/fastalu.vhd" in Library work.
Architecture fastalu_arch of Entity fastalu is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/regfile.vhd" in Library work.
Architecture regarch of Entity regfile is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/multiplier.vhd" in Library work.
Architecture rtl of Entity multiplier is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/int_rom.vhd" in Library work.
Entity <int_rom> compiled.
Entity <int_rom> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/int_ram.vhd" in Library work.
Architecture syn of Entity internal_ram is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/divider.vhd" in Library work.
Architecture rtl of Entity divider is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/int_handler.vhd" in Library work.
Architecture behavioral of Entity int_handler is up to date.
Compiling vhdl file "C:/Users/Angad Singh/Downloads/1 Trying S1S6/Lab1/8051_top_fpga.vhd" in Library work.
Architecture behavioral of Entity i8051_top is up to date.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.49 secs
 
--> 

Total memory usage is 173984 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)