rb_registers.xml

<?xml version="1.0" encoding="UTF-8"?>
<node>
    <node id="DRS"  address="0x0000"
    description="Implements various control and monitoring functions of the DRS Logic"
    fw_is_module="true"
    fw_use_tmr="true"
    fw_module_file="../drs/src/daq_board_top.vhd"
    fw_user_clock_signal="clock"
    fw_bus_clock_signal="ipb_clk"
    fw_bus_reset_signal="ipb_reset"
    fw_master_bus_signal="ipb_mosi_arr(0)"
    fw_slave_bus_signal="ipb_miso_arr(0)"
    fw_reg_addr_msb="9"
    fw_reg_addr_lsb="0">

        <node id="CHIP" address="0x0" description="Registers for configuring the DRS ASIC Directly">
            <node id="DMODE" address="0x0" permission="rw"
                description="set 1 = continuous domino, 0=single shot"
                mask="0x2"
                fw_signal="drs_dmode"
                fw_default="0x1"/>
            <node id="STANDBY_MODE" address="0x0" permission="rw"
                description="set 1 = shutdown drs"
                mask="0x4"
                fw_signal="drs_standby_mode"
                fw_default="0x0"/>
            <node id="TRANSPARENT_MODE" address="0x0" permission="rw"
                description="set 1 = transparent mode"
                mask="0x8"
                fw_signal="drs_transp_mode"
                fw_default="0x0"/>
            <node id="DRS_PLL_LOCK" address="0x0" permission="r"
                description="DRS PLL Locked"
                mask="0x10"
                fw_signal="drs_plllock_i" />
            <node id="CHANNEL_CONFIG" address="0x0" permission="rw"
                description="Write Shift Register Configuration
                            \\ # of chn - # of cells per ch - bit pattern
                            \\ 8        - 1024              - 11111111b
                            \\ 4        - 2048              - 01010101b
                            \\ 2        - 4096              - 00010001b
                            \\ 1        - 8192              - 00000001b"

                mask="0xff000000"
                fw_signal="chn_config"
                fw_default="0xff"/>
            <node id="DTAP_FREQ" address="0x1" permission="r"
                description="Frequency of DTAP in units of 100Hz"
                mask="0x0000ffff"
                fw_signal="dtap_cnt" />
            <node id="CLK_IDELAY" address="0x2" permission="rw"
                description="DRS CLK IDELAY Setting 0-31 in 78 ps increments"
                mask="0x1f"
                fw_default="0x0f"
                fw_signal="clock_tap_delays" />
            <node id="CYLON_MODE" address="0x3" permission="rw"
                description="1 for cylon mode"
                mask="0x1"
                fw_default="0x0"
                fw_signal="cylon_mode" />
            <node id="START_TIMER" address="0x3" permission="rw"
                description="Number of clock cycles to delay before allowing triggers."
                mask="0xff0"
                fw_default="105"
                fw_signal="drs_ctl_start_timer"/>
            <node id="LOSS_OF_LOCK" address="0x4" permission="r"
                description="Raw reading of LOL signal"
                mask="0x1"
                fw_signal="loss_of_lock_i" />
            <node id="LOSS_OF_LOCK_STABLE" address="0x4" permission="r"
                description="Loss of lock stable over the past ~second"
                mask="0x2"
                fw_signal="lock_stable" />

        </node> <!--CONFIG-->

        <node id="READOUT" address="0x10" description="Registers for configuring the readout state machine">

            <node id="ROI_MODE" address="0x0" permission="rw"
                description="Set to 1 to enable Region of Interest Readout"
                mask="0x1"
                fw_signal="drs_roi_mode"
                fw_default="0x1"/>
            <node id="BUSY" address="0x0" permission="r"
                description="DRS is busy"
                mask="0x2"
                fw_signal="drs_busy" />
            <node id="ADC_LATENCY" address="0x0" permission="rw"
                description="Latency from first sr clock to when ADC data should be valid"
                mask="0x3f0"
                fw_signal="adc_latency"
                fw_default="0x9"/>
            <node id="SAMPLE_COUNT" address="0x0" permission="rw"
                description="Number of samples to read out (0 to 1023)"
                mask="0x3ff000"
                fw_signal="sample_count_max"
                fw_default="0x3FF"/>
            <node id="EN_SPIKE_REMOVAL" address="0x0" permission="rw"
                description="set 1 to enable spike removal"
                mask="0x400000"
                fw_signal="drs_spike_removal"
                fw_default="0x1"/>


            <node id="READOUT_MASK" address="0x1" permission="rw"
                description="8 bit mask, set a bit to 1 to enable readout of that channel. 9th is auto-read if any channel is enabled *and* AUTO_9TH_CHANNEL set to 1"
                mask="0x1ff"
                fw_signal="readout_mask_axi"
                fw_default="0x1ff"/>
            <node id="AUTO_9TH_CHANNEL" address="0x1" permission="rw"
                description="Set to 1 to auto read the 9th channel"
                mask="0x200"
                fw_signal="readout_mask_9th_channel_auto"
                fw_default="0x1"/>
            <node id="START" address="0x2" permission="w"
                description="Write 1 to take the state machine out of idle mode"
                mask="0x1"
                fw_write_pulse_signal="drs_start"/>

            <node id="REINIT" address="0x3" permission="w"
                description="Write 1 to reinitialize DRS state machine (restores to idle state)"
                mask="0x1"
                fw_write_pulse_signal="drs_reinit" />

            <node id="CONFIGURE" address="0x4" permission="w"
                description="Write 1 to configure the DRS. Should be done before data taking"
                mask="0x1"
                fw_write_pulse_signal="drs_configure"/>

            <node id="DRS_RESET" address="0x5" permission="w"
                description="Write 1 to completely reset the DRS state machine logic"
                mask="0x1"
                fw_write_pulse_signal="drs_reset" />
            <node id="DAQ_RESET" address="0x6" permission="w"
                description="Write 1 to completely reset the DAQ state machine logic"
                mask="0x1"
                fw_write_pulse_signal="daq_reset" />
            <node id="DMA_RESET" address="0x7" permission="w"
                description="Write 1 to completely reset the DMA state machine logic"
                mask="0x1"
                fw_write_pulse_signal="dma_control_reset"/>

            <node id="WAIT_VDD_CLKS" address="0x8" permission="rw"
                description="Number of ADC clocks to wait before reading out the drs, allowing vdd to stabilize; default=0x14d=10us"
                mask="0xffff"
                fw_default="0x14d"
                fw_signal="wait_vdd_clocks"/>

            <node id="DRS_DIAGNOSTIC_MODE" address="0x9" permission="rw"
                description="1 will make the DRS read out the cell ID instead of ADC data"
                mask="0x1"
                fw_default="0x0"
                fw_signal="drs_diagnostic_mode"/>

            <node id="POSNEG" address="0xA" permission="rw"
                description="1 to sample on positive edge, 0 on negative"
                mask="0x1"
                fw_default="0x0"
                fw_signal="adc_posneg"/>

            <node id="SROUT_POSNEG" address="0xA" permission="rw"
                description="1 to sample on positive edge, 0 on negative"
                mask="0x2"
                fw_default="0x0"
                fw_signal="srout_posneg"/>

            <node id="SROUT_LATENCY" address="0xA" permission="rw"
                description="Latency of the SROUT readout"
                mask="0x70"
                fw_default="0x2"
                fw_signal="srout_latency"/>

            <node id="DMA_CLEAR" address="0xB" permission="w"
                description="Write 1 to clear the DMA memory (write zeroes)"
                mask="0x1"
                fw_write_pulse_signal="dma_clear"/>

            <node id="SOFT_RESET" address="0xC" permission="w"
                description="Write 1 to soft reset the readout buffers."
                mask="0x1"
                fw_write_pulse_signal="soft_reset"/>

            <node id="SOFT_RESET_DONE" address="0xD" permission="r"
                description="Soft reset is finished."
                mask="0x8000"
                fw_signal="soft_reset_done"/>

            <node id="SOFT_RESET_DRS_EN" address="0xD" permission="rw"
                description="Soft reset DRS."
                mask="0x0001"
                fw_signal="soft_reset_drs_en"
                fw_default="0x0" />

            <node id="SOFT_RESET_DAQ_EN" address="0xD" permission="rw"
                description="Soft reset DAQ."
                mask="0x0002"
                fw_signal="soft_reset_daq_en"
                fw_default="0x0" />

            <node id="SOFT_RESET_DMA_EN" address="0xD" permission="rw"
                description="Soft reset DMA."
                mask="0x0004"
                fw_signal="soft_reset_dma_en"
                fw_default="0x1" />

            <node id="SOFT_RESET_PTR_EN" address="0xD" permission="rw"
                description="Soft reset occupancy pointer."
                mask="0x0008"
                fw_signal="soft_reset_ptr_en"
                fw_default="0x1" />

            <node id="SOFT_RESET_BUF_EN" address="0xD" permission="rw"
                description="Soft reset buffers."
                mask="0x0020"
                fw_signal="soft_reset_buf_en"
                fw_default="0x1" />

            <node id="SOFT_RESET_WAIT_DRS" address="0xD" permission="rw"
                description="Wait for DRS to idle."
                mask="0x0100"
                fw_signal="soft_reset_wait_drs"
                fw_default="0x1" />

            <node id="SOFT_RESET_WAIT_DAQ" address="0xD" permission="rw"
                description="Wait for DAQ to idle."
                mask="0x0200"
                fw_signal="soft_reset_wait_daq"
                fw_default="0x1" />

            <node id="SOFT_RESET_WAIT_DMA" address="0xD" permission="rw"
                description="Wait for DMA to idle."
                mask="0x0400"
                fw_signal="soft_reset_wait_dma"
                fw_default="0x1" />

            <node id="SOFT_RESET_WATCHDOG_EN" address="0xE" permission="rw"
                description="Enable a watchdog timer for the soft reset module."
                mask="0x0800"
                fw_signal="soft_reset_watchdog_en"
                fw_default="0x1"/>

            <node id="DRS_DEADTIME" address="0xE" permission="r"
                description="Measured last deadtime of the DRS in clock cycles"
                mask="0xFFFF"
                fw_signal="std_logic_vector(to_unsigned(drs_busy_timer_stable, 16))"/>

        </node> <!--READOUT-->


        <node id="FPGA" address="0x020" description="FPGA Status">

            <node id="DNA" address="0x0"
                description="FPGA Device DNA">
                <node id="DNA_LSBS" address="0x0" permission="r"
                    description="Device DNA [31:0]"
                    mask="0xffffffff"
                    fw_signal="dna (31 downto 0)" />

                <node id="DNA_MSBS" address="0x1" permission="r"
                    description="Device DNA [56:32]"
                    mask="0x1ffffff"
                    fw_signal="dna (56 downto 32)" />
            </node> <!--DNA-->

            <node id="TIMESTAMP" address="0x4"
                description="Timestamp">
                <node id="TIMESTAMP_LSBS" address="0x0" permission="r"
                    description="Device TIMESTAMP [31:0]"
                    mask="0xffffffff"
                    fw_signal="std_logic_vector(timestamp (31 downto 0))" />

                <node id="TIMESTAMP_MSBS" address="0x1" permission="r"
                    description="Device TIMESTAMP [47:32]"
                    mask="0x0000ffff"
                    fw_signal="std_logic_vector(timestamp (47 downto 32))" />
            </node> <!--TIMESTAMP-->

            <node id="XADC" address="0x6"
                  description="Zynq XADC">
                <node id="CALIBRATION" address="0x0" permission="r"
                      description="XADC Calibration"
                      mask="0x00000fff"
                      fw_signal="calibration" />
                <node id="VCCPINT" address="0x0" permission="r"
                      description="XADC vccpint"
                      mask="0x0fff0000"
                      fw_signal="vccpint"/>
                <node id="VCCPAUX" address="0x1" permission="r"
                      description="XADC Calibration"
                      mask="0x00000fff"
                      fw_signal="vccpaux" />
                <node id="VCCODDR" address="0x1" permission="r"
                      description="XADC vccoddr"
                      mask="0x0fff0000"
                      fw_signal="vccoddr"/>
                <node id="TEMP" address="0x2" permission="r"
                      description="XADC Temperature"
                      mask="0x00000fff"
                      fw_signal="temp" />
                <node id="VCCINT" address="0x2" permission="r"
                      description="XADC vccint"
                      mask="0x0fff0000"
                      fw_signal="vccint"/>
                <node id="VCCAUX" address="0x3" permission="r"
                      description="XADC VCCAUX"
                      mask="0x00000fff"
                      fw_signal="vccaux" />
                <node id="VCCBRAM" address="0x3" permission="r"
                      description="XADC vccbram"
                      mask="0x0fff0000"
                      fw_signal="vccbram"/>
            </node> <!--XADC-->

            <node id="BOARD_ID" address="0xA" permission="rw"
                  description="Board ID Number"
                  mask="0xff"
                  fw_default="0x00"
                  fw_signal="board_id"/>

            <node id="DRS_TEMP" address="0xB" permission="rw"
                  description="Copy of the I2C DRS temperature reading"
                  mask="0x0000ffff"
                  fw_default="0x3039"
                  fw_signal="drs_temp" />

            <node id="RAT_HOUSEKEEPING" address="0xC" permission="rw"
                  description="32 bit RAT housekeeping data. Meaning is software defined."
                  mask="0xffffffff"
                  fw_signal="rat_housekeeping"
                  fw_default="0x00000000"/>

        </node> <!--FPGA-->


        <node id="DAQ" address="0x30"
            description="DAQ">
            <node id="INJECT_DEBUG_PACKET" address="0x0" permission="w"
                description="Injects a fixed format debug packet into the DAQ"
                mask="0x1"
                fw_write_pulse_signal="debug_packet_inject" />
            <node id="DAQ_FRAGMENT_EN" address="0x1" permission="rw"
                description="1 to enable daq fragments (header only packets) when the DRS is busy"
                mask="0x1"
                fw_default="0x0"
                fw_signal="daq_fragment_en" />
            <node id="DAQ_BUSY" address="0x1" permission="r"
                description="1 = DAQ is still busy reading out"
                mask="0x2"
                fw_signal="daq_busy" />
        </node> <!--DAQ-->

        <node id="TRIGGER" address="0x40"
            description="Trigger">
            <node id="FORCE_TRIGGER" address="0x0" permission="w"
                description="Generates a trigger"
                mask="0x1"
                fw_write_pulse_signal="force_trig" />
            <node id="EXT_TRIGGER_EN" address="0x1" permission="rw"
                description="Set to 1 to enable the external trigger"
                fw_default="0x0"
                mask="0x1"
                fw_signal="ext_trigger_en" />
            <node id="EXT_TRIGGER_ACTIVE_HI" address="0x1" permission="rw"
                description="Set to 1 for active high external trigger"
                fw_default="0x1"
                mask="0x2"
                fw_signal="ext_trigger_active_hi" />
            <node id="MT_TRIGGER_IS_LEVEL" address="0x1" permission="rw"
                description="Set to 1 for mt level trigger on v2.4 boards"
                fw_default="0x0"
                mask="0x4"
                fw_signal="mt_is_level_trigger" />
            <node id="MT_LINK_ID" address="0x1" permission="r"
                description="MT Link ID Received from MTB"
                mask="0x1f8"
                fw_signal="mt_link_id" />
            <node id="CNT_MT_PRBS_ERRS" address="0x3" permission="r"
                description="Number of PRBS errors on the MT line"
                mask="0xffffffff"
                fw_cnt_reset_signal="mt_prbs_rst"
                fw_cnt_en_signal="mt_prbs_err or mt_inactive"
                fw_signal="cnt_mt_prbs_err"/>
            <node id="MT_PRBS_ERR_RESET" address="0x4" permission="w"
                description="Write 1 to reset the MT PRBS Error Counter"
                mask="0x1"
                fw_write_pulse_signal="mt_prbs_rst" />
            <node id="MT_TRIGGER_MODE" address="0x5" permission="rw"
                description="1 to use the MT as the source of the trigger"
                mask="0x1"
                fw_default="0x0"
                fw_signal="mt_trigger_mode" />
            <node id="CNT_MT_CRC_ERR" address="0x6" permission="r"
                description="Number of MT CRC errors"
                mask="0xffff"
                fw_cnt_reset_signal="reset or cnt_reset"
                fw_cnt_en_signal="not mt_crc_ok and mt_crc_valid"
                fw_signal="cnt_mt_crc_err"/>
            <node id="TRIGGER_ENABLE" address="0x7" permission="rw"
                description="Set to 0 to stop all triggers. 1 to enable triggers."
                fw_default="0x0"
                mask="0x1"
                fw_signal="trigger_enable" />
            <node id="MT_EVENT_CNT" address="0x8" permission="r"
                description="Recevied event counter"
                mask="0xffffffff"
                fw_signal="mt_event_cnt" />
            <node id="MT_TRIGGER_RATE" address="0x9" permission="r"
                description="Rate of triggers received from the MTB in Hz"
                mask="0xffffffff"
                fw_signal="mt_trigger_rate"/>
        </node> <!--TRIGGER-->

        <node id="COUNTERS" address="0x50" description="Counters">
            <node id="CNT_SEM_CORRECTION" address="0x0" permission="r"
                description="Number of Single Event Errors corrected by the scrubber"
                mask="0xffff"
                fw_cnt_reset_signal="reset or cnt_reset"
                fw_cnt_en_signal="sem_correction"
                fw_signal="cnt_sem_corrected"/>

            <node id="CNT_SEM_UNCORRECTABLE" address="0x1" permission="r"
                description="Number of Critical Single Event Errors (uncorrectable by scrubber)"
                mask="0xf0000"
                fw_cnt_reset_signal="reset or cnt_reset"
                fw_cnt_en_signal="sem_uncorrectable_error"
                fw_signal="cnt_sem_uncorrectable"/>

            <node id="CNT_READOUTS_COMPLETED" address="0x2" permission="r"
                description="Number of readouts completed since reset"
                mask="0xffffffff"
                fw_cnt_reset_signal="reset or cnt_reset"
                fw_cnt_en_signal="readout_complete"
                fw_signal="cnt_readouts"/>

            <node id="CNT_DMA_READOUTS_COMPLETED" address="0x3" permission="r"
                description="Number of readouts completed since reset"
                mask="0xffffffff"
                fw_signal="dma_packet_counter"/>

            <node id="CNT_LOST_EVENT" address="0x4" permission="r"
                description="Number of trigger lost due to deadtime"
                mask="0xffff0000"
                fw_cnt_reset_signal="reset or cnt_reset"
                fw_cnt_en_signal="trigger and drs_busy"
                fw_signal="cnt_lost_events"/>

            <node id="CNT_EVENT" address="0x5" permission="r"
                description="Number of triggers received"
                mask="0xffffffff"
                fw_cnt_en_signal="trigger"
                fw_cnt_reset_signal="reset or cnt_reset"
                fw_signal="event_counter"/>

            <node id="TRIGGER_RATE" address="0x6" permission="r"
                description="Rate of triggers in Hz"
                mask="0xffffffff"
                fw_signal="trigger_rate"/>

            <node id="LOST_TRIGGER_RATE" address="0x7" permission="r"
                description="Rate of lost triggers in Hz"
                mask="0xffffffff"
                fw_signal="lost_trigger_rate"/>

            <node id="CNT_RESET" address="0x8" permission="w"
                description="Reset the counters"
                mask="0x1"
                fw_write_pulse_signal="cnt_reset"/>

        </node> <!--COUNTERS-->

        <node id="TRIG_GEN_RATE" address="0x59" permission="rw"
              description="Rate of generated triggers f_trig = (1/clk_period) * rate/0xffffffff"
              mask="0xffffffff"
              fw_default="0x0"
              fw_signal="trig_gen_rate"/>

        <node id="HOG" address="0x60" description = "HOG Parameters">
            <node id="GLOBAL_DATE" mask="0xFFFFFFFF" permission="r" address="0x0" description="HOG Global Date"    fw_signal="GLOBAL_DATE"/>
            <node id="GLOBAL_TIME" mask="0xFFFFFFFF" permission="r" address="0x1" description="HOG Global Time"    fw_signal="GLOBAL_TIME"/>
            <node id="GLOBAL_VER"  mask="0xFFFFFFFF" permission="r" address="0x2" description="HOG Global Version" fw_signal="GLOBAL_VER"/>
            <node id="GLOBAL_SHA"  mask="0xFFFFFFFF" permission="r" address="0x3" description="HOG Global SHA"     fw_signal="GLOBAL_SHA"/>
            <node id="REPO_SHA"    mask="0xFFFFFFFF" permission="r" address="0x4" description="HOG Repo SHA"       fw_signal="REPO_SHA"/>
            <node id="TOP_VER"     mask="0xFFFFFFFF" permission="r" address="0x5" description="HOG Repo Version"   fw_signal="REPO_VER"/>
            <node id="HOG_SHA"     mask="0xFFFFFFFF" permission="r" address="0x6" description="HOG SHA"            fw_signal="HOG_SHA"/>
            <node id="HOG_VER"     mask="0xFFFFFFFF" permission="r" address="0x7" description="HOG Version"        fw_signal="HOG_VER"/>
        </node> <!--HOG-->

        <node id="CNT_SNAP" address="0x80" permission="w"
              description="1 to freeze counters for readout"
              mask="0x1"
              fw_write_pulse_signal="cnt_snap"/>

        <node id="CNT_SNAP_DIS" address="0x80" permission="w"
              description="1 disables counter snapping; values continuously update"
              mask="0x2"
              fw_default="0x1"
              fw_signal="cnt_snap_dis"/>

        <node id="CNT_START_READOUT" address="0x81" permission="r"
              description="Count the number of times the DRS readout has started"
              mask="0xffffffff"
              fw_cnt_snap_signal="cnt_snap or cnt_snap_dis"
              fw_cnt_en_signal="start_readout"
              fw_cnt_reset_signal="reset or cnt_reset"
              fw_signal="start_readout_counter"/>

        <node id="CNT_EVENT_WR_EN" address="0x82" permission="r"
              description="Count the number of times the event queue has been written to"
              mask="0xffffffff"
              fw_cnt_snap_signal="cnt_snap or cnt_snap_dis"
              fw_cnt_en_signal="event_queue_wr_en"
              fw_cnt_reset_signal="reset or cnt_reset"
              fw_signal="event_queue_wr_counter"/>

        <node id="AUTO_PURGE_MODE" address="0x83" permission="rw"
              description="1 for the DAQ to automatically purge any remaining data from the DRS fifo after readout"
              mask="0x1"
              fw_default="0x0"
              fw_signal="auto_purge_mode"/>

        <node id="DMA" address="0x100" description = "DMA and ram buffer occupancy">
            <node id="RAM_A_OCC_RST"   permission="w" address="0x0" mask="0x00000001" description="Sets RAM buffer a counter to 0" fw_write_pulse_signal="ram_a_occ_rst"/>
            <node id="RAM_B_OCC_RST"   permission="w" address="0x1" mask="0x00000001" description="Sets RAM buffer b counter to 0" fw_write_pulse_signal="ram_b_occ_rst"/>
            <node id="RAM_A_OCCUPANCY" permission="r" address="0x2" mask="0xFFFFFFFF" description="RAM buffer a occupancy"  fw_signal="ram_buff_a_occupancy"/>
            <node id="RAM_B_OCCUPANCY" permission="r" address="0x3" mask="0xFFFFFFFF" description="RAM buffer b occupancy"  fw_signal="ram_buff_b_occupancy"/>
            <node id="DMA_POINTER"     permission="r" address="0x4" mask="0xFFFFFFFF" description="DMA controller pointer"  fw_signal="dma_pointer"/>
            <node id="TOGGLE_RAM"      permission="w" address="0x5"  description="Write 1 to switch the dma buffer to the other half" mask="0x1" fw_write_pulse_signal="ram_toggle_request" />
        </node>
    </node>
</node>