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0205-2024-05-30.md

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30 May 2024

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Very rough update for a few different days of experimentation

Assume raybox-zero versions:

  • 1.0: TT04
  • 1.3: EW (CI2311)
  • 1.4: GFMPW-1
  • 1.5: Upcoming TT07 version with conditional compilation added on top of 1.4

Doing TT07 with 1.5

  • Tried fixing GHA test artefact storage
  • Updated src/raybox-zero to @gf180-with-tests
  • Wired up project.v with new rbzero ports
  • Changed uo_outs to match Tiny VGA PMOD and updated tb.v to suit.
  • For now there is no texture ROM support, and i_gen_tex is hard-coded to 1. Some other features aren't yet mapped to pins e.g. map overlay, trace overlay (not working; needs an `ifdef fix).

Harden

source ./tt07-env.sh # Should load tt07 venv too.
./tt/tt_tool.py --create-user-config
time ./tt/tt_tool.py --harden # It took only 5 minutes! How is that possible?
./tt/tt_tool.py --print-warnings
./tt/tt_tool.py --print-stats
Utilisation (%) Wire length (um)
28.94 273033

GDS render

./tt/tt_tool.py --create-svg
rsvg-convert --unlimited gds_render.svg -s <(echo 'text{display:none;}') -o gds_render_png24.png --no-keep-image-data
xdg-open gds_render_png24.png

Simulate

cd test
cp ../runs/wokwi/results/final/verilog/gl/tt_um_algofoogle_raybox_zero.v gate_level_netlist.v
make clean clean_frames && make -B GATES=yes

Extras

Check:

runs/wokwi/reports/signoff/30-sta-rcx_nom/multi_corner_sta.checks.rpt
runs/wokwi/reports/signoff/39-antenna_violators.rpt
  • Finish:
    • Do final GL sim
    • PR for 1.5-dev
    • Doco
    • Do actual submission
    • Test on FPGA
  • SPI2 can turn on trace debug & map overlay
  • Option to flip the display (for clockwise rotation or mirroring)
  • Optional VGA output switching inc. to match TT04, my boards, and Matt's clock version
  • Anything else that is fun to put on-screen?
    • Why not a basic sprite?

Opening DEF files in KLayout:

# Using OpenLane's open_design.py, for example:
RUN=$OPENLANE_ROOT/designs/spm/runs/RUN_2023.11.29_01.00.58
python3 $OPENLANE_ROOT/scripts/klayout/open_design.py \
--input-lef $RUN/tmp/merged.nom.lef \
--lyt $PDK_ROOT/sky130A/libs.tech/klayout/tech/sky130A.lyt \
--lyp $PDK_ROOT/sky130A/libs.tech/klayout/tech/sky130A.lyp \
--lym $PDK_ROOT/sky130A/libs.tech/klayout/tech/sky130A.map \
$RUN/results/final/def/spm.def 
# Using OpenLane's open_design.py, for example:
RUN=/home/anton/projects/tt07-raybox-zero/runs/wokwi
python3 $OPENLANE_ROOT/scripts/klayout/open_design.py \
--input-lef $RUN/tmp/merged.nom.lef \
--lyt $PDK_ROOT/sky130A/libs.tech/klayout/tech/sky130A.lyt \
--lyp $PDK_ROOT/sky130A/libs.tech/klayout/tech/sky130A.lyp \
--lym $PDK_ROOT/sky130A/libs.tech/klayout/tech/sky130A.map \
$RUN/results/final/def/tt_um_algofoogle_raybox_zero.def

tt-vga-fun stuff

  • Harden digital block again. See how big it is now.
  • Work out where I was up to with dacboost and see if I can lay it out.
  • Extract dacboost (and full design) and simulate: I recall I was writing notes about doing this in a previous journal or my phone's 'Notes'? See how much current it uses.
  • Do check for those old notes, some might've been important, e.g. making sure line debug bits are not full brightness (or gating) during full pass-thru mode!
  • Try some pass gates to switch between buffered/not
  • Put buffers on the INPUTS to the DACs -- standard cells or just big double-inverters?

Hardening

Change config.json to initially use relative sizing, to see how much area we need. Note that max is about 160x220um.

source ./tt07-env.sh  # Sets some vars but also loads venv.
source ./openlane/controller/env.sh # WHAT I USED LAST TIME.
#NOTE: $PDK_ROOT now has this from 2024-04-19:
# /home/anton/antonOL/pdk
# ...and that contains: sky130A -> volare/sky130/versions/cd1748bb197f9b7af62a54507de6624e30363943/sky130A
time make harden

Harden takes about 2 minutes with 4 cores. Succeeds with no warnings. It wants 136x136um; that's doable. Could probably make it smaller, though. It's currently configured with "FP_CORE_UTIL": 50.

make update_files

PL_TARGET_DENSITY: Can make logic densely packed, despite large area. FP_CORE_UTIL: Sizes core relative to amount of logic.

These work OK and get an area of 117x117um:

    "FP_CORE_UTIL": 75,
    "PL_TARGET_DENSITY": 0.85,

Let's try a different aspect:

    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 150 95",
    "FP_CORE_UTIL": 80,
    "PL_TARGET_DENSITY": 0.86,

It fits, but takes 6mins now and gets fanouts (6/4).

cd mag
mkdir OLD
git mv sky130_fd_sc_hd__* OLD/
git mv sky130_ef_sc_hd__* OLD/
rm controller.gds
rm controller.mag

Stuff to document from GFMPW-1 etc:

https://openlane2.readthedocs.io/en/stable/usage/timing_closure/index.html#tips-for-achieving-timing-closure

Tidying vim backup/swap/undo files:

  • mkdir ~/.vimdata/config

  • Create ~/.vimdata/config/backunswap.vimrc:

    " https://vi.stackexchange.com/a/21709:
let &directory = expand('~/.vimdata/swap//')

set backup
let &backupdir = expand('~/.vimdata/backup//')

set undofile
let &undodir = expand('~/.vimdata/undo//')

if !isdirectory(&undodir) | call mkdir(&undodir, "p") | endif
if !isdirectory(&backupdir) | call mkdir(&backupdir, "p") | endif
if !isdirectory(&directory) | call mkdir(&directory, "p") | endif

  • Include it in ~/.vimrc:

    " https://vi.stackexchange.com/a/21709:
source ~/.vimdata/config/backunswap.vimrc

Vim junk files are now all confined to subdirs in ~/.vimdata/

tt-vga-fun didn't make it in to TT07

At least I still have raybox-zero.

Here's where I'm up to:

maybe branch has lots of mucking around with current steering.

xschem/bdac.sch is the best current steering DAC I was able to come up with that didn't use too much area and probably is OK with current on a resistor.

Miller capacitance?

Maybe I should try LVT/ZVT FETs.

TT08 analog

  • Find out how tt08-analog-template is different from tt06 -- esp. the template DEF
  • How about matt's analog instructions? I know the Makefile has been updated

TT04 testing

VGA output mapping:

uo_out raybox-zero PMOD VGA J1 VGA J2
OUT0 hsync_n 1 7
OUT1 vsync_n 2 8
OUT2 red[0] 3 3
OUT3 red[1] 4 4
GND GND 5 5
VCC3V3 VCC3V3 6 6
OUT4 green[0] 7 3
OUT5 green[1] 8 4
OUT6 blue[0] 9 9
OUT7 blue[1] 10 10
GND GND 11
VCC3V3 VCC3V3 12

Average MicroPython POV transmit time is 53ms when using 25.179MHz (core clock 101MHz)

At 31.5MHz (core clock 126MHz) this is reduced to 43us

The extra overhead of converting floating point POVs and sending them pieces appears to be about 3ms