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- Let's try a different mux layout: horizontal, in the middle. Expected advantages:
- BL corner can be reserved for JM to get close access to WB.
- TL can be for TRZF for close access to wb_clk_i, and direct
io_ins - The B edge of padframe is least important because it has no external IOs.
- Also R edge is of reduced interest because of SoC IO sharing. TRZF already avoids it, JM won't need it, DS can avoid most of it.
- Try alternate clock for 2nd raybox-zero instance?
- Repeat wb_clk_i (and reset?) out for all designs.
- Write steps for how to add a new design?
- Optionally allow io[0] to be an external reset? Can this function be gated by the mux?
- Work out ideal pin ordering for everyone's needs, inc. where some people can have direct inputs instead of via mux.
- Intentionally route some signals very far (e.g. LA[63:0]) to see if they ACTUALLY have a problem/latency.