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0168-2023-10-28.md | 0170-2023-10-31.md |
- Re-shape and reorder pins for top_ew_algofoogle
- Created
SNIPPET2_ShareIns.v
- Ran 13 harden tests on my macro (and UPW) until I settled on new parameters (see: at13 (Attempt 13) notes and GDS hardening results).
- Tested SNIPPET2_ShareIns successfully: RTL and GL.
- Re-ran existing rbz_basic test with
make coco_test_gl
for SNIPPET1; it still works. - Created
ew-snippet2-test
branch and set it up with improved tests. They work! Got red and blue channels coming out now. I hardened UPW with SNIPPET2, too, and it seemed fine.
- Write SNIPPET3_ShareMuxIO
- Core design improvements: Put in other general raybox-zero features
- Option for un/registered RGB outputs
- Maybe drop to Q11.11?
- Review EWSPEC
- Try newer OpenLane 1.x and updated CUP -- Matt's MPW9 instructions -- esp. new precheck
- Consider listing each reordered pin explicitly
- Test texture ROM in SIM -- will allow us to test texture effects such as address addend.
- Feed o_reset back to a LA.
- Design a buffer macro in case it's needed
- Consider placing pins differently for INPUT pads... even though they might switch between top-left and LHS regions.
cd ~/CUP/verilog/dv/rbz_basic
make coco_test_gl
Takes about 15mins to run.
Check resulting frame capture (even watching it load live): xdg-open rbz_basic_frame0.ppm
-- if it displays an image, the design is probably working OK...?
This verifies that -- through the GL netlist -- the firmware is able to:
- Configure SoC's GPIO as output, and pulse it.
- Configure MPRJ GPIOs (because
user_define.v
is not used in this sim...?) - Configure LAs as outputs and mux-select gpout[0] and [1] (blue colour channel). NOTE: If rendering more than 1 frame, we should also see that 'demo mode' is working via LA selection too.
- Reset lock can be asserted and released by LA.
- Mux is working and gpouts are outputting blue channel data (though rendered as green in the output image file).
i_debug_vec_overlay
should be visible, also asserted by LA.
NOTE: For me, the test didn't fail with -DUNIT_DELAY=#1
or #10
, which seems a little unlikely... but it DID fail when set to #100
-- I think due to it sending an invalid command to the SPI flash (which has its own $stop
). It even still works at #40
??
- Back up existing CUP working project -- plan to delete it, because git branches should do what we need instead. NOTE: It's about 8.5GB.
- Create
ew-snippet2-test
branch -- NOTE: The rest of the EW team shouldn't really need anything from it, because it's just for me to test SNIPPET2. The main top_ew_algofoogle GDS, Verilog, netlist should not change in this new branch. - Paste snippet into UPW.
- Update
user_defines
- NOTE: Need to make sure
io_oeb[]
is set correctly for the shared inputs, e.g. add this above the snippet in UPW (which I had to do for simulations/tests):assign {io_oeb[35:34], io_oeb[32:31]} = a1s[3:0]; //NOTE: a1s is a source of constant '1's
- CHECK: Can UPW harden this, inc. using top_ew_algofoogle.gds.GZ?? NOPE, it needs to be uncompressed.
cd ~/CUP/gds gunzip top_ew_algofoogle.gds.gz cd .. make user_project_wrapper
- Update tests, esp. more colour: Keep firmware code that sets gpout[1:0] to blue channel. Leave gpout[3:2] as default red channel. Update test to use these actual 2 colour channels.
NOTE: I had to change the test so that the texture flash ROM was sensing and asserting MPRJ_IO[22]
directly, instead of via my signal io_tex_io0
. I retained that signal to use in the tests, but trying to assert via that doesn't seem to work, i.e. it doesn't apply an assigned value back to all of its connected nets. Maybe this is just a cocotb thing, though. Not sure.
FWIW, UPW harden has basically the same slew/cap results as at13. In fact, slightly better because its input lines are shorter.
UPW GDS from step 6 above:
- Diagrams to show placement and congestion, and possible buffer/routing macro idea
- Share updated EWSPEC
- What is CUP's
verilog/rtl/uprj_netlists.v
? - I've started keeping past harden configs/runs in
at6
and above inopenlane/*/
- Aliases:
alias maketeaupw='cd ~/CUP && make top_ew_algofoogle && make user_project_wrapper' alias tea-gds='cd ~/CUP && summary.py --caravel --design top_ew_algofoogle --gds' alias upw-gds='cd ~/CUP && summary.py --caravel --design user_project_wrapper --gds'
❗ IDEA: |
---|
A very tall macro would probably help with slew/cap issues from long LA/IO wires: Places LA/user_clock2 nearer the bottom-right, and IOs nearer the top-left. |
Click to see attempts 7 to 12...
- Put zeros, ones, and main I on W.
- Put rgb on N.
- Change width so LAs on S mostly line up.
- Higher LA on E.
- Placement is nearest LAs
- LAs all line up pretty well
- user_clock2 goes past a bunch of LAs. It might affect them
- Move all outputs to the top of W, followed by inputs, followed by zeros, then ones.
- Place macro up and a little to the left
- Delete FP_IO_V/HTHICKNESS_MULT
- Expect:
- TEA: Slight change in bottom-left logic, since outputs have moved.
- UPW: Better IO performance, worse LA, worse user_clock2
- Check:
logs/signoff/34-antenna.log
reports/signoff/25-rcx_sta.slew.rpt
- Result:
- TEA:
- GDS:
- Antenna step log: 1 iters, 2 remaining
- Antenna violations: count: 8 - worst: 633/400 (good)
- Fanout: count: 30 - worst: 28 (input36/X) - avg: -5
- Slews: 0
- Caps: 0
- UPW:
- GDS:
- Antenna step log: 0
- Antenna violations: count: 0 - worst: nil
- Fanout: 0
- Slews: 2 - io_in[25]=-0.37, la_data_in[114]=-0.20
- Caps: 3 - io_in[25]=-0.09, la_data_in[114]=-0.05, io_in[26]=-0.01
- user_clock2: OK
- TEA:
- Portrait (vertical) orientation: 400x900
- Plan for LHS placement
- N: All IOs/zeros/ones
- E: Most LAs
- S: RGBs on left, low LAs on right
- W: Nothing?
- Check:
logs/signoff/34-antenna.log
reports/signoff/25-rcx_sta.slew.rpt
- Result:
- TEA:
- GDS:
- Antenna step log: 1 iters, 8 remaining
- Antenna violations: count: 10 - worst: 1019/400 (BAD!)
- Fanout: count: 57 - worst: 25 (clkbuf) - avg: -8
- Slews: 0
- Caps: 0
- UPW:
- GDS:
- Antenna step log: nil
- Antenna violations: nil
- Fanout: 0
- Slews: 10 - most are LA -0.8, user_clock2=-0.17
- Caps: 10 - mostly same as slews, user_clock2=-0.05
- TEA:
- Let OpenLane choose its own size:
"FP_SIZING": "relative", "FP_CORE_UTIL": 45, "PL_TARGET_DENSITY": 0.55,
- Keep pin placement as-is
- Keep macro placement as-is
- Check:
logs/signoff/34-antenna.log
reports/signoff/25-rcx_sta.slew.rpt
- Result:
- TEA:
- Floorplanned 500x500um (exactly, on its own??)
- GDS:
- Antenna step log: 1 iters, 3 remaining
- Antenna violations: count: 8 - worst: 807/400 (OK)
- Fanout: count: 30 - worst: 20 (clkbuf) - avg: -5 (OK)
- Slews: 0
- Caps: 0
- UPW:
- GDS:
- Antenna step log: nil
- Antenna violations: nil
- Fanout: 0
- Slews: 3, io_in [25]=-1.22 [26]=-1.0 [22]=-0.11
- Caps: 3, io_in [25]=-0.3 [26]=-0.24 [22]=-0.05
- TEA:
- Squeeze at10 a little:
- FP_CORE_UTIL: 50
- PL_TARGET_DENSITY: 0.60
- Move macro slightly left/up: (-200,+200)
- FAILED with routing congestion:
-
[STEP 12] [INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/zerotoasic/asic_tools/caravel_user_project/openlane-at11/top_ew_algofoogle/runs/23_10_30_16_42/logs/routing/12-resizer.log)... [ERROR]: during executing openroad script /openlane/scripts/openroad/resizer_routing_timing.tcl [ERROR]: Log: ../home/zerotoasic/asic_tools/caravel_user_project/openlane-at11/top_ew_algofoogle/runs/23_10_30_16_42/logs/routing/12-resizer.log [ERROR]: Last 10 lines: [INFO GRT-0101] Running extra iterations to remove overflow. [WARNING GRT-0227] Reached 20 congestion iterations with less than 15% of reduction between iterations. [INFO GRT-0197] Via related to pin nodes: 55540 [INFO GRT-0198] Via related Steiner nodes: 172 [INFO GRT-0199] Via filling finished. [INFO GRT-0111] Final number of vias: 66335 [INFO GRT-0112] Final usage 3D: 269212 [ERROR GRT-0118] Routing congestion too high. Check the congestion heatmap in the GUI.
- I tried these adjustments to help it out:
NOTE: DRT_OPT_ITERS/ROUTING_OPT_ITERS must not exceed 64, or it fails like this:
"GRT_OVERFLOW_ITERS": 60, "GRT_ANT_ITERS": 20, "GRT_MAX_DIODE_INS_ITERS": 10, "DRT_OPT_ITERS": 64, "ROUTING_OPT_ITERS": 64, "FP_CORE_UTIL": 48, "PL_TARGET_DENSITY": 0.56,
[STEP 17] [INFO]: Running Detailed Routing (log: ../home/zerotoasic/asic_tools/caravel_user_project/openlane-at11/top_ew_algofoogle/runs/23_10_30_16_49/logs/routing/17-detailed.log)... [ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl [ERROR]: Log: ../home/zerotoasic/asic_tools/caravel_user_project/openlane-at11/top_ew_algofoogle/runs/23_10_30_16_49/logs/routing/17-detailed.log [ERROR]: Last 10 lines: OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO ORD-0030] Using 6 thread(s). Error: droute.tcl, 38 Wrong number of arguments :utl::warn tool id msg argument 2
-
- Check:
logs/signoff/34-antenna.log
reports/signoff/25-rcx_sta.slew.rpt
- Result:
- TEA:
- GDS:
- Antenna step log: 0 iters
- Antenna violations: count: 8 - worst: 2423/400 (BAD) -- but is this real or repaired??
- Fanout: count: 38 - worst: 18 (clkbuf) - avg: -4 (OK)
- Slews: 0
- Caps: 0
- UPW:
- GDS:
- Antenna step log: nil
- Antenna violations: nil
- Fanout: 0
- Slews: 6 - io_in [25]=-0.93, [26]=-0.7, rest are LAs and <=-0.07
- Caps: 7 - io_in [25]=-0.23, [26]=-0.17, rest are LAs and <=-0.02
- TEA:
485x484um
- Remove routing iters and expand a bit:
"FP_SIZING": "relative", "FP_CORE_UTIL": 40, "PL_TARGET_DENSITY": 0.50,
- Move placement a little more: (-200,+200):
top_ew_algofoogle 1100 1300 N
- Check:
logs/signoff/34-antenna.log
reports/signoff/25-rcx_sta.slew.rpt
- Result:
- Floorplanned at 531x530um
- TEA:
- GDS:
- Antenna step log: 1 iters, 2 remaining
- Antenna violations: count: 9 - worst: 1495/400 (?)
- Fanout: count: 33 - worst: -8 (clkbuf, -6 on input) - avg: -4
- Slews: 0
- Caps: 0
- UPW:
- GDS:
- Antenna step log: nil
- Antenna violations: nil
- Fanout: 0
- Slews: 8 - io_in [25]=-0.55, [26]=-0.32
- Caps: 8 - io_in [25]=-0.13, [26]=-0.08
- NOTE: UPW is getting better for IO slew/caps. LA is getting marginally worse, but probably doesn't matter...?
- Go looser:
"FP_SIZING": "relative", "FP_CORE_UTIL": 35, // "PL_TARGET_DENSITY": 0.50, // Let OpenLane choose.
- Move placement a little, just up now: (0,+200):
top_ew_algofoogle 1100 1500 N
- Check:
logs/signoff/34-antenna.log
reports/signoff/25-rcx_sta.slew.rpt
- Result:
- Floorplanned: 568x566um
- TEA:
- GDS:
- Antenna step log: nil!
- Antenna violations: count: 9 - worst: 888/400 (OK)
- Fanout: count: 19 - worst: 21 (input43/X) - avg: -5
- Slews: 0
- Caps: 0
- UPW:
- GDS:
- Antenna step log: nil
- Antenna violations: count: nil
- Fanout: 0
- Slews: 9 - io_in[25]=-0.39, [26]=-0.15, user_clock2=-0.02
- Caps: 9 - io_in[25]=-0.09, [26]=-0.04, user_clock2=-0.01
This is sort of looking the best so far.
NOT DONE YET.
- ???
- Check:
logs/signoff/34-antenna.log
reports/signoff/25-rcx_sta.slew.rpt
- Result:
- TEA:
- GDS:
- Antenna step log: X iters, X remaining
- Antenna violations: count: X - worst: X/400 (?)
- Fanout: count: X - worst: X (?) - avg: X
- Slews:
- Caps:
- UPW:
- GDS:
- Antenna step log:
- Antenna violations: count: - worst:
- Fanout:
- Slews:
- Caps:
- TEA: