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- After implementing SPI and other improvements, make sure it's possible to test them with the Verilator sim.
- Write better cocotb and/or Verilog tests.
- Come up with a way to read and render VGA frame from VCD data.
- Try GL sim with cocotb-to-VCD (inc. gate-level 1ns+ delay test) to make sure: (a) tests still pass; and (b) VCD still renders VGA frame as expected.
- Make VCD-to-VGA-frame rendering support greater than pixel-clock resolution, i.e. if a 640x480 VGA frame is actually 800x525 pixels, then 3x this is 2400x1575 (sort of fits the key stuff in 2560x1440), and 4x is 3200x2100 (fits in 3840x2160). In fact, why not just render at 10x direct to PNG, then we can inspect in Photoshop and get 4ns horizontal resolution.
- Update READMEs.
For now this is being done in the solo_squash repo:
- Created
spibranch. - Started implementing SPI clocking stuff.
- 0.9: Basically the version that was used for TT03p5
- 1.0: Minor tidy-up of 0.9
- And I will make 2.0: new version with new features for TT04 (or should I call it version 4.0?)
- Metastability, clock domains, etc: Why does this page have a sync on MOSI? I would assume it only gets sampled by anything on the rising edge of SCLK, at which point it should well and truly be stable. Either it's in there because a metastable state outside of clocking could have an effect, or because it aims to avoid a case where there might be a Master error that could propagate?
- Is there a way we can prove that without sync on SPI bus we get an error? Can we try this on the FPGA?
- Maybe try reading more here: https://www.fpga4fun.com/CrossClockDomain.html