Skip to content

Latest commit

 

History

History
34 lines (21 loc) · 2.3 KB

0056-2020-08-09.md

File metadata and controls

34 lines (21 loc) · 2.3 KB
Raw

9 Aug 2020

Previous journal: Next journal:
0055-2020-08-08.md 0057-2020-08-10.md

Verilator VGA signal generation

I've started adapting my code from XC9572XL/test09/t09d (VGA tile renderer) to work with Verilator, to see if I can make it output at least one frame of data to display in Eric Eastwood's VGA Simulator. This is in t02a.

Requirements:

  • Probably simulate at least 2 full frames, since the first one might start with registers all over the place before it settles.
  • Generate an output text file that matches the requirements of the VGA Simulator. There is an example write_log.txt file as well as "Log file guidelines" explaining the format.
  • Simulate the ROM, optionally with latency.

Progress so far has the image generation working with rom_data just hard-wired to the value 0xAA, and it's working:

VGA Simulation output of t02a

I have since added very rough ROM simulation. It's pretty slow because I'm not buffering the file. It's also not very authentic because it's not: (a) paying attention to OE and CE; (b) not simulating a delay in the response time of the ROM.

It does give the expected image, though:

VGA Simulation with ROM

Later I will try and use Gisselquist's own vgasim example.

I need to include data dir stuff (ROM generation) in the Makefile.

Other notes

"Power-Up Characteristics" of the XC9500XL Data Sheet explains that:

  • It's better to bring up Vccint (main supply) before Vccio to ensure that I/Os will start in 3-state mode with weak pull-up. Otherwise, Vccio coming up before or in sync with Vccint might lead to some I/Os briefly being asserted.
  • It evidently takes about 200µS after power-up for the CPLD to be stable and ready for operation.