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- I don't think it's possible to manipulate Verilog
parameters with Verilator. Probably not an issue, though: I guess a higher-level Verilog module in the hierarchy could set parameters of submodules, as it sees fit, and then the Verilator-based testbench would just manipulate the signals it cares about to drive things. - Nice suggestion here about abstracting deep hierarchical signal access in C++.
In t01e I added basic Verilator trace support, logging to trace.vcd.
To see what was changed to add this (including adding the --trace switch to verilator in the Makefile), see the differences in this commit.
Next step is to install GTKWave and try checking out the trace.vcd file that it generates.
- Learn more about Verilog tasks.