| Previous journal: | Next journal: |
|---|---|
| 0047-2020-07-25 | 0049-2020-08-02 |
Started work on t09c; trying out VGA timing with HSYNC and VSYNC pulses leading everything else. Will it make the design easier/harder? And will it fit better or not? One important difference: X and Y screen positions now are offset and need compensation.
I want to use this approach to see if it makes it easier (and more elegant) to determine line content (especially character data) before the line starts rendering.
Other thoughts:
- "An alternative way to do this, instead of using one big counter, is to use two counters? i.e. one that stops when it hits its milestone, and causes the other to trigger, and it's the other that restarts the first."
- "Could we use a
casein this, with reg set/reset instead ofwireconditions?"
NOTE: I learned that when there are multiple assignments in Verilog, apparently the last one wins. But what about when they depend on the same register? For example:
always @(posedge clk) begin
c <= c+1
c <= c+2
end...will this always just "rule out" the first assignment and cause c just to increment by 2 (instead of 1 or 3) each time? See also: this.
This might be good reading, if looked at in detail: Exploring FPGA Graphics. It's got stuff in there like logic, always_comb, and always_ff.