- Setting Global Constraints and Options re XST, especially re Verilog-2001 Attributes and doing so with Verilog-2001 Meta Comments. How official is this?
- Synthesizing Verilog designs in 7400-series logic using Yosys.
- Check out Nand2Tetris along with this and [this] related to this example of video simulation from Verilog.
Sometimes "Fit" will apparently fail with no explanation, despite everything seeming to have worked. I've tried running the command manually and seen that it gives a SEGFAULT. Evidently a solution to this is to go to the properties for the "Fit" process, select "Reports", and change "HDL Equations Style" to ABEL.
Paddle doesn't go all the way to the top because the comparison between v and paddle only happens while v is still one line behind. Changing it to be exact would probably add extra adder/subtractor logic that we can't afford.