Generated test banches cannot be used with Xcelium or Iverilog

[zputrle]

The test benches generated by Sby when an assertion fails cannot be used with the Xcelium or Iverilog simulators.

The problem that I encountered is that, when you try to use the generated test benches with Xcelium and Iverilog, they report that hierarchical name component lookup fails:

xmelab: *E,CUVHNF (../rtl/trace7_tb.v,460|59): Hierarchical name component lookup failed at 'UUT.i_byd_axi_mlic.i_dec.\dec_for_loop[0] '.
    UUT.i_axi_mlic.i_dec.\dec_for_loop[0] .i_dec_rd.len_cnt = 8'b00000000; 

After discussing this with @nakengelhardt on Yosy's Slack channel, he pointed out that "Yosys doesn't retain enough information about the original structure of the RTL to be able to correctly address the signals that need to be set to the right initial state for the simulation to reproduce the same result."

I'm posting this as an issue so that others looking into using the generated test benches will know that currently they cannot be used.

(Being able to use the test benches would be great because it would allow you test that an issue that you encountered was fixed for that specific test benches before continuing with the verification.)