Configuring IOs with input as LVDS and outputs as single-ended

[tomverbeure]

This sounds dumb, but hear me out...

It is possible to create high-speed AD converters with just LVDS IOs.

• the positive input of the LVDS comparator contains the analog signal
• the negative input contains a slope using an R/C network where both an R and C are stray resistance and capacitance of the IO pad itself
• the output driver of the negative LVDS IO contains a clock that charges and discharges the R/C network
• the output driver of the positive LVDS IO is kept in tri-state

See this paper, which creates a 600Msps (!!!) 7-bit ADC this way.

To get these high speeds, you need to configure the IO cell as LVDS input and single-ended output. In the paper above, they use special Vivado hacks to get such a Franken-configuration through Vivado.

I'm wondering what it would take to make this happen on an ECP5?

Tom