Skip to content
This repository has been archived by the owner on Nov 4, 2021. It is now read-only.

Add verilator? #7

Open
edbordin opened this issue May 2, 2020 · 2 comments
Open

Add verilator? #7

edbordin opened this issue May 2, 2020 · 2 comments

Comments

@edbordin
Copy link
Collaborator

edbordin commented May 2, 2020

No description provided.

@abhishek-kakkar
Copy link

I'm curious if there's a reason it's not there in these tools yet? I'd be interested in having these integrated into the fpga-toolchain package.

@edbordin
Copy link
Collaborator Author

edbordin commented Sep 7, 2020

It hasn't been a priority because I figured if you are willing to compile your simulations then you are probably more comfortable building verilator from source. I haven't looked into the details but can imagine this tool would also not be easy to package up in a portable way - if it builds dynamic libs for your simulation to link against that would probably complicate matters. Also if it "learns" details of your system toolchain at configure time then that will not be portable to another system.

You're welcome to contribute something if you can find a way to make it work though.

Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants