From 8d29423575ad94e2379bb6ec19d07be10b597137 Mon Sep 17 00:00:00 2001 From: Eddie Richter Date: Wed, 7 Feb 2024 09:17:44 -0700 Subject: [PATCH] Initial implementation of lit testing on VCK5000 --- CMakeLists.txt | 1 + test/CMakeLists.txt | 2 +- test/lit.cfg.py | 24 +++++++++++++------ test/lit.site.cfg.py.in | 4 ++++ .../aie/01_memory_read_write/aie.mlir | 2 +- .../aie/02_lock_acquire_release/aie.mlir | 2 +- .../aie/03_sync_with_locks/aie.mlir | 2 +- test/unit_tests/aie/04_shared_memory/aie.mlir | 2 +- test/unit_tests/aie/05_tiledma/aie.mlir | 2 +- .../aie/08_stream_broadcast/aie.mlir | 2 +- .../aie/09_simple_shim_dma/aie.mlir | 2 +- test/unit_tests/aie/10_scalar_fp/aie.mlir | 2 +- test/unit_tests/aie/11_vector_fp/aie.mlir | 2 +- test/unit_tests/aie/12_julia/aie.mlir | 2 +- test/unit_tests/aie/13_julia_fp/aie.mlir | 2 +- test/unit_tests/aie/14_stream_packet/aie.mlir | 2 +- test/unit_tests/aie/15_prime_sieve/aie.mlir | 2 +- test/unit_tests/aie/16_libm_expf/aie.mlir | 2 +- .../aie/17_shim_dma_with_core/aie.mlir | 2 +- .../aie/18_simple_shim_dma_routed/aie.mlir | 2 +- .../aie/19_shim_dma_with_core_routed/aie.mlir | 2 +- .../aie/20_shim_dma_broadcast/aie.mlir | 2 +- .../aie/21_shim_dma_packet/aie.mlir | 2 +- test/unit_tests/aie/21_target_triple/aie.mlir | 2 +- test/unit_tests/aie/22_init_locks/aie.mlir | 2 +- .../aie/23_broadcast_packet/aie.mlir | 5 ++-- test/unit_tests/aie/23_packet_biShim/aie.mlir | 2 +- test/unit_tests/aie/24_host_loop/aie.mlir | 2 +- .../unit_tests/aie/25_host_multirate/aie.mlir | 2 +- .../aie/27_single_L1_single_lock/aie.mlir | 2 +- .../multi_depth/aie.mlir | 2 +- .../single_depth/aie.mlir | 2 +- .../aie/29_aie2_nd_dma_even_odd/aie.mlir | 2 +- .../30_aie2_nd_dma_transpose_repeat/aie.mlir | 2 +- test/unit_tests/aie/31_stream_core/aie.mlir | 2 +- 35 files changed, 55 insertions(+), 41 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 0eb7af0a99..670def06a7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -98,6 +98,7 @@ find_package(Vitis 2023.2 COMPONENTS AIE AIE2) configure_file(./utils/vitisVariables.config.in ${CMAKE_BINARY_DIR}/utils/vitisVariables.config @ONLY) find_package(XRT) +find_package(hsa-runtime64) # Set up default Vitis Sysroot as sysroot when testing on aarch64 list(FIND AIE_RUNTIME_TARGETS "aarch64" indexAarch64) diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 82f9e78682..590fde6cf6 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -66,7 +66,7 @@ find_package(Python3 COMPONENTS Interpreter) find_package(XRT) cmake_dependent_option(ENABLE_CHESS_TESTS "Enable backend tests using xchesscc" ON "Vitis_FOUND" OFF) -cmake_dependent_option(ENABLE_BOARD_TESTS "Enable board tests" ON "CMAKE_HOST_SYSTEM_PROCESSOR MATCHES aarch64" OFF) +cmake_dependent_option(ENABLE_BOARD_TESTS "Enable board tests" ON "hsa-runtime64_FOUND" OFF) cmake_dependent_option(ENABLE_PYTHON_TESTS "Enable python tests" ON "AIE_ENABLE_BINDINGS_PYTHON" OFF) # Look for LibXAIE diff --git a/test/lit.cfg.py b/test/lit.cfg.py index 261959f21a..0c3b565320 100644 --- a/test/lit.cfg.py +++ b/test/lit.cfg.py @@ -54,15 +54,25 @@ # for xchesscc_wrapper llvm_config.with_environment("AIETOOLS", config.vitis_aietools_dir) -if config.enable_board_tests: - config.substitutions.append( - ("%run_on_board", "echo %T >> /home/xilinx/testlog | sync | sudo") - ) -else: - config.substitutions.append(("%run_on_board", "echo")) - run_on_ipu = "echo" xrt_flags = "" + +if config.hsa_found: + # Getting the path to the ROCm directory. hsa-runtime64 points to the cmake + # directory so need to go up three directories + rocm_root = os.path.join(config.hsa_dir, "..", "..", "..") + print("Found ROCm:", rocm_root) + config.substitutions.append(('%link_against_hsa%', "--link_against_hsa")) + + if config.enable_board_tests: + config.substitutions.append(('%run_on_board', "sudo")) + else: + print("Skipping execution of unit tests (ENABLE_BOARD_TESTS=OFF)") + config.substitutions.append(('%run_on_board', "echo")) +else: + print("ROCm not found") + config.substitutions.append(('%link_against_hsa%', "")) + if config.xrt_lib_dir: print("xrt found at", os.path.dirname(config.xrt_lib_dir)) xrt_flags = "-I{} -L{} -luuid -lxrt_coreutil".format( diff --git a/test/lit.site.cfg.py.in b/test/lit.site.cfg.py.in index f1b5e82cdf..ea3f8783d6 100644 --- a/test/lit.site.cfg.py.in +++ b/test/lit.site.cfg.py.in @@ -48,6 +48,10 @@ config.aie_obj_root = "@AIE_BINARY_DIR@" # test_exec_root: The root path where tests should be run. config.test_exec_root = "@CMAKE_CURRENT_BINARY_DIR@" +# Pointing to the ROCr directories +config.hsa_dir = "@hsa-runtime64_DIR@" +config.hsa_found = "@hsa-runtime64_FOUND@" + # available features config.enable_chess_tests = lit.util.pythonize_bool("@ENABLE_CHESS_TESTS@") config.enable_board_tests = lit.util.pythonize_bool("@ENABLE_BOARD_TESTS@") diff --git a/test/unit_tests/aie/01_memory_read_write/aie.mlir b/test/unit_tests/aie/01_memory_read_write/aie.mlir index e3e7ec26fb..8da335fa16 100644 --- a/test/unit_tests/aie/01_memory_read_write/aie.mlir +++ b/test/unit_tests/aie/01_memory_read_write/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf module @test01_memory_read_write { diff --git a/test/unit_tests/aie/02_lock_acquire_release/aie.mlir b/test/unit_tests/aie/02_lock_acquire_release/aie.mlir index 58be93d4b9..df03b69917 100644 --- a/test/unit_tests/aie/02_lock_acquire_release/aie.mlir +++ b/test/unit_tests/aie/02_lock_acquire_release/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf module @test02_lock_acquire_release { diff --git a/test/unit_tests/aie/03_sync_with_locks/aie.mlir b/test/unit_tests/aie/03_sync_with_locks/aie.mlir index 6297899da3..26a09e3748 100644 --- a/test/unit_tests/aie/03_sync_with_locks/aie.mlir +++ b/test/unit_tests/aie/03_sync_with_locks/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf module @test03_sync_with_locks { diff --git a/test/unit_tests/aie/04_shared_memory/aie.mlir b/test/unit_tests/aie/04_shared_memory/aie.mlir index 6813ab78ec..3dcda1c185 100644 --- a/test/unit_tests/aie/04_shared_memory/aie.mlir +++ b/test/unit_tests/aie/04_shared_memory/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf module @test04_shared_memory { diff --git a/test/unit_tests/aie/05_tiledma/aie.mlir b/test/unit_tests/aie/05_tiledma/aie.mlir index 81af3e2818..1e2f892cba 100644 --- a/test/unit_tests/aie/05_tiledma/aie.mlir +++ b/test/unit_tests/aie/05_tiledma/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf module @test05_tiledma { diff --git a/test/unit_tests/aie/08_stream_broadcast/aie.mlir b/test/unit_tests/aie/08_stream_broadcast/aie.mlir index 13d8c5b8f6..4bb4658a11 100644 --- a/test/unit_tests/aie/08_stream_broadcast/aie.mlir +++ b/test/unit_tests/aie/08_stream_broadcast/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf module @test08_stream_broadcast { diff --git a/test/unit_tests/aie/09_simple_shim_dma/aie.mlir b/test/unit_tests/aie/09_simple_shim_dma/aie.mlir index dd334c7baf..375db1cc4c 100644 --- a/test/unit_tests/aie/09_simple_shim_dma/aie.mlir +++ b/test/unit_tests/aie/09_simple_shim_dma/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf module @test09_simple_shim_dma { diff --git a/test/unit_tests/aie/10_scalar_fp/aie.mlir b/test/unit_tests/aie/10_scalar_fp/aie.mlir index 780d4e986e..726ebaf8c2 100644 --- a/test/unit_tests/aie/10_scalar_fp/aie.mlir +++ b/test/unit_tests/aie/10_scalar_fp/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test { diff --git a/test/unit_tests/aie/11_vector_fp/aie.mlir b/test/unit_tests/aie/11_vector_fp/aie.mlir index 407ca8c3c4..aa1f119562 100644 --- a/test/unit_tests/aie/11_vector_fp/aie.mlir +++ b/test/unit_tests/aie/11_vector_fp/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test { diff --git a/test/unit_tests/aie/12_julia/aie.mlir b/test/unit_tests/aie/12_julia/aie.mlir index 9ed36d4fd6..16acfe471d 100644 --- a/test/unit_tests/aie/12_julia/aie.mlir +++ b/test/unit_tests/aie/12_julia/aie.mlir @@ -10,7 +10,7 @@ // REQUIRES: peano && jackl // RUN: %PEANO_INSTALL_DIR/bin/clang++ --target=aie -c -I/usr/include/aie %S/kernel.cpp -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/aie/13_julia_fp/aie.mlir b/test/unit_tests/aie/13_julia_fp/aie.mlir index ccb5d3c28a..a90af5318d 100644 --- a/test/unit_tests/aie/13_julia_fp/aie.mlir +++ b/test/unit_tests/aie/13_julia_fp/aie.mlir @@ -10,7 +10,7 @@ // REQUIRES: peano && jackl // RUN: %PEANO_INSTALL_DIR/bin/clang++ -O2 --target=aie -c -I/usr/include/aie %S/kernel.cpp -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test { diff --git a/test/unit_tests/aie/14_stream_packet/aie.mlir b/test/unit_tests/aie/14_stream_packet/aie.mlir index b460d14417..4bf557474b 100644 --- a/test/unit_tests/aie/14_stream_packet/aie.mlir +++ b/test/unit_tests/aie/14_stream_packet/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test14_stream_packet { diff --git a/test/unit_tests/aie/15_prime_sieve/aie.mlir b/test/unit_tests/aie/15_prime_sieve/aie.mlir index 65495dd25e..ca61de078e 100644 --- a/test/unit_tests/aie/15_prime_sieve/aie.mlir +++ b/test/unit_tests/aie/15_prime_sieve/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test15_prime_sieve { diff --git a/test/unit_tests/aie/16_libm_expf/aie.mlir b/test/unit_tests/aie/16_libm_expf/aie.mlir index 6429428e0b..7f8c22b275 100644 --- a/test/unit_tests/aie/16_libm_expf/aie.mlir +++ b/test/unit_tests/aie/16_libm_expf/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test { diff --git a/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir b/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir index d3cdae2aa6..7863b701e6 100644 --- a/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir +++ b/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // clang -O2 --target=aie -c %S/kernel.cc -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test17_shim_dma_with_core{ diff --git a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir index 4275e7bb86..06f8e000a8 100644 --- a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir +++ b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test18_simple_shim_dma_routed { diff --git a/test/unit_tests/aie/19_shim_dma_with_core_routed/aie.mlir b/test/unit_tests/aie/19_shim_dma_with_core_routed/aie.mlir index 2ea68ade4f..4a0400a1c5 100644 --- a/test/unit_tests/aie/19_shim_dma_with_core_routed/aie.mlir +++ b/test/unit_tests/aie/19_shim_dma_with_core_routed/aie.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // clang -O2 --target=aie -c %S/kernel.cc -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test19_shim_dma_with_core_routed{ diff --git a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir index 60c3ee752a..918faa65cc 100644 --- a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir +++ b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test20_shim_dma_broadcast { diff --git a/test/unit_tests/aie/21_shim_dma_packet/aie.mlir b/test/unit_tests/aie/21_shim_dma_packet/aie.mlir index eeb7be90eb..def605aed3 100644 --- a/test/unit_tests/aie/21_shim_dma_packet/aie.mlir +++ b/test/unit_tests/aie/21_shim_dma_packet/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // A single kernel 32x32x32 GEMM using GMIO. diff --git a/test/unit_tests/aie/21_target_triple/aie.mlir b/test/unit_tests/aie/21_target_triple/aie.mlir index 0a036944ea..d788cd07f6 100644 --- a/test/unit_tests/aie/21_target_triple/aie.mlir +++ b/test/unit_tests/aie/21_target_triple/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // When this IR is lowered to LLVM, the affine.load operation resulting "%val0" diff --git a/test/unit_tests/aie/22_init_locks/aie.mlir b/test/unit_tests/aie/22_init_locks/aie.mlir index 855afba919..3a75e68976 100644 --- a/test/unit_tests/aie/22_init_locks/aie.mlir +++ b/test/unit_tests/aie/22_init_locks/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @test22_init_locks { diff --git a/test/unit_tests/aie/23_broadcast_packet/aie.mlir b/test/unit_tests/aie/23_broadcast_packet/aie.mlir index ef92511b22..252f388825 100644 --- a/test/unit_tests/aie/23_broadcast_packet/aie.mlir +++ b/test/unit_tests/aie/23_broadcast_packet/aie.mlir @@ -8,8 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf -// RUN: %run_on_board ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf module @test23_broadcast_packet { @@ -111,4 +110,4 @@ module @test23_broadcast_packet { aie.end } -} \ No newline at end of file +} diff --git a/test/unit_tests/aie/23_packet_biShim/aie.mlir b/test/unit_tests/aie/23_packet_biShim/aie.mlir index da6ea5696f..0a50916a81 100644 --- a/test/unit_tests/aie/23_packet_biShim/aie.mlir +++ b/test/unit_tests/aie/23_packet_biShim/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf module @aie_module { %t70 = aie.tile(7, 0) diff --git a/test/unit_tests/aie/24_host_loop/aie.mlir b/test/unit_tests/aie/24_host_loop/aie.mlir index a11edb31a9..2f448e74e9 100755 --- a/test/unit_tests/aie/24_host_loop/aie.mlir +++ b/test/unit_tests/aie/24_host_loop/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf aie.device(xcvc1902) { diff --git a/test/unit_tests/aie/25_host_multirate/aie.mlir b/test/unit_tests/aie/25_host_multirate/aie.mlir index aba031c725..49757e707c 100755 --- a/test/unit_tests/aie/25_host_multirate/aie.mlir +++ b/test/unit_tests/aie/25_host_multirate/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf aie.device(xcvc1902) { diff --git a/test/unit_tests/aie/27_single_L1_single_lock/aie.mlir b/test/unit_tests/aie/27_single_L1_single_lock/aie.mlir index 0ce32fa7d6..341d5d6da0 100644 --- a/test/unit_tests/aie/27_single_L1_single_lock/aie.mlir +++ b/test/unit_tests/aie/27_single_L1_single_lock/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test.elf -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf module @test27_simple_shim_dma_single_lock { diff --git a/test/unit_tests/aie/28_multidepth_objectFifos/multi_depth/aie.mlir b/test/unit_tests/aie/28_multidepth_objectFifos/multi_depth/aie.mlir index 0166e91458..096e6f90ea 100755 --- a/test/unit_tests/aie/28_multidepth_objectFifos/multi_depth/aie.mlir +++ b/test/unit_tests/aie/28_multidepth_objectFifos/multi_depth/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @multi_depth { diff --git a/test/unit_tests/aie/28_multidepth_objectFifos/single_depth/aie.mlir b/test/unit_tests/aie/28_multidepth_objectFifos/single_depth/aie.mlir index d125506c9c..f3ca94ed79 100755 --- a/test/unit_tests/aie/28_multidepth_objectFifos/single_depth/aie.mlir +++ b/test/unit_tests/aie/28_multidepth_objectFifos/single_depth/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @single_depth { diff --git a/test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir b/test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir index 26fbf9db2a..c290eb62df 100644 --- a/test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir +++ b/test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir @@ -24,7 +24,7 @@ // checked from the host code to be correct. // REQUIRES: valid_xchess_license -// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf // RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s diff --git a/test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir b/test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir index 7c037b235e..6a6f57279b 100644 --- a/test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir +++ b/test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir @@ -12,7 +12,7 @@ // buffer descriptors. // REQUIRES: valid_xchess_license -// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test -L%host_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test -L%host_runtime_lib%/test_lib/lib -ltest_lib // RUN: %run_on_board ./test.elf // RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s diff --git a/test/unit_tests/aie/31_stream_core/aie.mlir b/test/unit_tests/aie/31_stream_core/aie.mlir index 7ed8a7676b..8eb0b9861f 100644 --- a/test/unit_tests/aie/31_stream_core/aie.mlir +++ b/test/unit_tests/aie/31_stream_core/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // CHECK: test start.