See Vitis™ Development Environment on xilinx.com |
The AIE-ML Development Feature Tutorials highlight specific features and flows that help develop AIE-ML applications.
| Tutorial | Description |
| A to Z Bare-metal Flow | This tutorial walks through the steps to create a custom Baremetal platform, and also integrate Baremetal host application along with an AI Engines graph and PL kernels. |
| Using GMIO with AIE-ML | This tutorial introduces the usage of global memory I/O (GMIO) for sharing data between the AI Engine-ML (AIE-ML) and external DDR. |
| Runtime Parameter Reconfiguration | Learn how to dynamically update AI Engine-ML (AIE-ML) runtime parameters. |
| Packet Switching | This tutorial illustrates how to use data packet switching with AI Engine-ML (AIE-ML) designs to optimize efficiency. |
| AI Engine Versal Integration for Hardware Emulation and Hardware | This tutorial demonstrates creating a system design running on the AI Engine-ML (AIE-ML), PS, and PL and validating the design running on these heterogeneous domains by running Hardware Emulation. |
| AI Engine-ML Performance Analysis Tutorial | This tutorial introduces you to performance analysis and optimization methods, and shows you how synchronization works in graph execution. It also demonstrates the analysis of a hang issue using an example. |
| AIE Compiler Features | This tutorial shares a variety of features that are useful for AI Engine / AI Engine-ML (AIE-ML) programming to create more visible and efficient code compared to early versions of the compiler. |
| Performance Validation in Analysis View of the Vitis Unified IDE | This tutorial demonstrates throughput and latency computation after AI Engine Simulation and their analysis in the Analysis View of the Vitis Unified IDE. |
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