RapidWright 2018.3.2-beta Release

Notes:

• API Additions:
  • com.xilinx.rapidwright.design.Cell "public boolean updateName(String newCellName)"
  • com.xilinx.rapidwright.design.Cell "public boolean isPlaced()"
  • com.xilinx.rapidwright.design.Design "public Cell addCell(Cell c)"
  • com.xilinx.rapidwright.design.Design "public void addSiteInst(SiteInst inst)";
  • com.xilinx.rapidwright.design.Design "public Net addNet(Net net)";
  • com.xilinx.rapidwright.design.Net "public boolean updateName(String newName)"
• Fixes an issue related to creating a module instance if the cell instance isn't already present in the netlist
• Adds return value for
• com.xilinx.rapidwright.design.Design.removeNet(*), returns the net that was removed or null if unsuccessful
• Changed behavior of com.xilinx.rapidwright.design.Design.removeSiteInst(SiteInst) -- now only unroutes portions of nets connected to SiteInst rather than the entire net.
• Fixed potential NPE case in com.xilinx.rapidwright.design.Design.removeCell(Cell).
• Changed com.xilinx.rapidwright.design.Net.addPins(ArrayList) to accept List.
• Fixed an issue when unrouting partial nets in com.xilinx.rapidwright.design.Net.unroute().

RapidWright 2018.3.1-beta Release

Notes:

• API Additions:
  • com.xilinx.rapidwright.design.Design "public SiteInst createSiteInst(Site site)"
  • com.xilinx.rapidwright.design.Design "public SiteInst createSiteInst(String siteName)"
  • com.xilinx.rapidwright.design.Design "public SiteInst createSiteInst(String name, SiteTypeEnum type, Site placement)"
  • com.xilinx.rapidwright.design.SiteInst "public Cell getCell(BEL bel)"
  • com.xilinx.rapidwright.design.Cell "public Map<EDIFName, EDIFPropertyValue> getProperties()"
  • com.xilinx.rapidwright.design.Cell "public void setProperties(Map<EDIFName, EDIFPropertyValue> properties)"
• API Removals (deprecated):
  • com.xilinx.rapidwright.design.SiteInst "public void addSitePIP(String belName, String inputPin, String outputPin)"
  • com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(String belName, String inputPin, String outputPin)"
  • com.xilinx.rapidwright.device.Site "public BELPin[] getConnectedBELPins(int siteWireIndex)"
  • com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(BELPin input, BELPin output)"
• Changed the toString() method on SiteInst class to help address issue #23
• Improved the error message when trying to create and place a transformed prim (issue #22)
• Removed the Hessian library, no longer used
• Fixes issue with SLRCrossingGenerator DCPs not always working with Vivado's clock router
• Adds preliminary support for SAT routing
• Pblock support for PerformanceExplorer

RapidWright 2018.3.0-beta Release

Notes:

• Compatibility with Vivado 2018.3.0 and its devices
• Adds support for RapidWright Jupyter Notebook kernels
• Reduces device file size to improve download times and load times
• Removes Hessian implementation dependency for PartNameTools resource file and
  ModuleCache files. This was done to resolve Java >=9 issues with
  obsolete reflection usage.
• Removed com.xilinx.rapidwright.edif.InstPair class and replaced functionality
  with com.xilinx.rapidwright.edif.EDIFHierCellInst.
• API Additions:
  • com.xilinx.rapidwright.design.SiteInst "public void addSitePIP(String belName, String inputPin)"
  • com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(String belName, String inputPin)"
  • com.xilinx.rapidwright.design.SiteInst "public Set getSiteWiresFromNet(Net net)"
  • com.xilinx.rapidwright.device.Device "public Node getNode(String name)"
  • com.xilinx.rapidwright.device.Device "public Wire getWire(String name)"
  • com.xilinx.rapidwright.device.Device "public PIP getPIP(String name)"
  • com.xilinx.rapidwright.device.Device "public SitePin getSitePin(String name)"
  • com.xilinx.rapidwright.device.Site "public Integer getSiteWireIndex(String siteWireName)"
  • com.xilinx.rapidwright.device.Site "public BELPin[] getBELPins(int siteWireIndex)"
  • com.xilinx.rapidwright.device.Site "public BELPin[] getBELPins(String siteWireName)"
  • com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(BELPin input)"
  • com.xilinx.rapidwright.device.Wire "public Node getNode()"
• Deprecated APIs:
  • com.xilinx.rapidwright.design.SiteInst "public void addSitePIP(String belName, String inputPin, String outputPin)"
  • com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(String belName, String inputPin, String outputPin)"
  • com.xilinx.rapidwright.device.Site "public BELPin[] getConnectedBELPins(int siteWireIndex)"
  • com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(BELPin input, BELPin output)"

Known Issues:

• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.
• Clock router in Router class is disabled (under development).
• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.

RapidWright v2018.2.5-beta Release

Notes:

• Fixes an issue in
  com.xilinx.rapidwright.device.Tile.getWireConnections(int wire) that was
  causing an issue when routing clocking routes. This was manifesting
  in the SLRCrosserGenerator demo.
  Known Issues:
• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.
• Clock router in Router class is disabled (under development).
• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.

NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.

RapidWright v2018.2.4-beta Release

Notes:

• API Additions:
  • com.xilinx.rapidwright.design.SiteInst "public boolean unrouteIntraSiteNet(BELPin src, BELPin snk)"
  • com.xilinx.rapidwright.design.SitePinInst "public void setSiteInst(SiteInst instance, boolean keepRouting"
  • com.xilinx.rapidwright.device.Wire "public ArrayList getBackwardPIPs()"
  • com.xilinx.rapidwright.device.Wire "public ArrayList getForwardPIPs()"
• API Removals:
  • com.xilinx.rapidwright.device.Wire "public ? getBackwardPIPs()"
  • com.xilinx.rapidwright.device.Wire "public ? getForwardPIPs()"
• Resolves issues: #14, #15
  Known Issues:
• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.
• Clock router in Router class is disabled (under development).
• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.

NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.

RapidWright 2018.2.3-beta Release

Notes:

• API Additions:

  • com.xilinx.rapidwright.design.Design "public Cell createAndPlaceIOB(String name, PinType dir, String pkgPin, String ioStandard, Net portNet, EDIFNet logNet)"
  • com.xilinx.rapidwright.design.Design "public Cell placeIOB(EDIFCellInst bufInst, String pkgPin, String ioStandard)"

• API Removals:

  • com.xilinx.rapidwright.design.Design "public EDIFCellInst createIBUF(String portName, Site site, Net portNet, EDIFNet logNet, String ioStandard)"
  • com.xilinx.rapidwright.design.Design "public Cell createOBUF(String portName, Site site, Net portNet, EDIFNet logNet, String ioStandard)"

• Enables fix to run HandPlacer in both modes of BlockStitcher (rapid_compile_ipi)

• Fixes routing issue when loading two different devices

• Fixes some issues related to creating top-level ports

• Removes artificial anchor for Modules that do not have internal logic (anchor is allowed to be null)

• Resolves issue: #8
  Known Issues:

• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.

• Clock router in Router class is disabled (under development).

• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.

NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.

RapidWright 2018.2.2-beta Release

Notes:

• API Additions:

  • com.xilinx.rapidwright.device.PIP "public boolean isRouteThru()"
  • com.xilinx.rapidwright.device.Site "public BEL[] getBELs()"
  • com.xilinx.rapidwright.design.SiteInst "public BEL[] getBELs()"
  • com.xilinx.rapidwright.design.SiteInst "public String getPrimarySitePinName(String alternateSitePinName)"
  • com.xilinx.rapidwright.design.SiteInst "public String getAlternateSitePinName(String primarySitePinName)"
  • com.xilinx.rapidwright.design.Module "public PBlock getPBlock()"
  • com.xilinx.rapidwright.design.Module "public void setPBlock(PBlock pblock)"
  • com.xilinx.rapidwright.design.Module "public Map<String, String> getMetaDataMap()"
  • com.xilinx.rapidwright.design.Module "public void setMetaDataMap(HashMap<String, String> metaDataMap)"

• API Removals:

  • com.xilinx.rapidwright.design.Module "public String[] getExternalInputNames()"
  • com.xilinx.rapidwright.design.Module "public void setExternalInputNames(String[] externalInputNames)"
  • com.xilinx.rapidwright.design.Module "public String[] getExternalOutputNames()"
  • com.xilinx.rapidwright.design.Module "public void setExternalOutputNames(String[] externalOutputNames)"
  • com.xilinx.rapidwright.design.Module "public HashMap<String, ArrayList> getMetaDataMap()"
  • com.xilinx.rapidwright.design.Module "public void setMetaDataMap(HashMap<String, ArrayList> metaDataMap)"

• API Renames:

  • com.xilinx.rapidwright.design.Module "public String getPBlock()" --> "public String getPBlockString()"

• Changes Implementation Guide File extension from '.impl.guide' to '.igf'

• Fixed an issue in the HandPlacer where it would fail to start because of some missing saveDesign() methods.

• Modules now store PBlocks when using the rapid_compile_ipi flow

• If no impl guide file is supplied, rapid_compile_ipi will create an example file

• enables non-LUT routethrus in Router

• Resolves issue: #7

Known Issues:

• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.
• Clock router in Router class is disabled (under development).
• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.

NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.

RapidWright 2018.2.1-beta Release

Notes:

• API Additions:
  • com.xilinx.rapidwright.device.Site "public SiteTypeEnum[] getAlternateSiteTypeEnums()"
  • com.xilinx.rapidwright.design.SiteInst "public SiteTypeEnum getPrimarySiteTypeEnum()"
  • com.xilinx.rapidwright.design.SiteInst "public SiteTypeEnum[] getAlternateSiteTypeEnums()"
• API Removals:
  • com.xilinx.rapidwright.device.Site "public SiteType getPrimarySiteType()"
• Resolves issues: #5, #6
• Preliminary tutorial for running IP Integrator flow (rapid_compile_ipi)
  Known Issues:
• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.
• Clock router in Router class is disabled (under development).
• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.
• Issue #4 - JDK9 Compliance for some 3rd party libraries prints out warnings

NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.

RapidWright 2018.2.0-beta Release

Notes:

• Initial release with new RapidWright API Library
  Known Issues:
• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.
• Clock router in Router class is disabled (under development).
• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.
• Issue #4 - JDK9 Compliance for some 3rd party libraries prints out warnings