Source and Sink Pins for Internally Routed (Intra-Site) Nets

[sma-asghar]

Hi Chris,

I am trying to find the source and sink pins of all the nets in a design. However, for the internally routed (intra-site) nets the methods, n.getSinkPins() and n.getSource() return [] and 'None' respectively. Vivado does show the source and sink connections of internal nets in the net property browser. Could you please direct me to the appropriate methods in the Javadoc for this purpose.

Regards,
Ali

[clavin-xlnx]

Hi Ali,

It sounds like you want all of the logical pin connections on a physical net, regardless of if they connect to a site pin or not. If that is correct, the best way to iterate through a net's connections is to examine the logical net's pins. We use the EDIF prefix to denote any of the logical netlist classes in RapidWright since EDIF is the primary netlist file format we support. There are both regular and hierarchical variants that are prefixed with EDIFHier in order for the object to provide absolute reference to a specific entity in the netlist and hierarchy.

To get all the logical pins of a net, you'll want to get the EDIFHierNet, you can get that from the physical Net class by calling Net.getLogicalHierNet(), then you can call EDIFHierNet.getLeafHierPortInsts() to get all the pins (port instances).

Take a look at the EDIF package documentation if you have any questions, I find this picture particularly instructive:

https://www.rapidwright.io/docs/_images/edif_netlist.png

Hope that helps, let me know if you have more questions.

Chris

[sma-asghar]

Thanks for your reply Chris. Your answer has solved the the issue.
I am trying to trace the paths of nets passing through different sites till they reach a flip flop. To accomplish this, I need to find if a net entering a site is connected to a FF or it leaves the site to get connected to another LUT in a different site.

I still have confusion regarding the difference between EDIF Cell, EDIF CellInst and Cell. Could you please provide a brief description of these terms.

Regards,
Ali

[sma-asghar]

Sorry, forgot to ask this. If a net is connected to a LUT input, is it possible to get the following net from the LUT output. Also, is it possible to distinguish which LUT output the net is connected to (in case both O6 and O5 are used)?

[clavin-xlnx]

Thanks for your reply Chris. Your answer has solved the the issue. I am trying to trace the paths of nets passing through different sites till they reach a flip flop. To accomplish this, I need to find if a net entering a site is connected to a FF or it leaves the site to get connected to another LUT in a different site.

I think there is some similar code that does this kind of graph expansion in the TimingGraph, but it might be a bit difficult to follow.

I still have confusion regarding the difference between EDIF Cell, EDIF CellInst and Cell. Could you please provide a brief description of these terms.

EDIFCell = Logical definition of a logical cell. It describes the prototype of a logical cell (ports, nets, instances inside if its not a primitive). All EDIFCell objects should belong to an EDIFLibrary.
EDIFCellInst = A logical instance of an EDIFCell. This is actually an instance of a library cell, so it instantiates an EDIFCell. This instance also is generally instantiated as part of a definition of a larger cell.
Cell = This is the instance of a physical cell in a design. It will map an EDIFCellInst to a specific BEL on the fabric.

Sorry, forgot to ask this. If a net is connected to a LUT input, is it possible to get the following net from the LUT output. Also, is it possible to distinguish which LUT output the net is connected to (in case both O6 and O5 are used)?

To distinguish between O5 and O6 outputs, note that you'll have to get a reference to the respective Cell that lives on the LUT5 or LUT6 BEL respectively. Each Cell object has a set of pin mappings (logical->physical and vice versa) that will help you identify connections, some useful APIs on Cell:

• getPinMappingsP2L()
• getPinMappingsL2P()
• getLogicalPinMapping(String physicalPin)
• getLogicalPinMapping(String physicalPin)

These mappings are the same that exist as shown in the Vivado GUI:

The logical would be the Name column and the physical would be the BEL Pin column.