Logic Synthesis

[cyberpunksubru]

I'm trying to implement FSMs from KISS files in RapidWright. Since I'm new to the tool, I was counting on the RapidWright tutorials to give me an idea. But most tutorials seem to be implementation based. Is there any tutorial that is more focused to fit my requirements?

[clavin-xlnx]

This is a very interesting challenge. The short answer is that RapidWright does not have any logic synthesis capabilities built in. However, this scenario would be a very useful and interesting feature that could be added to RapidWright. Since state machines have very deterministic behavior and corresponding implementations, one could image RapidWright taking as input a KISS file with a description of a state machine and generating a synthesized, placed and routed implementation of that state machine given a target FPGA device. All the APIs exist to generate the flip flops, logic and nets to generate the implementation, the code and logic would just need to be created to make it work.

Although I don't have anything to point at today, I think we'll seriously consider this feature in the near future as a way to demonstrate the power and capabilities of RapidWright. If you are interested in learning about what it would take to build such a feature, we can certainly continue that conversation here.

[cyberpunksubru]

Hi,

The idea is to design a generator that implements the FSM based on the kISS file as a RAM based implementation.
Currently, I'm working on the parser code that parses the KISS file and the class that defines the state and stuff.
My aim is to parse it in such a way that the output can be directly implemented onto the device.
Since I'm new to RapidWright (and Vivado as a whole), it's the integration part that I'm confused about. Would you recommend that I start by working on the logical netlist for the FSM implementation first and then move on to its physical implementation?

[clavin-xlnx]

Having the logical implementation first would be a great start. One good resource would be this white paper (WP335) that describes how a block RAM could be used to implement a state machine.

There is an existing implementation of this blockRAM-based state machine in the PYNQ project - tutorial describing it here:
https://www.hackster.io/news/pynq-edition-implementing-fsms-in-the-pl-with-python-768e72cc3bd9
However, I not sure if they use the KISS format.

[cyberpunksubru]

Thanks.

To see if I can sort of figure out how this was done in RapidWright, we wrote a small module with a Block RAM in verilog and made it into a design checkpoint.
Then, we initialised a RapidWright Design variable by reading this checkpoint.
We were hoping we could sort of debug how the structure was formed in our IntelliJ IDE using some commands but cannot figure out how exactly.
Is such a method plausible?

[clavin-xlnx]

If a netlist is relatively small (10-20ish unique cells), it could be feasible to generate it with some code or if there is a very regular structure of some larger pattern of cells. Beyond that, the recommendation would be to combine pre-compiled modules together and "stitch" them into the desired circuit.

In order to build a design in RapidWright from scratch, you will need to construct both a logical netlist and physical netlist. One way is to create the logical netlist fully first (instantiate all of the cells and connect them) by using all the APIs in the edif package. Then you could place the cells using those APIs in the design package.

It sounds like the module you want to prototype seems simple with it mainly consisting of a BlockRAM. We do have an example application that will generate a placed and routed adder/subtractor circuit based on a set of parameters. Perhaps you could try it out--generate a few DCPs and examine them in Vivado--and look at the source code to help you build up a sense of the APIs that are involved. The code is here: https://github.com/Xilinx/RapidWright/blob/master/src/com/xilinx/rapidwright/examples/AddSubGenerator.java.
You can run the example by running (from the RapidWright directory):

// This will generate a sample DCP
java -cp bin:jars/* com.xilinx.rapidwright.examples.AddSubGenerator

You can also print out the available options by adding a -h flag:

java -cp bin:jars/* com.xilinx.rapidwright.examples.AddSubGenerator -h

which yields:

==============================================================================
==                        Adder/Subtractor Generator                        ==
==============================================================================
This RapidWright program creates a placed and routed DCP that can be 
imported into UltraScale+ designs to perform addition or subtraction.  See 
RapidWright documentation for more information.

Option                                   Description                   
------                                   -----------                   
-?, -h                                   Print Help                    
-c [String: Clk net name]                (default: clk)                
-d [String: Design Name]                 (default: addsub)             
-f [Boolean: Adds input pipeline flop]   (default: true)               
-m [Boolean: Subtraction instead of      (default: true)               
  addition]                                                            
-o [String: Output DCP File Name]        (default: slr_crosser.dcp)    
-p [String: UltraScale+ Part Name]       (default: xcvu9p-flgb2104-2-i)
-s [String: Lower left slice to be       (default: SLICE_X101Y480)     
  used for adder/subtracter]                                           
-v [Boolean: Print verbose output]       (default: true)               
-w [Integer: Operand width]              (default: 16)                 
-x [Double: Clk period constraint (ns)]  (default: 1.291)              
          

Come back with questions here if you are still trying to get your head wrapped around it.