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Describe the bug
The sram liberty files generated for the freepdk45 technology appear to be flawed for internal power. The internal power numbers are the same regardless of the polarity of the chip select. Version
Which commit are you using? v1.2.7
To Reproduce
What did you do to demonstrate the bug?
Ran power analysis on a design that used a 1r1w ram to implement a shifting line buffer architecture and power analysis on a circular buffer architecture. The shifting line buffer architecture reads and writes all line buffer memories every clock cycle. The circular architecture reads all memories but only writes one memory every clock cycle.
I then examined the generated liberty file where you can see that the power is the same for csb0 and !csb0
pin(clk0){
clock : true;
direction : input;
capacitance : 0.00020910000000000001;
internal_power(){
when : "!csb0";
rise_power(scalar){
values("4.351111e+00");
}
fall_power(scalar){
values("4.351111e+00");
}
}
internal_power(){
when : "csb0";
rise_power(scalar){
values("4.351111e+00");
}
fall_power(scalar){
values("4.351111e+00");
}
}
Please include your configuration file used.
Expected behavior
I would expect to see much lower power consumption when chip select is disabled. Logs
If applicable, add logs or output to help explain your problem.
Additional context
Add any other context about the problem here. free_config_1w_1r.zip
The text was updated successfully, but these errors were encountered:
Describe the bug
The sram liberty files generated for the freepdk45 technology appear to be flawed for internal power. The internal power numbers are the same regardless of the polarity of the chip select.
Version
Which commit are you using? v1.2.7
To Reproduce
What did you do to demonstrate the bug?
Ran power analysis on a design that used a 1r1w ram to implement a shifting line buffer architecture and power analysis on a circular buffer architecture. The shifting line buffer architecture reads and writes all line buffer memories every clock cycle. The circular architecture reads all memories but only writes one memory every clock cycle.
I then examined the generated liberty file where you can see that the power is the same for csb0 and !csb0
pin(clk0){
clock : true;
direction : input;
capacitance : 0.00020910000000000001;
internal_power(){
when : "!csb0";
rise_power(scalar){
values("4.351111e+00");
}
fall_power(scalar){
values("4.351111e+00");
}
}
internal_power(){
when : "csb0";
rise_power(scalar){
values("4.351111e+00");
}
fall_power(scalar){
values("4.351111e+00");
}
}
Please include your configuration file used.
Expected behavior
I would expect to see much lower power consumption when chip select is disabled.
Logs
If applicable, add logs or output to help explain your problem.
Additional context
Add any other context about the problem here.
free_config_1w_1r.zip
The text was updated successfully, but these errors were encountered: