From 98a788ad30fb8ec9e019d285dcb7ca66d583658b Mon Sep 17 00:00:00 2001 From: VidyaChhabria Date: Mon, 4 Nov 2024 16:02:40 -0700 Subject: [PATCH] Use DESIGN HOME variable in config.mk --- flow/designs/asap7/aes-block/config.mk | 4 +- flow/designs/asap7/aes-mbff/config.mk | 4 +- flow/designs/asap7/aes/config.mk | 4 +- flow/designs/asap7/aes_lvt/config.mk | 4 +- flow/designs/asap7/ethmac/config.mk | 4 +- flow/designs/asap7/ethmac_lvt/config.mk | 4 +- flow/designs/asap7/gcd/config.mk | 4 +- flow/designs/asap7/ibex/config.mk | 4 +- flow/designs/asap7/jpeg/config.mk | 6 +- flow/designs/asap7/jpeg_lvt/config.mk | 6 +- flow/designs/asap7/mock-array/config.mk | 6 +- flow/designs/asap7/mock-cpu/config.mk | 4 +- .../fakeram7_256x32/config.mk | 4 +- flow/designs/asap7/riscv32i/config.mk | 4 +- flow/designs/asap7/swerv_wrapper/config.mk | 10 +-- flow/designs/asap7/uart/config.mk | 4 +- flow/designs/gf12/aes/config.mk | 4 +- flow/designs/gf12/ariane/config.mk | 10 +-- flow/designs/gf12/ariane133/config.mk | 2 +- flow/designs/gf12/bp_single/config.mk | 2 +- flow/designs/gf12/coyote/config.mk | 8 +- flow/designs/gf12/gcd/config.mk | 4 +- flow/designs/gf12/ibex/config.mk | 82 +++++++++--------- flow/designs/gf12/jpeg/config.mk | 6 +- flow/designs/gf12/swerv_wrapper/config.mk | 8 +- flow/designs/gf12/tinyRocket/config.mk | 16 ++-- flow/designs/gf180/aes-hybrid/config.mk | 8 +- flow/designs/gf180/aes/config.mk | 4 +- flow/designs/gf180/ibex/config.mk | 76 ++++++++--------- flow/designs/gf180/jpeg/config.mk | 6 +- flow/designs/gf180/riscv32i/config.mk | 4 +- flow/designs/gf180/uart-blocks/config.mk | 8 +- .../gf180/uart-blocks/uart_rx/config.mk | 6 +- flow/designs/gf55/aes/config.mk | 2 +- flow/designs/ihp-sg13g2/aes/config.mk | 4 +- flow/designs/ihp-sg13g2/gcd/config.mk | 4 +- flow/designs/ihp-sg13g2/ibex/config.mk | 76 ++++++++--------- flow/designs/ihp-sg13g2/jpeg/config.mk | 6 +- flow/designs/ihp-sg13g2/riscv32i/config.mk | 4 +- flow/designs/ihp-sg13g2/spi/config.mk | 4 +- flow/designs/intel16/gcd/config.mk | 4 +- flow/designs/intel22/jpeg/config.mk | 2 +- flow/designs/nangate45/aes/config.mk | 6 +- flow/designs/nangate45/ariane133/config.mk | 6 +- flow/designs/nangate45/ariane136/config.mk | 6 +- flow/designs/nangate45/black_parrot/config.mk | 6 +- flow/designs/nangate45/bp_be_top/config.mk | 6 +- flow/designs/nangate45/bp_fe_top/config.mk | 6 +- flow/designs/nangate45/bp_multi_top/config.mk | 6 +- flow/designs/nangate45/bp_quad/config.mk | 6 +- flow/designs/nangate45/dynamic_node/config.mk | 4 +- flow/designs/nangate45/gcd/config.mk | 4 +- flow/designs/nangate45/ibex/config.mk | 84 +++++++++---------- flow/designs/nangate45/jpeg/config.mk | 6 +- .../designs/nangate45/mempool_group/config.mk | 6 +- flow/designs/nangate45/swerv/config.mk | 4 +- .../designs/nangate45/swerv_wrapper/config.mk | 8 +- flow/designs/nangate45/tinyRocket/config.mk | 18 ++-- flow/designs/sky130hd/aes/config.mk | 6 +- flow/designs/sky130hd/chameleon/config.mk | 46 +++++----- .../chameleon_hier/DFFRAM_4K/config.mk | 4 +- .../chameleon_hier/DMC_32x16HC/config.mk | 4 +- .../chameleon_hier/apb_sys_0/config.mk | 4 +- .../designs/sky130hd/chameleon_hier/config.mk | 42 +++++----- .../chameleon_hier/ibex_wrapper/config.mk | 4 +- flow/designs/sky130hd/coyote_tc/config.mk | 14 ++-- flow/designs/sky130hd/gcd/config.mk | 4 +- flow/designs/sky130hd/ibex/config.mk | 78 ++++++++--------- flow/designs/sky130hd/jpeg/config.mk | 8 +- flow/designs/sky130hd/microwatt/config.mk | 8 +- flow/designs/sky130hd/riscv32i/config.mk | 4 +- flow/designs/sky130hd_fakestack/aes/config.mk | 4 +- .../sky130hd_fakestack/ariane136/config.mk | 6 +- flow/designs/sky130hd_fakestack/gcd/config.mk | 4 +- flow/designs/sky130hs/aes/config.mk | 4 +- flow/designs/sky130hs/coyote_tc/config.mk | 18 ++-- flow/designs/sky130hs/gcd/config.mk | 4 +- flow/designs/sky130hs/ibex/config.mk | 76 ++++++++--------- flow/designs/sky130hs/jpeg/config.mk | 6 +- flow/designs/sky130hs/riscv32i/config.mk | 6 +- flow/designs/tsmc65lp/aes/config.mk | 4 +- flow/designs/tsmc65lp/ariane/config.mk | 6 +- flow/designs/tsmc65lp/black_parrot/config.mk | 6 +- flow/designs/tsmc65lp/bp_be_top/config.mk | 6 +- flow/designs/tsmc65lp/bp_fe_top/config.mk | 6 +- flow/designs/tsmc65lp/bp_multi_top/config.mk | 6 +- flow/designs/tsmc65lp/coyote/config.mk | 8 +- flow/designs/tsmc65lp/dynamic_node/config.mk | 4 +- flow/designs/tsmc65lp/gcd/config.mk | 4 +- flow/designs/tsmc65lp/ibex/config.mk | 76 ++++++++--------- flow/designs/tsmc65lp/jpeg/config.mk | 6 +- flow/designs/tsmc65lp/swerv/config.mk | 4 +- flow/designs/tsmc65lp/swerv_wrapper/config.mk | 6 +- flow/designs/tsmc65lp/tinyRocket/config.mk | 14 ++-- flow/designs/tsmc65lp/vanilla5/config.mk | 4 +- 95 files changed, 566 insertions(+), 566 deletions(-) diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk index d13c524ee9..79520f6b4c 100644 --- a/flow/designs/asap7/aes-block/config.mk +++ b/flow/designs/asap7/aes-block/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = aes_cipher_top export DESIGN_NICKNAME = aes-block -export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/aes-mbff/config.mk b/flow/designs/asap7/aes-mbff/config.mk index d1a31fe77d..ac7f0f1aa8 100644 --- a/flow/designs/asap7/aes-mbff/config.mk +++ b/flow/designs/asap7/aes-mbff/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = aes_cipher_top export DESIGN_NICKNAME = aes-mbff -export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/aes/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/aes/config.mk b/flow/designs/asap7/aes/config.mk index 05cd01aeee..fa660b726e 100644 --- a/flow/designs/asap7/aes/config.mk +++ b/flow/designs/asap7/aes/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = aes_cipher_top export DESIGN_NICKNAME = aes -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/aes_lvt/config.mk b/flow/designs/asap7/aes_lvt/config.mk index 1ae7270e25..e3d1779d9b 100644 --- a/flow/designs/asap7/aes_lvt/config.mk +++ b/flow/designs/asap7/aes_lvt/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = aes_cipher_top export DESIGN_NICKNAME = aes_lvt -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/ethmac/config.mk b/flow/designs/asap7/ethmac/config.mk index 00efe3335c..fad9fb1cca 100644 --- a/flow/designs/asap7/ethmac/config.mk +++ b/flow/designs/asap7/ethmac/config.mk @@ -2,8 +2,8 @@ export PLATFORM = asap7 export DESIGN_NAME = ethmac -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/asap7/ethmac_lvt/config.mk b/flow/designs/asap7/ethmac_lvt/config.mk index 0135606146..21dc689e75 100644 --- a/flow/designs/asap7/ethmac_lvt/config.mk +++ b/flow/designs/asap7/ethmac_lvt/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = ethmac export DESIGN_NICKNAME = ethmac_lvt -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/asap7/gcd/config.mk b/flow/designs/asap7/gcd/config.mk index 699ddae5b7..35d247211a 100644 --- a/flow/designs/asap7/gcd/config.mk +++ b/flow/designs/asap7/gcd/config.mk @@ -2,8 +2,8 @@ export PLATFORM = asap7 export DESIGN_NAME = gcd -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export DIE_AREA = 0 0 16.2 16.2 export CORE_AREA = 1.08 1.08 15.12 15.12 diff --git a/flow/designs/asap7/ibex/config.mk b/flow/designs/asap7/ibex/config.mk index 53e54ba599..b49ef0dac7 100644 --- a/flow/designs/asap7/ibex/config.mk +++ b/flow/designs/asap7/ibex/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/asap7/jpeg/config.mk b/flow/designs/asap7/jpeg/config.mk index d23d475a8c..f00ea0e782 100644 --- a/flow/designs/asap7/jpeg/config.mk +++ b/flow/designs/asap7/jpeg/config.mk @@ -3,9 +3,9 @@ export PLATFORM = asap7 export DESIGN_NAME = jpeg_encoder export DESIGN_NICKNAME = jpeg -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 30 diff --git a/flow/designs/asap7/jpeg_lvt/config.mk b/flow/designs/asap7/jpeg_lvt/config.mk index 2e5369ae4d..975596c3a4 100644 --- a/flow/designs/asap7/jpeg_lvt/config.mk +++ b/flow/designs/asap7/jpeg_lvt/config.mk @@ -3,9 +3,9 @@ export PLATFORM = asap7 export DESIGN_NAME = jpeg_encoder export DESIGN_NICKNAME = jpeg_lvt -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc export ABC_AREA = 1 export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \ diff --git a/flow/designs/asap7/mock-array/config.mk b/flow/designs/asap7/mock-array/config.mk index 214aa3868c..f5f04eca76 100644 --- a/flow/designs/asap7/mock-array/config.mk +++ b/flow/designs/asap7/mock-array/config.mk @@ -32,7 +32,7 @@ export BLOCKS ?= Element ifneq ($(BLOCKS),) export GDS_ALLOW_EMPTY = Element ifneq ($(RTLMP_FLOW), 1) - export MACRO_PLACEMENT_TCL = ./designs/asap7/mock-array/macro-placement.tcl + export MACRO_PLACEMENT_TCL = $(DESIGN_HOME)/asap7/mock-array/macro-placement.tcl endif export PDN_TCL = $(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl endif @@ -44,13 +44,13 @@ export IO_CONSTRAINTS = designs/asap7/mock-array/io.tcl verilog: export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \ export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \ - ./designs/asap7/mock-array/verilog.sh + $(DESIGN_HOME)/asap7/mock-array/verilog.sh .PHONY: simulate simulate: export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \ export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \ - ./designs/asap7/mock-array/simulate.sh + $(DESIGN_HOME)/asap7/mock-array/simulate.sh .PHONY: power power: diff --git a/flow/designs/asap7/mock-cpu/config.mk b/flow/designs/asap7/mock-cpu/config.mk index f486f52e96..2eb0c35ac2 100644 --- a/flow/designs/asap7/mock-cpu/config.mk +++ b/flow/designs/asap7/mock-cpu/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = mock_cpu export DESIGN_NICKNAME = mock-cpu -export VERILOG_FILES = $(wildcard ./designs/src/fifo/*.v) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(wildcard $(DESIGN_HOME)/src/fifo/*.v) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk index b4c53955fb..a029c68794 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk +++ b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i-mock-sram_fakeram7_256x32 export DESIGN_NAME = fakeram7_256x32 export PLATFORM = asap7 -export VERILOG_FILES = ./designs/asap7/riscv32i-mock-sram/fakeram7_256x32/*.v -export SDC_FILE = ./designs/$(PLATFORM)/riscv32i-mock-sram/fakeram7_256x32/constraints.sdc +export VERILOG_FILES = $(DESIGN_HOME)/asap7/riscv32i-mock-sram/fakeram7_256x32/*.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/riscv32i-mock-sram/fakeram7_256x32/constraints.sdc export CORE_UTILIZATION = 50 export CORE_ASPECT_RATIO = 8 diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk index 5d235ac63d..d129acb64e 100644 --- a/flow/designs/asap7/riscv32i/config.mk +++ b/flow/designs/asap7/riscv32i/config.mk @@ -11,8 +11,8 @@ export RTLMP_MAX_MACRO = 5 export MAX_UNGROUP_SIZE ?= 1000 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/riscv32i/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/riscv32i/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/riscv32i/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/riscv32i/constraint.sdc ifeq ($(BLOCKS),) export ADDITIONAL_LEFS = ./platforms/$(PLATFORM)/lef/fakeram7_256x32.lef diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk index 80fa22d9c7..2a42119d6d 100644 --- a/flow/designs/asap7/swerv_wrapper/config.mk +++ b/flow/designs/asap7/swerv_wrapper/config.mk @@ -10,12 +10,12 @@ export RTLMP_MIN_MACRO = 4 export LIB_MODEL = CCS -export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \ - ./designs/$(PLATFORM)/swerv_wrapper/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/swerv_wrapper/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc -export ADDITIONAL_LEFS = $(sort $(wildcard ./designs/$(PLATFORM)/swerv_wrapper/lef/*.lef)) -export ADDITIONAL_LIBS = $(sort $(wildcard ./designs/$(PLATFORM)/swerv_wrapper/lib/*.lib)) +export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lef/*.lef)) +export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lib/*.lib)) export DIE_AREA = 0 0 550 600 export CORE_AREA = 5 5 545 595 diff --git a/flow/designs/asap7/uart/config.mk b/flow/designs/asap7/uart/config.mk index 5f00ce2e2d..6d980d3f7d 100644 --- a/flow/designs/asap7/uart/config.mk +++ b/flow/designs/asap7/uart/config.mk @@ -3,8 +3,8 @@ export CORNER = TC export DESIGN_NAME = uart -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export PLACE_DENSITY = 0.70 export DIE_AREA = 0 0 17 17 diff --git a/flow/designs/gf12/aes/config.mk b/flow/designs/gf12/aes/config.mk index d6797c3930..7145449318 100644 --- a/flow/designs/gf12/aes/config.mk +++ b/flow/designs/gf12/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = gf12 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk index 22a38dcdf4..bc3ef63e47 100644 --- a/flow/designs/gf12/ariane/config.mk +++ b/flow/designs/gf12/ariane/config.mk @@ -5,11 +5,11 @@ export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE ?= 10000 # -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -#export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint_hier.sdc +#export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint_hier.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12lp_1rf_lg8_w64_byte.lef @@ -27,7 +27,7 @@ export PLACE_PINS_ARGS = -exclude left:0-150 -exclude left:450-600 -exclude righ export MACRO_PLACE_HALO = 7 7 export MACRO_PLACE_CHANNEL = 14 14 -export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl ifeq ($(USE_FILL),1) export DESIGN_TYPE = CELL diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk index 51dc5f6dc9..fb084b725a 100644 --- a/flow/designs/gf12/ariane133/config.mk +++ b/flow/designs/gf12/ariane133/config.mk @@ -9,7 +9,7 @@ export MAX_UNGROUP_SIZE ?= 10000 export VERILOG_FILES = $(PLATFORM_DIR)/ariane133/ariane.v -export SDC_FILE = ./designs/$(PLATFORM)/ariane133/ariane.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ariane133/ariane.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk index f10c8732bf..8a9a24d646 100644 --- a/flow/designs/gf12/bp_single/config.mk +++ b/flow/designs/gf12/bp_single/config.mk @@ -61,7 +61,7 @@ export MACRO_PLACEMENT = $(PLATFORM_DIR)/bp/auto_fence2_bp_single.macro_placment export MACRO_BLOCKAGE_HALO = 25 export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl ifeq ($(USE_FILL),1) export DESIGN_TYPE = CHIP diff --git a/flow/designs/gf12/coyote/config.mk b/flow/designs/gf12/coyote/config.mk index 5a754be25b..db5c537c5c 100644 --- a/flow/designs/gf12/coyote/config.mk +++ b/flow/designs/gf12/coyote/config.mk @@ -2,10 +2,10 @@ export DESIGN_NICKNAME = coyote export DESIGN_NAME = bsg_rocket_node_client_rocc export PLATFORM = gf12 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w80_bit.lef \ @@ -25,7 +25,7 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg6_w80_bit.gds2 \ export PLACE_DENSITY = 0.35 -export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl export DIE_AREA = 0 0 752 752 export CORE_AREA = 2 2 750 750 diff --git a/flow/designs/gf12/gcd/config.mk b/flow/designs/gf12/gcd/config.mk index f35f197557..470e63993d 100644 --- a/flow/designs/gf12/gcd/config.mk +++ b/flow/designs/gf12/gcd/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = gcd_$(TRACK_OPTION)_$(TECH_OPTION) export DESIGN_NAME = gcd export PLATFORM = gf12 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc # These values must be multiples of placement site export DIE_AREA = 0 0 99.96 100.128 diff --git a/flow/designs/gf12/ibex/config.mk b/flow/designs/gf12/ibex/config.mk index 54be100405..c94bfc69e1 100644 --- a/flow/designs/gf12/ibex/config.mk +++ b/flow/designs/gf12/ibex/config.mk @@ -3,47 +3,47 @@ export DESIGN_NAME = ibex_core export PLATFORM = gf12 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - - - -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v + + + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/gf12/jpeg/config.mk b/flow/designs/gf12/jpeg/config.mk index df448a8a43..3a817b948a 100644 --- a/flow/designs/gf12/jpeg/config.mk +++ b/flow/designs/gf12/jpeg/config.mk @@ -2,10 +2,10 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = gf12 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk index 6ebac68cbc..56b208a44d 100644 --- a/flow/designs/gf12/swerv_wrapper/config.mk +++ b/flow/designs/gf12/swerv_wrapper/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg11_w40_all.lef \ $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w22_all.lef \ @@ -32,7 +32,7 @@ export CORE_AREA = 2 2 608 498 export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-10 -exclude bottom:400-700 export PLACE_DENSITY_LB_ADDON = 0.05 -export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl # export MACRO_PLACE_HALO = 7 7 export MACRO_PLACE_CHANNEL = 14 14 diff --git a/flow/designs/gf12/tinyRocket/config.mk b/flow/designs/gf12/tinyRocket/config.mk index 673bfe72b0..98eeb8da2e 100644 --- a/flow/designs/gf12/tinyRocket/config.mk +++ b/flow/designs/gf12/tinyRocket/config.mk @@ -5,14 +5,14 @@ export PLATFORM = gf12 export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE ?= 1000 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ - ./designs/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ - ./designs/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_all.lef \ $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_byte.lef @@ -31,7 +31,7 @@ export CORE_AREA = 19.992 20.16 380.016 380.16 export PLACE_DENSITY = 0.20 -export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl ifeq ($(USE_FILL),1) export DESIGN_TYPE = CELL diff --git a/flow/designs/gf180/aes-hybrid/config.mk b/flow/designs/gf180/aes-hybrid/config.mk index 2113b1a32f..7da1e35827 100644 --- a/flow/designs/gf180/aes-hybrid/config.mk +++ b/flow/designs/gf180/aes-hybrid/config.mk @@ -3,7 +3,7 @@ export DESIGN_NAME = aes_cipher_top export PLATFORM = gf180 # See the README -export SC_LEF = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/adjusted-gf180mcu_5LM_1TM_9K_9t_sc.lef +export SC_LEF = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/adjusted-gf180mcu_5LM_1TM_9K_9t_sc.lef export BC_ADDITIONAL_LIB_FILES = gf180mcu_fd_sc_mcu7t$(POWER_OPTION)__ff_n40C_5v50.lib.gz @@ -11,7 +11,7 @@ export WC_ADDITIONAL_LIB_FILES = gf180mcu_fd_sc_mcu7t$(POWER_OPTION)__ss_125C_4v export TC_ADDITIONAL_LIB_FILES = gf180mcu_fd_sc_mcu7t$(POWER_OPTION)__tt_025C_5v00.lib.gz -export ADDITIONAL_LEFS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/hybrid_sites.lef \ +export ADDITIONAL_LEFS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/hybrid_sites.lef \ $(PLATFORM_DIR)/lef/gf180mcu_5LM_1TM_9K_7t_sc.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/$($(CORNER)_ADDITIONAL_LIB_FILES) #export ADDITIONAL_GDS = $(wildcard $(PLATFORM_DIR)/gds/7t/*.gds) @@ -20,8 +20,8 @@ export GDS_ALLOW_EMPTY = gf180mcu_fd_sc_mcu7t5v0__.* export PLACE_SITE = sc9sc7 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/aes/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 30 diff --git a/flow/designs/gf180/aes/config.mk b/flow/designs/gf180/aes/config.mk index c11063120d..74abc9da2d 100644 --- a/flow/designs/gf180/aes/config.mk +++ b/flow/designs/gf180/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = gf180 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 35 diff --git a/flow/designs/gf180/ibex/config.mk b/flow/designs/gf180/ibex/config.mk index 0954f47fc0..ebeeadf520 100644 --- a/flow/designs/gf180/ibex/config.mk +++ b/flow/designs/gf180/ibex/config.mk @@ -2,45 +2,45 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = gf180 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.1 diff --git a/flow/designs/gf180/jpeg/config.mk b/flow/designs/gf180/jpeg/config.mk index f3d6be3acd..edce7ef623 100644 --- a/flow/designs/gf180/jpeg/config.mk +++ b/flow/designs/gf180/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = gf180 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.20 diff --git a/flow/designs/gf180/riscv32i/config.mk b/flow/designs/gf180/riscv32i/config.mk index 5ebdc8f5be..7fd7df9230 100644 --- a/flow/designs/gf180/riscv32i/config.mk +++ b/flow/designs/gf180/riscv32i/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i export DESIGN_NAME = riscv export PLATFORM = gf180 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 diff --git a/flow/designs/gf180/uart-blocks/config.mk b/flow/designs/gf180/uart-blocks/config.mk index 033e53d088..70ba7881f3 100644 --- a/flow/designs/gf180/uart-blocks/config.mk +++ b/flow/designs/gf180/uart-blocks/config.mk @@ -3,8 +3,8 @@ export PLATFORM = gf180 export DESIGN_NAME = uart export DESIGN_NICKNAME = uart-blocks -export VERILOG_FILES = ./designs/src/uart-no-param/*.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/uart-no-param/*.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export SYNTH_HIERARCHICAL = 1 export BLOCKS = uart_rx @@ -17,9 +17,9 @@ export PLACE_PINS_ARGS = -exclude bottom:* -exclude top:* -exclude right:* export MACRO_PLACE_HALO = 20 20 export MACRO_PLACE_CHANNEL = 20 20 -export PDN_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/BLOCKS_grid_strategy.tcl +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/BLOCKS_grid_strategy.tcl export PLACE_DENSITY = 0.60 -export TAPCELL_TCL ?= ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/tapcell.tcl +export TAPCELL_TCL ?= $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/tapcell.tcl export MACRO_HALO_X = 14 export MACRO_HALO_Y = 14 diff --git a/flow/designs/gf180/uart-blocks/uart_rx/config.mk b/flow/designs/gf180/uart-blocks/uart_rx/config.mk index 688159feff..28d3e1aaf4 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/config.mk +++ b/flow/designs/gf180/uart-blocks/uart_rx/config.mk @@ -3,15 +3,15 @@ export PLATFORM = gf180 export DESIGN_NAME = uart_rx export DESIGN_NICKNAME = uart-blocks_uart_rx -export VERILOG_FILES = ./designs/src/uart-no-param/*.v -export SDC_FILE = ./designs/$(PLATFORM)/uart-blocks/uart_rx/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/uart-no-param/*.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/uart-blocks/uart_rx/constraint.sdc export CORE_UTILIZATION = 30 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 export PLACE_DENSITY = 0.60 -export PDN_TCL = ./designs/$(PLATFORM)/uart-blocks/BLOCKS_grid_strategy.tcl +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/uart-blocks/BLOCKS_grid_strategy.tcl export PLACE_PINS_ARGS = -exclude bottom:* -exclude top:* -exclude right:* diff --git a/flow/designs/gf55/aes/config.mk b/flow/designs/gf55/aes/config.mk index 2ba971e3fd..51640fcc8d 100644 --- a/flow/designs/gf55/aes/config.mk +++ b/flow/designs/gf55/aes/config.mk @@ -5,7 +5,7 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = gf55 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) export SDC_FILE = $(DESIGN_DIR)/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/ihp-sg13g2/aes/config.mk b/flow/designs/ihp-sg13g2/aes/config.mk index c72e089d8d..5acb53d84d 100644 --- a/flow/designs/ihp-sg13g2/aes/config.mk +++ b/flow/designs/ihp-sg13g2/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 20 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/ihp-sg13g2/gcd/config.mk b/flow/designs/ihp-sg13g2/gcd/config.mk index a6d9895c17..7fceb006ae 100644 --- a/flow/designs/ihp-sg13g2/gcd/config.mk +++ b/flow/designs/ihp-sg13g2/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export USE_FILL = 1 diff --git a/flow/designs/ihp-sg13g2/ibex/config.mk b/flow/designs/ihp-sg13g2/ibex/config.mk index ed352f6283..8565d7e0b5 100644 --- a/flow/designs/ihp-sg13g2/ibex/config.mk +++ b/flow/designs/ihp-sg13g2/ibex/config.mk @@ -2,45 +2,45 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # Adders degrade ibex setup repair export ADDER_MAP_FILE := diff --git a/flow/designs/ihp-sg13g2/jpeg/config.mk b/flow/designs/ihp-sg13g2/jpeg/config.mk index e9a0fd1083..79fe5ed4a4 100644 --- a/flow/designs/ihp-sg13g2/jpeg/config.mk +++ b/flow/designs/ihp-sg13g2/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 55 export PLACE_DENSITY_LB_ADDON = 0.20 diff --git a/flow/designs/ihp-sg13g2/riscv32i/config.mk b/flow/designs/ihp-sg13g2/riscv32i/config.mk index 47593d42ff..43bbc9f064 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/config.mk +++ b/flow/designs/ihp-sg13g2/riscv32i/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i export DESIGN_NAME = riscv export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export USE_FILL 1 diff --git a/flow/designs/ihp-sg13g2/spi/config.mk b/flow/designs/ihp-sg13g2/spi/config.mk index 995e7e0a47..d791fbec23 100644 --- a/flow/designs/ihp-sg13g2/spi/config.mk +++ b/flow/designs/ihp-sg13g2/spi/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = spi export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/spi.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/spi.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export USE_FILL = 1 diff --git a/flow/designs/intel16/gcd/config.mk b/flow/designs/intel16/gcd/config.mk index bb23ac570f..6d857dfbd6 100644 --- a/flow/designs/intel16/gcd/config.mk +++ b/flow/designs/intel16/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = intel16 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ABC_AREA = 1 # Adders degrade GCD diff --git a/flow/designs/intel22/jpeg/config.mk b/flow/designs/intel22/jpeg/config.mk index 3ca6ed0df8..246f63bb3f 100644 --- a/flow/designs/intel22/jpeg/config.mk +++ b/flow/designs/intel22/jpeg/config.mk @@ -6,7 +6,7 @@ export DESIGN_NAME = jpeg_encoder export PLATFORM = intel22 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include export SDC_FILE = $(DESIGN_DIR)/constraint.sdc export CORE_UTILIZATION = 30 diff --git a/flow/designs/nangate45/aes/config.mk b/flow/designs/nangate45/aes/config.mk index a797e9ff36..f653445292 100644 --- a/flow/designs/nangate45/aes/config.mk +++ b/flow/designs/nangate45/aes/config.mk @@ -2,10 +2,10 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = nangate45 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export FLOORPLAN_DEF = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/aes_ng45_fp.def +export FLOORPLAN_DEF = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/aes_ng45_fp.def export PLACE_DENSITY_LB_ADDON = 0.20 export TNS_END_PERCENT = 100 diff --git a/flow/designs/nangate45/ariane133/config.mk b/flow/designs/nangate45/ariane133/config.mk index d440d5f4f2..6790881b88 100644 --- a/flow/designs/nangate45/ariane133/config.mk +++ b/flow/designs/nangate45/ariane133/config.mk @@ -10,10 +10,10 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 16 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/ariane133/ariane.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ariane133/ariane.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x16.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x16.lib diff --git a/flow/designs/nangate45/ariane136/config.mk b/flow/designs/nangate45/ariane136/config.mk index 6fdc44d170..a730c66d84 100644 --- a/flow/designs/nangate45/ariane136/config.mk +++ b/flow/designs/nangate45/ariane136/config.mk @@ -11,10 +11,10 @@ export RTLMP_MAX_MACRO = 16 export RTLMP_MIN_MACRO = 4 export RTLMP_SIGNATURE_NET_THRESHOLD = 30 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x16.lef diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk index be943c4c9d..16e60bd058 100644 --- a/flow/designs/nangate45/black_parrot/config.mk +++ b/flow/designs/nangate45/black_parrot/config.mk @@ -10,12 +10,12 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v export ABC_AREA = 1 -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_512x64.lef \ $(PLATFORM_DIR)/lef/fakeram45_256x95.lef \ diff --git a/flow/designs/nangate45/bp_be_top/config.mk b/flow/designs/nangate45/bp_be_top/config.mk index 08f2628621..6d21176d60 100644 --- a/flow/designs/nangate45/bp_be_top/config.mk +++ b/flow/designs/nangate45/bp_be_top/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_512x64.lef \ $(PLATFORM_DIR)/lef/fakeram45_64x15.lef \ diff --git a/flow/designs/nangate45/bp_fe_top/config.mk b/flow/designs/nangate45/bp_fe_top/config.mk index 8a5b3a516c..aa6cc60fe8 100644 --- a/flow/designs/nangate45/bp_fe_top/config.mk +++ b/flow/designs/nangate45/bp_fe_top/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_512x64.lef \ $(PLATFORM_DIR)/lef/fakeram45_64x7.lef \ diff --git a/flow/designs/nangate45/bp_multi_top/config.mk b/flow/designs/nangate45/bp_multi_top/config.mk index 59c9975a36..71ce929ee1 100644 --- a/flow/designs/nangate45/bp_multi_top/config.mk +++ b/flow/designs/nangate45/bp_multi_top/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ABC_AREA = 1 export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_512x64.lef \ diff --git a/flow/designs/nangate45/bp_quad/config.mk b/flow/designs/nangate45/bp_quad/config.mk index f55ffdd96f..4064f9bb17 100644 --- a/flow/designs/nangate45/bp_quad/config.mk +++ b/flow/designs/nangate45/bp_quad/config.mk @@ -10,10 +10,10 @@ export SYNTH_HIERARCHICAL = 1 #export RTLMP_MAX_MACRO = 16 #export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/bsg_chip_block.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/bsg_chip_block.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/bsg_chip.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/bsg_chip.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x48.lef \ $(PLATFORM_DIR)/lef/fakeram45_32x32.lef \ diff --git a/flow/designs/nangate45/dynamic_node/config.mk b/flow/designs/nangate45/dynamic_node/config.mk index ac7805eea3..33365ed46c 100644 --- a/flow/designs/nangate45/dynamic_node/config.mk +++ b/flow/designs/nangate45/dynamic_node/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = dynamic_node export DESIGN_NAME = dynamic_node_top_wrap export PLATFORM = nangate45 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 diff --git a/flow/designs/nangate45/gcd/config.mk b/flow/designs/nangate45/gcd/config.mk index 536991d4d2..1b61b78af4 100644 --- a/flow/designs/nangate45/gcd/config.mk +++ b/flow/designs/nangate45/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = nangate45 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ABC_AREA = 1 # Adders degrade GCD diff --git a/flow/designs/nangate45/ibex/config.mk b/flow/designs/nangate45/ibex/config.mk index 4b4db1cfd5..8d6843f00e 100644 --- a/flow/designs/nangate45/ibex/config.mk +++ b/flow/designs/nangate45/ibex/config.mk @@ -4,48 +4,48 @@ export PLATFORM = nangate45 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - - - - -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v + + + + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION ?= 50 export PLACE_DENSITY_LB_ADDON = 0.20 diff --git a/flow/designs/nangate45/jpeg/config.mk b/flow/designs/nangate45/jpeg/config.mk index 55a99dd60d..ff8578ccd2 100644 --- a/flow/designs/nangate45/jpeg/config.mk +++ b/flow/designs/nangate45/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = nangate45 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION ?= 45 diff --git a/flow/designs/nangate45/mempool_group/config.mk b/flow/designs/nangate45/mempool_group/config.mk index 4859cff4e6..50d4c1ee76 100644 --- a/flow/designs/nangate45/mempool_group/config.mk +++ b/flow/designs/nangate45/mempool_group/config.mk @@ -4,10 +4,10 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 -export TEMP_DESIGN_DIR = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME) -export VERILOG_FILES = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v +export TEMP_DESIGN_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) +export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x32.lef \ $(PLATFORM_DIR)/lef/fakeram45_64x64.lef \ diff --git a/flow/designs/nangate45/swerv/config.mk b/flow/designs/nangate45/swerv/config.mk index 93210cf09f..6625aced49 100644 --- a/flow/designs/nangate45/swerv/config.mk +++ b/flow/designs/nangate45/swerv/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = swerv export PLATFORM = nangate45 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk index d464f44273..f6e9fc3430 100644 --- a/flow/designs/nangate45/swerv_wrapper/config.mk +++ b/flow/designs/nangate45/swerv_wrapper/config.mk @@ -9,9 +9,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \ - ./designs/$(PLATFORM)/swerv/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/swerv_wrapper/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/swerv/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_2048x39.lef \ $(PLATFORM_DIR)/lef/fakeram45_256x34.lef \ @@ -31,5 +31,5 @@ export MACRO_PLACE_CHANNEL = 20 20 export PLACE_DENSITY_LB_ADDON = 0.10 export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl diff --git a/flow/designs/nangate45/tinyRocket/config.mk b/flow/designs/nangate45/tinyRocket/config.mk index 3ba4266214..d06262dd95 100644 --- a/flow/designs/nangate45/tinyRocket/config.mk +++ b/flow/designs/nangate45/tinyRocket/config.mk @@ -5,17 +5,17 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE ?= 5000 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ - ./designs/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ - ./designs/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export ADDITIONAL_LEFS = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lef)) -export ADDITIONAL_LIBS = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lib)) +export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lef)) +export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lib)) # These values must be multiples of placement site diff --git a/flow/designs/sky130hd/aes/config.mk b/flow/designs/sky130hd/aes/config.mk index 7195ef15bd..a7fdf67708 100644 --- a/flow/designs/sky130hd/aes/config.mk +++ b/flow/designs/sky130hd/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = sky130hd -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export PLACE_PINS_ARGS = -min_distance 4 -min_distance_in_tracks @@ -14,7 +14,7 @@ export CORE_MARGIN = 2 export PLACE_DENSITY = 0.6 export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/sky130hd/chameleon/config.mk b/flow/designs/sky130hd/chameleon/config.mk index 375321a149..be2a73d697 100644 --- a/flow/designs/sky130hd/chameleon/config.mk +++ b/flow/designs/sky130hd/chameleon/config.mk @@ -2,37 +2,37 @@ export DESIGN_NICKNAME = chameleon export DESIGN_NAME = soc_core export PLATFORM = sky130hd -export VERILOG_FILES_BLACKBOX = ./designs/src/$(DESIGN_NICKNAME)/ibex/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/DFFRAM_4K.v \ - ./designs/src/$(DESIGN_NICKNAME)/AHB_sys_0/APB_sys_0/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/DMC_32x16HC.v - -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/acc/AHB_SPM.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/AHBSRAM.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/DFFRAMBB.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/GPIO.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/APB_I2C.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/APB_SPI.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/APB_UART.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/i2c_master.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/PWM32.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/RAM_3Kx32.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/QSPI_XIP_CTRL.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/spi_master.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/TIMER32.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/WDT32.v \ - ./designs/src/$(DESIGN_NICKNAME)/AHB_sys_0/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/soc_core.v \ +export VERILOG_FILES_BLACKBOX = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/DFFRAM_4K.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AHB_sys_0/APB_sys_0/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/DMC_32x16HC.v + +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/acc/AHB_SPM.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/AHBSRAM.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/DFFRAMBB.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/GPIO.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/APB_I2C.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/APB_SPI.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/APB_UART.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/i2c_master.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/PWM32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/RAM_3Kx32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/QSPI_XIP_CTRL.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/spi_master.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/TIMER32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/WDT32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AHB_sys_0/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/soc_core.v \ $(VERILOG_FILES_BLACKBOX) export ABC_AREA = 1 -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export DIE_AREA = 0 0 2920 3520 export CORE_AREA = 20 20 2900 3500 -export chameleon_DIR = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME) +export chameleon_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) export ADDITIONAL_GDS = $(chameleon_DIR)/gds/apb_sys_0.gds.gz \ $(chameleon_DIR)/gds/DMC_32x16HC.gds.gz \ diff --git a/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk b/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk index 19c59dfd34..7a3fe7c767 100644 --- a/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk @@ -1,10 +1,10 @@ export TOP_NICKNAME = chameleon_hier -export TOP_DIR = ./designs/$(PLATFORM)/${TOP_NICKNAME} +export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} export DESIGN_NAME = DFFRAM_4K export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} export PLATFORM = sky130hd -export RTL_DIR = ./designs/src/${TOP_NICKNAME}/rtl +export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl export VERILOG_FILES = \ ${RTL_DIR}/IPs/DFFRAM_4K.v \ diff --git a/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk b/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk index e29494e4ac..c63c632188 100644 --- a/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk @@ -1,10 +1,10 @@ export TOP_NICKNAME = chameleon_hier -export TOP_DIR = ./designs/$(PLATFORM)/${TOP_NICKNAME} +export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} export DESIGN_NAME = DMC_32x16HC export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} export PLATFORM = sky130hd -export RTL_DIR = ./designs/src/${TOP_NICKNAME}/rtl +export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl export VERILOG_FILES = \ ${RTL_DIR}/IPs/DFFRAMBB.v \ diff --git a/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk b/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk index 31a2cfd9e1..9ad85c0488 100644 --- a/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk @@ -1,10 +1,10 @@ export TOP_NICKNAME = chameleon_hier -export TOP_DIR = ./designs/$(PLATFORM)/${TOP_NICKNAME} +export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} export DESIGN_NAME = apb_sys_0 export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} export PLATFORM = sky130hd -export RTL_DIR = ./designs/src/${TOP_NICKNAME}/rtl +export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl export VERILOG_FILES = \ ${RTL_DIR}/AHB_sys_0/APB_sys_0/*\ diff --git a/flow/designs/sky130hd/chameleon_hier/config.mk b/flow/designs/sky130hd/chameleon_hier/config.mk index ceb86b845a..cd63d0fa5b 100644 --- a/flow/designs/sky130hd/chameleon_hier/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/config.mk @@ -9,10 +9,10 @@ export IO_DIR = ./platforms/sky130io export VERILOG_FILES_BLACKBOX = \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/ibex/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAM_4K.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/APB_sys_0/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/DMC_32x16HC.v + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/ibex/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAM_4K.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/APB_sys_0/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DMC_32x16HC.v export BLOCKS = \ DFFRAM_4K \ @@ -22,22 +22,22 @@ export BLOCKS = \ export VERILOG_FILES = \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/acc/AHB_SPM.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/AHBSRAM.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAMBB.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/GPIO.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_I2C.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_SPI.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_UART.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/i2c_master.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/PWM32.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/RAM_3Kx32.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/QSPI_XIP_CTRL.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/spi_master.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/TIMER32.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/WDT32.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/soc_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/acc/AHB_SPM.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/AHBSRAM.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAMBB.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/GPIO.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_I2C.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_SPI.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_UART.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/i2c_master.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/PWM32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/RAM_3Kx32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/QSPI_XIP_CTRL.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/spi_master.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/TIMER32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/WDT32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/soc_core.v \ $(VERILOG_FILES_BLACKBOX) export ENABLE_DPO = 0 @@ -45,7 +45,7 @@ export MACRO_PLACE_CHANNEL = 160 160 export MACRO_PLACE_HALO = 160 160 export DIE_AREA = 0.0 0.0 6800 6800 export CORE_AREA = 200 200 6600 6600 -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export MIN_ROUTING_LAYER = met1 export MAX_ROUTING_LAYER = met5 diff --git a/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk b/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk index 44a26e5ceb..5a8995057d 100644 --- a/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk @@ -1,10 +1,10 @@ export TOP_NICKNAME = chameleon_hier -export TOP_DIR = ./designs/$(PLATFORM)/${TOP_NICKNAME} +export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} export DESIGN_NAME = ibex_wrapper export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} export PLATFORM = sky130hd -export RTL_DIR = ./designs/src/${TOP_NICKNAME}/rtl +export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl export VERILOG_FILES = \ ${RTL_DIR}/ibex/ibex_core.v\ diff --git a/flow/designs/sky130hd/coyote_tc/config.mk b/flow/designs/sky130hd/coyote_tc/config.mk index 82b6d20da2..c7ff070a28 100644 --- a/flow/designs/sky130hd/coyote_tc/config.mk +++ b/flow/designs/sky130hd/coyote_tc/config.mk @@ -12,15 +12,15 @@ export SKY130_IO_VERSION ?= v0.2.0 export OPENRAMS_DIR = ./platforms/sky130ram export IO_DIR = ./platforms/sky130io -export VERILOG_FILES = ./designs/$(PLATFORM)/coyote_tc/ios.v \ - ./designs/$(PLATFORM)/coyote_tc/macros.v \ - ./designs/src/coyote_tc/coyote_tc.v \ - ./designs/src/coyote/coyote.sv2v.v \ +export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/ios.v \ + $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/macros.v \ + $(DESIGN_HOME)/src/coyote_tc/coyote_tc.v \ + $(DESIGN_HOME)/src/coyote/coyote.sv2v.v \ $(IO_DIR)/verilog/sky130_io.blackbox.v -export SDC_FILE = ./designs/$(PLATFORM)/coyote_tc/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/constraint.sdc -export FOOTPRINT_TCL = ./designs/$(PLATFORM)/coyote_tc/pad.tcl +export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pad.tcl export ADDITIONAL_LIBS = $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib \ $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib \ @@ -61,7 +61,7 @@ export DIE_AREA = 0.0 0.0 5200 4609.14 export CORE_AREA = 250 250 4950 4349.14 # Use custom power grid with core rings offset from the pads -export PDN_TCL = ./designs/$(PLATFORM)/coyote_tc/pdn.tcl +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pdn.tcl # Point to the RC file export SETRC_FILE = $(PLATFORM_DIR)/setRC.tcl diff --git a/flow/designs/sky130hd/gcd/config.mk b/flow/designs/sky130hd/gcd/config.mk index 1d7248feb4..9b725dcf0b 100644 --- a/flow/designs/sky130hd/gcd/config.mk +++ b/flow/designs/sky130hd/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = sky130hd -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # Adders degrade GCD export ADDER_MAP_FILE := diff --git a/flow/designs/sky130hd/ibex/config.mk b/flow/designs/sky130hd/ibex/config.mk index 91c302a9f6..1173a088a0 100644 --- a/flow/designs/sky130hd/ibex/config.mk +++ b/flow/designs/sky130hd/ibex/config.mk @@ -2,45 +2,45 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = sky130hd -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # Adders degrade ibex setup repair export ADDER_MAP_FILE := @@ -49,6 +49,6 @@ export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/sky130hd/jpeg/config.mk b/flow/designs/sky130hd/jpeg/config.mk index 7857e38ad7..dced6f2bca 100644 --- a/flow/designs/sky130hd/jpeg/config.mk +++ b/flow/designs/sky130hd/jpeg/config.mk @@ -2,14 +2,14 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = sky130hd -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 50 export PLACE_DENSITY_LB_ADDON = 0.15 export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk index 07bdd1cf10..4fff3e0c67 100644 --- a/flow/designs/sky130hd/microwatt/config.mk +++ b/flow/designs/sky130hd/microwatt/config.mk @@ -2,18 +2,18 @@ export DESIGN_NICKNAME = microwatt export DESIGN_NAME = microwatt export PLATFORM = sky130hd -export VERILOG_FILES_BLACKBOX = ./designs/src/$(DESIGN_NICKNAME)/IPs/*.v -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v \ +export VERILOG_FILES_BLACKBOX = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/*.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v \ $(VERILOG_FILES_BLACKBOX))) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export DIE_AREA = 0 0 2920 3520 export CORE_AREA = 10 10 2910 3510 export PLACE_DENSITY ?= 0.25 -export microwatt_DIR = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME) +export microwatt_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) export ADDITIONAL_GDS = $(wildcard $(microwatt_DIR)/gds/*.gds.gz) diff --git a/flow/designs/sky130hd/riscv32i/config.mk b/flow/designs/sky130hd/riscv32i/config.mk index 78dfa704a2..523df1d1c1 100644 --- a/flow/designs/sky130hd/riscv32i/config.mk +++ b/flow/designs/sky130hd/riscv32i/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i export DESIGN_NAME = riscv export PLATFORM = sky130hd -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 diff --git a/flow/designs/sky130hd_fakestack/aes/config.mk b/flow/designs/sky130hd_fakestack/aes/config.mk index 5e7513f4d8..e4c679faf2 100644 --- a/flow/designs/sky130hd_fakestack/aes/config.mk +++ b/flow/designs/sky130hd_fakestack/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = sky130hd_fakestack -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 20 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/sky130hd_fakestack/ariane136/config.mk b/flow/designs/sky130hd_fakestack/ariane136/config.mk index 8d76ad6dd0..8ab5d099ac 100644 --- a/flow/designs/sky130hd_fakestack/ariane136/config.mk +++ b/flow/designs/sky130hd_fakestack/ariane136/config.mk @@ -5,10 +5,10 @@ export PLATFORM = sky130hd_fakestack export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE = 10000 -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram130_256x16.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram130_256x16.lib diff --git a/flow/designs/sky130hd_fakestack/gcd/config.mk b/flow/designs/sky130hd_fakestack/gcd/config.mk index 53acdea671..4ebdfbc698 100644 --- a/flow/designs/sky130hd_fakestack/gcd/config.mk +++ b/flow/designs/sky130hd_fakestack/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = sky130hd_fakestack -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # Adders degrade GCD export ADDER_MAP_FILE := diff --git a/flow/designs/sky130hs/aes/config.mk b/flow/designs/sky130hs/aes/config.mk index 1ae8e2c5b2..78dd2e33a6 100644 --- a/flow/designs/sky130hs/aes/config.mk +++ b/flow/designs/sky130hs/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = sky130hs -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/sky130hs/coyote_tc/config.mk b/flow/designs/sky130hs/coyote_tc/config.mk index 6d48cf0a33..bb141adccf 100644 --- a/flow/designs/sky130hs/coyote_tc/config.mk +++ b/flow/designs/sky130hs/coyote_tc/config.mk @@ -10,17 +10,17 @@ export SKY130_IO_VERSION ?= v0.2.0 export OPENRAMS_DIR = ./platforms/sky130ram export IO_DIR = ./platforms/sky130io -export VERILOG_FILES = ./designs/src/coyote_tc/coyote_tc.v \ - ./designs/src/coyote/coyote.sv2v.v \ - ./designs/$(PLATFORM)/coyote_tc/ios.v \ - ./designs/$(PLATFORM)/coyote_tc/macros.v \ +export VERILOG_FILES = $(DESIGN_HOME)/src/coyote_tc/coyote_tc.v \ + $(DESIGN_HOME)/src/coyote/coyote.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/ios.v \ + $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/macros.v \ $(IO_DIR)/verilog/sky130_io.blackbox.v -export SDC_FILE = ./designs/$(PLATFORM)/coyote_tc/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/constraint.sdc export FOOTPRINT_LIBRARY = $(IO_DIR)/library.sky130_fd_io.tcl -export FOOTPRINT = ./designs/$(PLATFORM)/coyote_tc/coyote_tc.package.strategy -export SIG_MAP_FILE = ./designs/$(PLATFORM)/coyote_tc/coyote_tc.sigmap +export FOOTPRINT = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/coyote_tc.package.strategy +export SIG_MAP_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/coyote_tc.sigmap export ADDITIONAL_LIBS = $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib \ $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib \ @@ -64,10 +64,10 @@ export CORE_AREA = 210 210 4990 4389.14 export ABC_DRIVER_CELL = sky130_fd_sc_hs__buf_1 export ABC_LOAD_IN_FF = 3 -export POST_SYNTHESYS_RENAMING = ./designs/$(PLATFORM)/coyote_tc/post_synthesis_rename.tcl +export POST_SYNTHESYS_RENAMING = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/post_synthesis_rename.tcl # Use custom power grid with core rings offset from the pads -export PDN_CFG = ./designs/$(PLATFORM)/coyote_tc/pdn.cfg +export PDN_CFG = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pdn.cfg # Point to the RC file export SETRC_FILE = $(PLATFORM_DIR)/setRC.tcl diff --git a/flow/designs/sky130hs/gcd/config.mk b/flow/designs/sky130hs/gcd/config.mk index b37de24845..8e0a87133b 100644 --- a/flow/designs/sky130hs/gcd/config.mk +++ b/flow/designs/sky130hs/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = sky130hs -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 # Adders degrade GCD diff --git a/flow/designs/sky130hs/ibex/config.mk b/flow/designs/sky130hs/ibex/config.mk index b03d4a1f06..3235138721 100644 --- a/flow/designs/sky130hs/ibex/config.mk +++ b/flow/designs/sky130hs/ibex/config.mk @@ -2,44 +2,44 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = sky130hs -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 diff --git a/flow/designs/sky130hs/jpeg/config.mk b/flow/designs/sky130hs/jpeg/config.mk index 8df8c90626..6e7b62953e 100644 --- a/flow/designs/sky130hs/jpeg/config.mk +++ b/flow/designs/sky130hs/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = sky130hs -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 50 diff --git a/flow/designs/sky130hs/riscv32i/config.mk b/flow/designs/sky130hs/riscv32i/config.mk index 467d36af0d..1cf6ab1cf9 100644 --- a/flow/designs/sky130hs/riscv32i/config.mk +++ b/flow/designs/sky130hs/riscv32i/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i export DESIGN_NAME = riscv export PLATFORM = sky130hs -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 @@ -11,6 +11,6 @@ export PLACE_DENSITY_LB_ADDON = 0.2 export PLACE_PINS_ARGS=-min_distance 6 -min_distance_in_tracks export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/tsmc65lp/aes/config.mk b/flow/designs/tsmc65lp/aes/config.mk index 2c75469042..d8ed07c577 100644 --- a/flow/designs/tsmc65lp/aes/config.mk +++ b/flow/designs/tsmc65lp/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = tsmc65lp -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/tsmc65lp/ariane/config.mk b/flow/designs/tsmc65lp/ariane/config.mk index 3e7c20984e..2d97789c52 100644 --- a/flow/designs/tsmc65lp/ariane/config.mk +++ b/flow/designs/tsmc65lp/ariane/config.mk @@ -3,10 +3,10 @@ export PLATFORM = tsmc65lp export SYNTH_HIERARCHICAL = 1 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg8_w64_byte.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg8_w64_byte_ss_1p08v_1p08v_125c.lib diff --git a/flow/designs/tsmc65lp/black_parrot/config.mk b/flow/designs/tsmc65lp/black_parrot/config.mk index 1f55e1f239..62c0998b62 100644 --- a/flow/designs/tsmc65lp/black_parrot/config.mk +++ b/flow/designs/tsmc65lp/black_parrot/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ diff --git a/flow/designs/tsmc65lp/bp_be_top/config.mk b/flow/designs/tsmc65lp/bp_be_top/config.mk index d3f4916616..937ffce750 100644 --- a/flow/designs/tsmc65lp/bp_be_top/config.mk +++ b/flow/designs/tsmc65lp/bp_be_top/config.mk @@ -4,9 +4,9 @@ export PLATFORM = tsmc65lp export SYNTH_HIERARCHICAL = 1 # -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w96_bit.lef \ diff --git a/flow/designs/tsmc65lp/bp_fe_top/config.mk b/flow/designs/tsmc65lp/bp_fe_top/config.mk index 0a62e5d519..5b5161a467 100644 --- a/flow/designs/tsmc65lp/bp_fe_top/config.mk +++ b/flow/designs/tsmc65lp/bp_fe_top/config.mk @@ -4,9 +4,9 @@ export PLATFORM = tsmc65lp export SYNTH_HIERARCHICAL = 1 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w96_bit.lef \ diff --git a/flow/designs/tsmc65lp/bp_multi_top/config.mk b/flow/designs/tsmc65lp/bp_multi_top/config.mk index 475fded14c..9e4d4aebad 100644 --- a/flow/designs/tsmc65lp/bp_multi_top/config.mk +++ b/flow/designs/tsmc65lp/bp_multi_top/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ diff --git a/flow/designs/tsmc65lp/coyote/config.mk b/flow/designs/tsmc65lp/coyote/config.mk index 4f4b3379da..2d52982f86 100644 --- a/flow/designs/tsmc65lp/coyote/config.mk +++ b/flow/designs/tsmc65lp/coyote/config.mk @@ -11,10 +11,10 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 10 export RTLMP_MIN_MACRO = 5 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -#export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_hier.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +#export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_hier.sdc export ABC_AREA = 1 export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w80_bit.lef \ diff --git a/flow/designs/tsmc65lp/dynamic_node/config.mk b/flow/designs/tsmc65lp/dynamic_node/config.mk index cc715798a2..973945e928 100644 --- a/flow/designs/tsmc65lp/dynamic_node/config.mk +++ b/flow/designs/tsmc65lp/dynamic_node/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = dynamic_node export DESIGN_NAME = dynamic_node_top_wrap export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # These values must be multiples of placement site export DIE_AREA = 0 0 500 501.6 diff --git a/flow/designs/tsmc65lp/gcd/config.mk b/flow/designs/tsmc65lp/gcd/config.mk index edebb09326..aad84150d4 100644 --- a/flow/designs/tsmc65lp/gcd/config.mk +++ b/flow/designs/tsmc65lp/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ABC_AREA = 1 # These values must be multiples of placement site diff --git a/flow/designs/tsmc65lp/ibex/config.mk b/flow/designs/tsmc65lp/ibex/config.mk index 5711d86239..16405a538a 100644 --- a/flow/designs/tsmc65lp/ibex/config.mk +++ b/flow/designs/tsmc65lp/ibex/config.mk @@ -2,47 +2,47 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/tsmc65lp/jpeg/config.mk b/flow/designs/tsmc65lp/jpeg/config.mk index 1aebb9fff4..65077f3e2f 100644 --- a/flow/designs/tsmc65lp/jpeg/config.mk +++ b/flow/designs/tsmc65lp/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = tsmc65lp -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/tsmc65lp/swerv/config.mk b/flow/designs/tsmc65lp/swerv/config.mk index 7b5b8267be..52cd636c16 100644 --- a/flow/designs/tsmc65lp/swerv/config.mk +++ b/flow/designs/tsmc65lp/swerv/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = swerv export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc # These values must be multiples of placement site export DIE_AREA = 0 0 1550 1341.6 diff --git a/flow/designs/tsmc65lp/swerv_wrapper/config.mk b/flow/designs/tsmc65lp/swerv_wrapper/config.mk index 5482d732fb..0b2ea6472b 100644 --- a/flow/designs/tsmc65lp/swerv_wrapper/config.mk +++ b/flow/designs/tsmc65lp/swerv_wrapper/config.mk @@ -9,9 +9,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg11_w40_all.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w22_all.lef \ diff --git a/flow/designs/tsmc65lp/tinyRocket/config.mk b/flow/designs/tsmc65lp/tinyRocket/config.mk index b42f5bc1b6..9d43e434da 100644 --- a/flow/designs/tsmc65lp/tinyRocket/config.mk +++ b/flow/designs/tsmc65lp/tinyRocket/config.mk @@ -5,14 +5,14 @@ export PLATFORM = tsmc65lp export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE ?= 5000 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ - ./designs/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ - ./designs/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w32_byte.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w32_all.lef \ diff --git a/flow/designs/tsmc65lp/vanilla5/config.mk b/flow/designs/tsmc65lp/vanilla5/config.mk index be37f0b139..80122d2091 100644 --- a/flow/designs/tsmc65lp/vanilla5/config.mk +++ b/flow/designs/tsmc65lp/vanilla5/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = vanilla5 export DESIGN_NAME = bsg_manycore_tile export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/bsg_manycore_tile.sv2v.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/bsg_manycore_tile.sv2v.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg10_w32_all.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_2rf_lg5_w32_all.lef \