From 5c3e7fc822720db03155f8c16af740e60cfcee18 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Sat, 12 Oct 2024 16:32:21 +0000 Subject: [PATCH 1/7] initial scaffold for tunable variables Signed-off-by: Jack Luar --- docs/user/FlowVariables.md | 42 +++-- flow/scripts/generate-variables-docs.py | 152 ++++++++++--------- flow/scripts/tunable.py | 15 ++ flow/scripts/variables.yaml | 117 +++++++++++++- flow/util/utils.mk | 5 + tools/AutoTuner/src/autotuner/distributed.py | 43 +----- 6 files changed, 257 insertions(+), 117 deletions(-) create mode 100644 flow/scripts/tunable.py diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index a042ccc3d2..4265ae003e 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -100,6 +100,7 @@ configuration file. | GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| | | GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| | | HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix.| | +| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | | IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| | | IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| | | IR_DROP_LAYER| Default metal layer to report IR drop.| | @@ -123,6 +124,7 @@ configuration file. | PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | | PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| | | PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | +| PLACE_PINS_ARGS| Arguments to place_pins| | | PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | | PLATFORM| Specifies process design kit or technology node to be used.| | | POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | @@ -131,6 +133,7 @@ configuration file. | PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | | RCX_RULES| RC Extraction rules file path.| | | RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0 | +| REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist.| | | REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | | REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | | RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| | @@ -139,6 +142,7 @@ configuration file. | RTLMP_FLOW| 1 to enable the Hierarchical RTLMP flow, default empty.| | | SC_LEF| Path to technology standard cell LEF file.| | | SDC_FILE| The path to design constraint (SDC) file.| | +| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | SEAL_GDS| Seal macro to place around the design.| | | SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations.| | | SET_RC_TCL| Metal & Via RC definition file path.| | @@ -160,7 +164,8 @@ configuration file. | VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | | VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | | VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | -## synth variables + +## Synth variables - [ABC_AREA](#ABC_AREA) - [ABC_CLOCK_PERIOD_IN_PS](#ABC_CLOCK_PERIOD_IN_PS) @@ -174,6 +179,8 @@ configuration file. - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS) - [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER) - [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER) +- [SDC_FILE](#SDC_FILE) +- [SDC_GUT](#SDC_GUT) - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) @@ -181,7 +188,7 @@ configuration file. - [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS) - [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS) -## floorplan variables +## Floorplan variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) @@ -191,6 +198,7 @@ configuration file. - [CORE_UTILIZATION](#CORE_UTILIZATION) - [DIE_AREA](#DIE_AREA) - [FLOORPLAN_DEF](#FLOORPLAN_DEF) +- [IO_CONSTRAINTS](#IO_CONSTRAINTS) - [IO_PLACER_H](#IO_PLACER_H) - [IO_PLACER_V](#IO_PLACER_V) - [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO) @@ -204,28 +212,34 @@ configuration file. - [MAKE_TRACKS](#MAKE_TRACKS) - [PDN_TCL](#PDN_TCL) - [PLACE_DENSITY](#PLACE_DENSITY) +- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [PLACE_SITE](#PLACE_SITE) +- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS) - [RTLMP_FLOW](#RTLMP_FLOW) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TAPCELL_TCL](#TAPCELL_TCL) - [TNS_END_PERCENT](#TNS_END_PERCENT) -## place variables +## Place variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) - [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN) - [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN) +- [IO_CONSTRAINTS](#IO_CONSTRAINTS) - [IO_PLACER_H](#IO_PLACER_H) - [IO_PLACER_V](#IO_PLACER_V) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [PLACE_DENSITY](#PLACE_DENSITY) +- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) -## cts variables +## Cts variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) @@ -239,9 +253,10 @@ configuration file. - [POST_CTS_TCL](#POST_CTS_TCL) - [REMOVE_CELLS_FOR_EQY](#REMOVE_CELLS_FOR_EQY) - [SKIP_CTS_REPAIR_TIMING](#SKIP_CTS_REPAIR_TIMING) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TNS_END_PERCENT](#TNS_END_PERCENT) -## grt variables +## Grt variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) @@ -249,21 +264,29 @@ configuration file. - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TNS_END_PERCENT](#TNS_END_PERCENT) -## route variables +## Route variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [DETAILED_ROUTE_ARGS](#DETAILED_ROUTE_ARGS) - [DETAILED_ROUTE_END_ITERATION](#DETAILED_ROUTE_END_ITERATION) +- [FILL_CELLS](#FILL_CELLS) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) -## final variables +## Final variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) +- [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) +- [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) +- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) +- [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) ## All stages variables @@ -286,12 +309,10 @@ configuration file. - [DPO_MAX_DISPLACEMENT](#DPO_MAX_DISPLACEMENT) - [ENABLE_DPO](#ENABLE_DPO) - [FASTROUTE_TCL](#FASTROUTE_TCL) -- [FILL_CELLS](#FILL_CELLS) - [FILL_CONFIG](#FILL_CONFIG) - [GDS_FILES](#GDS_FILES) - [GENERATE_ARTIFACTS_ON_FAILURE](#GENERATE_ARTIFACTS_ON_FAILURE) - [GLOBAL_PLACEMENT_ARGS](#GLOBAL_PLACEMENT_ARGS) -- [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) - [GUI_TIMING](#GUI_TIMING) - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [IR_DROP_LAYER](#IR_DROP_LAYER) @@ -302,19 +323,16 @@ configuration file. - [PLATFORM](#PLATFORM) - [PRESERVE_CELLS](#PRESERVE_CELLS) - [PROCESS](#PROCESS) -- [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) - [RCX_RULES](#RCX_RULES) - [RECOVER_POWER](#RECOVER_POWER) - [REPAIR_PDN_VIA_LAYER](#REPAIR_PDN_VIA_LAYER) - [SC_LEF](#SC_LEF) -- [SDC_FILE](#SDC_FILE) - [SEAL_GDS](#SEAL_GDS) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SET_RC_TCL](#SET_RC_TCL) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) - [SKIP_INCREMENTAL_REPAIR](#SKIP_INCREMENTAL_REPAIR) - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) -- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [SLEW_MARGIN](#SLEW_MARGIN) - [SYNTH_ARGS](#SYNTH_ARGS) - [TAP_CELL_NAME](#TAP_CELL_NAME) diff --git a/flow/scripts/generate-variables-docs.py b/flow/scripts/generate-variables-docs.py index c1940b326f..8481e12daf 100755 --- a/flow/scripts/generate-variables-docs.py +++ b/flow/scripts/generate-variables-docs.py @@ -1,83 +1,97 @@ #!/usr/bin/env python3 -# variables.yaml is the single source of truth w.r.t. metainformation about -# the ORFS variables. -# -# This script injects an autogenerated section in FlowVariables.md with -# information about the variables from variables.yaml. +""" +This script injects an autogenerated section in FlowVariables.md with +information about the variables from variables.yaml. + +variables.yaml is the single source of truth w.r.t. metainformation about +the ORFS variables. +""" import os import yaml dir_path = os.path.dirname(os.path.realpath(__file__)) - yaml_path = os.path.join(dir_path, "variables.yaml") +preferred_order = ["synth", "floorplan", "place", "cts", "grt", "route", "final"] +table_header = "| Variable | Description | Default |\n| --- | --- | --- |\n" -with open(yaml_path, "r") as file: - data = yaml.safe_load(file) -preferred_order = ["synth", "floorplan", "place", "cts", "grt", "route", "final"] -stages = {stage for value in data.values() for stage in value.get("stages", [])} -# convert set of stages to stages in a list in the preferred order, but -# list all stages -stages = [stage for stage in preferred_order if stage in stages] + [ - stage for stage in stages if stage not in preferred_order -] +def load_yaml(yaml_path: str) -> dict: + if not os.path.exists(yaml_path): + raise FileNotFoundError(f"File {yaml_path} not found") + with open(yaml_path, "r") as file: + return yaml.safe_load(file) -markdown_table = "" -markdown_table += "## Variables in alphabetic order\n\n" -table_header = "| Variable | Description | Default |\n| --- | --- | --- |\n" -table_rows = "" -for key in sorted(data): - value = data[key] - description = value.get("description", "").replace("\n", " ").strip() - table_rows += ( +def preprocess(data: dict) -> list: + # convert set of stages to stages in a list in the preferred order, but + # list all stages + stages = {stage for value in data.values() for stage in value.get("stages", [])} + stages = [stage for stage in preferred_order if stage in stages] + [ + stage for stage in stages if stage not in preferred_order + ] + return stages + + +def generate_md(data: dict, stages: list) -> None: + # Populate overview section + markdown_table = "## Variables in alphabetic order\n\n" + table_rows = "\n".join( f'| {key}' - + f"| {description}" - + f'| {value.get("default", "")} |\n' + + f"| {value.get('description', '').replace('\n', ' ').strip()}" + + f'| {value.get("default", "")} |' + for key, value in sorted(data.items()) ) + markdown_table += table_header + table_rows + "\n\n" -markdown_table += table_header + table_rows - -for stage in stages + ["All stages", "Uncategorized"]: - markdown_table += f"## {stage} variables\n\n" - stage_keys = [ - key - for key in sorted(data) - if ( - ("stages" in data[key] and stage in data[key]["stages"]) - or ("stages" not in data[key] and stage == "Uncategorized") - or ( - stage == "All stages" - and set(data[key].get("stages", [])) == set(stages) + # Populate stages section + for stage in stages + ["All stages", "Uncategorized"]: + markdown_table += f"## {stage.capitalize()} variables\n\n" + stage_keys = [ + key + for key in sorted(data) + if ( + ("stages" in data[key] and stage in data[key]["stages"]) + or ("stages" not in data[key] and stage == "Uncategorized") + or ( + stage == "All stages" + and set(data[key].get("stages", [])) == set(stages) + ) ) - ) - ] - markdown_table += "\n".join(map(lambda k: f"- [{k}](#{k})", stage_keys)) - markdown_table += "\n\n" - -docs = os.path.join(dir_path, "..", "..", "docs", "user", "FlowVariables.md") -with open(docs, "r") as file: - lines = file.readlines() - -# Find the section to replace -start_marker = "# Automatically generated" -end_marker = "# " -start_index = None -end_index = len(lines) - -for i, line in enumerate(lines): - if line.startswith(start_marker): - start_index = i + 1 - elif start_index is not None and line.startswith(end_marker): - end_index = i - break - -if start_index is None: - raise ValueError("Start marker not found") - -# Replace the section with the new table -new_lines = lines[:start_index] + [markdown_table] + lines[end_index:] - -# Write the updated content back to FlowVariables.md -with open(docs, "w") as file: - file.writelines(new_lines) + ] + markdown_table += "\n".join(map(lambda k: f"- [{k}](#{k})", stage_keys)) + markdown_table += "\n\n" + + # Read the existing content of FlowVariables.md + docs = os.path.join(dir_path, "..", "..", "docs", "user", "FlowVariables.md") + with open(docs, "r") as file: + lines = file.readlines() + + # Find the section to replace + start_marker = "# Automatically generated" + end_marker = "# " + start_index = None + end_index = len(lines) + + for i, line in enumerate(lines): + if line.startswith(start_marker): + start_index = i + 1 + elif start_index is not None and line.startswith(end_marker): + end_index = i + break + + if start_index is None: + raise ValueError("Start marker not found") + + # Replace the section with the new table + new_lines = lines[:start_index] + [markdown_table] + lines[end_index:] + + # Write the updated content back to FlowVariables.md + with open(docs, "w") as file: + file.writelines(new_lines) + + +if __name__ == "__main__": + data = load_yaml(yaml_path) + stages = preprocess(data) + generate_md(data, stages) + print("FlowVariables.md updated successfully") diff --git a/flow/scripts/tunable.py b/flow/scripts/tunable.py new file mode 100644 index 0000000000..6602df17d1 --- /dev/null +++ b/flow/scripts/tunable.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 + +import os +import yaml + +dir_path = os.path.dirname(os.path.realpath(__file__)) + +yaml_path = os.path.join(dir_path, "variables.yaml") +with open(yaml_path, "r") as file: + data = yaml.safe_load(file) + +for key, value in data.items(): + if value.get("tunable", False) is False: + continue + print(f"{key}") diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 690c68594a..b8327460e9 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -25,7 +25,7 @@ GENERATE_ARTIFACTS_ON_FAILURE: use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server. default: 0 - + tunable: false TNS_END_PERCENT: description: > Default TNS_END_PERCENT value for post CTS timing repair. @@ -34,12 +34,14 @@ TNS_END_PERCENT: Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed. default: 100 + tunable: false stages: - cts - floorplan - grt ROUTING_LAYER_ADJUSTMENT: default: 0.5 + tunable: false description: Default routing layer adjustment stages: - place @@ -50,17 +52,20 @@ RECOVER_POWER: description: > Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100]. default: 0 + tunable: false SKIP_INCREMENTAL_REPAIR: default: 0 description: > Skip incremental repair in global route. stages: - grt + tunable: false DETAILED_METRICS: description: > If set, then calls report_metrics prior to repair operations in the CTS and global route stages default: 0 + tunable: false stages: - cts - grt @@ -68,6 +73,7 @@ EQUIVALENCE_CHECK: description: > Enable running equivalence checks to verify logical correctness of repair_timing. default: 0 + tunable: false stages: - cts CORE_UTILIZATION: @@ -75,12 +81,14 @@ CORE_UTILIZATION: The core utilization percentage (0-100). stages: - floorplan + tunable: false CORE_AREA: description: > The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). stages: - floorplan + tunable: false SKIP_REPORT_METRICS: description: > If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds. @@ -91,29 +99,37 @@ SKIP_REPORT_METRICS: - grt - route - final + tunable: false PROCESS: description: > Technology node or process in use. + tunable: false CORNER: description: > Library to select based on corner BC/TC/WC. + tunable: false TECH_LEF: description: > A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements. + tunable: false SC_LEF: description: > Path to technology standard cell LEF file. + tunable: false GDS_FILES: description: > Path to platform GDS files. + tunable: false LIB_FILES: description: > A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell. + tunable: false DONT_USE_CELLS: description: > Dont use cells eases pin access in detailed routing. + tunable: false SYNTH_GUT: description: > Load design and remove all internal logic before doing synthesis. This @@ -122,162 +138,193 @@ SYNTH_GUT: SRAMs, for instance. stages: - synth + tunable: false SYNTH_HIERARCHICAL: description: > Enable to Synthesis hierarchically, otherwise considered flat synthesis. stages: - synth + tunable: false LATCH_MAP_FILE: description: > List of latches treated as a black box by Yosys. stages: - synth + tunable: false CLKGATE_MAP_FILE: description: > List of cells for gating clock treated as a black box by Yosys. stages: - synth + tunable: false ADDER_MAP_FILE: description: > List of adders treated as a black box by Yosys. stages: - synth + tunable: false TIEHI_CELL_AND_PORT: description: > Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist. stages: - synth - place + tunable: false TIELO_CELL_AND_PORT: description: > Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. stages: - synth - place + tunable: false MIN_BUF_CELL_AND_PORTS: description: > Used to insert a buffer cell to pass through wires. Used in synthesis. stages: - synth + tunable: false ABC_CLOCK_PERIOD_IN_PS: description: > Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`. stages: - synth + tunable: false ABC_DRIVER_CELL: description: > Default driver cell used during ABC synthesis. stages: - synth + tunable: false ABC_LOAD_IN_FF: description: > During synthesis set_load value used. stages: - synth + tunable: false MAX_UNGROUP_SIZE: description: > For hierarchical synthesis, we ungroup modules of size given by this variable. stages: - synth + tunable: false FLOORPLAN_DEF: description: > Use the DEF file to initialize floorplan. stages: - floorplan + tunable: false REMOVE_ABC_BUFFERS: description: > Remove abc buffers from the netlist. stages: - floorplan + tunable: false PLACE_SITE: description: > Placement site for core cells defined in the technology LEF file. stages: - floorplan + tunable: false TAPCELL_TCL: description: > Path to Endcap and Welltie cells file. stages: - floorplan + tunable: false RTLMP_FLOW: description: > 1 to enable the Hierarchical RTLMP flow, default empty. stages: - floorplan + tunable: false MACRO_PLACEMENT: description: > Specifies the path of a file on how to place certain macros manually using read_macro_placement. stages: - floorplan + tunable: false MACRO_PLACEMENT_TCL: description: > Specifies the path of a TCL file on how to place certain macros manually. stages: - floorplan + tunable: false MACRO_PLACE_HALO: description: > Horizontal/vertical halo around macros (microns). Used by automatic macro placement. stages: - floorplan + tunable: false MACRO_PLACE_CHANNEL: description: > Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. stages: - floorplan + tunable: false MACRO_BLOCKAGE_HALO: description: > Blockage width overridden from default calculation. stages: - floorplan + tunable: false PDN_TCL: description: > File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. stages: - floorplan + tunable: false MAKE_TRACKS: description: > Tcl file that defines add routing tracks to a floorplan. stages: - floorplan + tunable: false IO_CONSTRAINTS: description: > File path to the IO constraints .tcl file. stages: - floorplan - place + tunable: false IO_PLACER_H: description: > The metal layer on which to place the I/O pins horizontally (top and bottom of the die). stages: - floorplan - place + tunable: false IO_PLACER_V: description: > The metal layer on which to place the I/O pins vertically (sides of the die). stages: - floorplan - place + tunable: false GUI_TIMING: description: > Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc. default: 1 + tunable: false FILL_CELLS: description: > Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped. stages: - route + tunable: false TAP_CELL_NAME: description: > Name of the cell to use in tap cell insertion. + tunable: false CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: description: > Cell padding on both sides in site widths to ease routability during global placement. stages: - place - floorplan + tunable: true CELL_PAD_IN_SITES_DETAIL_PLACEMENT: description: > Cell padding on both sides in site widths to ease routability in detail placement. @@ -285,12 +332,14 @@ CELL_PAD_IN_SITES_DETAIL_PLACEMENT: - place - cts - grt + tunable: true PLACE_PINS_ARGS: description: > Arguments to place_pins stages: - place - floorplan + tunable: false PLACE_DENSITY: description: > The desired placement density of cells. It reflects how spread the cells would be on the core area. @@ -298,66 +347,83 @@ PLACE_DENSITY: stages: - floorplan - place + tunable: false PLACE_DENSITY_LB_ADDON: description: > Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. + tunable: true REPAIR_PDN_VIA_LAYER: description: > Remove power grid vias which generate DRC violations after detailed routing. + tunable: false GLOBAL_PLACEMENT_ARGS: description: > Use additional tuning parameters during global placement other than default args defined in global_place.tcl. + tunable: false ENABLE_DPO: description: > Enable detail placement with improve_placement feature. + tunable: false DPO_MAX_DISPLACEMENT: description: > Specifies how far an instance can be moved when optimizing. + tunable: false GPL_TIMING_DRIVEN: description: > Specifies whether the placer should use timing driven placement. stages: - place + tunable: false GPL_ROUTABILITY_DRIVEN: description: > Specifies whether the placer should use routability driven placement. stages: - place + tunable: false CAP_MARGIN: description: > Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix. + tunable: false SLEW_MARGIN: description: > Specifies a slew margin when fixing max slew violations. This option allows you to overfix. + tunable: false CTS_ARGS: description: > Override `clock_tree_synthesis` arguments. stages: - cts + tunable: false HOLD_SLACK_MARGIN: description: > Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix. + tunable: false SETUP_SLACK_MARGIN: description: > Specifies a time margin for the slack when fixing setup violations. + tunable: false SKIP_GATE_CLONING: description: > Do not use gate cloning transform to fix timing violations (default: use gate cloning). + tunable: false SKIP_PIN_SWAP: description: > Do not use pin swapping as a transform to fix timing violations (default: use pin swapping). + tunable: false REMOVE_CELLS_FOR_EQY: description: > String patterns directly passed to write_verilog -remove_cells <> for equivalence checks. stages: - cts + tunable: false SKIP_CTS_REPAIR_TIMING: description: > Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running. stages: - cts + tunable: false MIN_ROUTING_LAYER: description: > The lowest metal layer name to be used in routing. @@ -366,6 +432,7 @@ MIN_ROUTING_LAYER: - grt - route - final + tunable: false MAX_ROUTING_LAYER: description: > The highest metal layer name to be used in routing. @@ -374,42 +441,53 @@ MAX_ROUTING_LAYER: - grt - route - final + tunable: false DETAILED_ROUTE_ARGS: description: > Add additional arguments for debugging purposes during detail route. stages: - route + tunable: false MACRO_EXTENSION: description: > Sets the number of GCells added to the blockages boundaries from macros. + tunable: false DETAILED_ROUTE_END_ITERATION: description: > Maximum number of iterations, default 64. stages: - route + tunable: false RCX_RULES: description: > RC Extraction rules file path. + tunable: false SET_RC_TCL: description: > Metal & Via RC definition file path. + tunable: false FILL_CONFIG: description: > JSON rule file for metal fill during chip finishing. + tunable: false KLAYOUT_TECH_FILE: description: > A mapping from LEF/DEF to GDS using the KLayout tool. + tunable: false IR_DROP_LAYER: description: > Default metal layer to report IR drop. + tunable: false PLATFORM: required: true description: > Specifies process design kit or technology node to be used. + tunable: false DESIGN_NAME: required: true description: > The name of the top-level module of the design. + tunable: false VERILOG_FILES: required: true description: > @@ -417,12 +495,14 @@ VERILOG_FILES: of modules (check `yosys -h write_json` for more details). stages: - synth + tunable: false SDC_FILE: required: true description: > The path to design constraint (SDC) file. stages: - synth + tunable: false SDC_GUT: description: > Load design and remove all internal logic before doing synthesis. This @@ -431,6 +511,7 @@ SDC_GUT: SRAMs, for instance. stages: - synth + tunable: false ADDITIONAL_FILES: description: > Additional files to be added to `make issue` archive. @@ -442,67 +523,84 @@ ADDITIONAL_FILES: - grt - route - final + tunable: false ADDITIONAL_LEFS: description: > Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file. + tunable: false ADDITIONAL_LIBS: description: > Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file. + tunable: false ADDITIONAL_GDS: description: > Hardened macro GDS files listed here. + tunable: false VERILOG_INCLUDE_DIRS: description: > Specifies the include directories for the Verilog input files. stages: - synth + tunable: false CORNER: description: > PVT corner library selection. Only available for ASAP7 and GF180 PDK. + tunable: false DESIGN_NICKNAME: description: > DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design. + tunable: false ABC_AREA: description: > Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED. stages: - synth + tunable: false PWR_NETS_VOLTAGES: description: > Used for IR Drop calculation. stages: - final + tunable: false GND_NETS_VOLTAGES: description: > Used for IR Drop calculation. stages: - final + tunable: false BLOCKS: description: > Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile. + tunable: false CDL_FILES: description: > Insert additional Circuit Description Language (`.cdl`) netlist files. + tunable: false DFF_LIB_FILES: description: > Technology mapping liberty files for flip-flops. + tunable: false DONT_USE_LIBS: description: > Set liberty files as `dont_use`. + tunable: false PRESERVE_CELLS: description: > Mark modules to keep from getting removed in flattening. + tunable: false SYNTH_ARGS: description: > Optional synthesis variables for yosys. + tunable: false VERILOG_TOP_PARAMS: description: > Apply toplevel params (if exist). + tunable: false stages: - synth CORE_ASPECT_RATIO: @@ -511,6 +609,7 @@ CORE_ASPECT_RATIO: is undefined. stages: - floorplan + tunable: false CORE_MARGIN: description: > The margin between the core area and die area, in multiples of SITE heights. @@ -518,73 +617,89 @@ CORE_MARGIN: is undefined. stages: - floorplan + tunable: true DIE_AREA: description: > The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). stages: - floorplan + tunable: false RESYNTH_AREA_RECOVER: description: > Enable re-synthesis for area reclaim. stages: - synth + tunable: false RESYNTH_TIMING_RECOVER: description: > Enable re-synthesis for timing optimization. stages: - synth + tunable: false MACRO_HALO_X: description: > Set macro halo for x-direction. Only available for ASAP7 PDK. stages: - floorplan + tunable: false MACRO_HALO_Y: description: > Set macro halo for y-direction. Only available for ASAP7 PDK. stages: - floorplan + tunable: false MACRO_WRAPPERS: description: > The wrapper file that replaces existing macros with their wrapped version. stages: - floorplan + tunable: false CTS_BUF_DISTANCE: description: > Distance (in microns) between buffers. stages: - cts + tunable: false CTS_CLUSTER_DIAMETER: description: > Maximum diameter (in microns) of sink cluster. Default 20. stages: - cts + tunable: true CTS_CLUSTER_SIZE: description: > Maximum number of sinks per cluster. Default 50. stages: - cts + tunable: true CTS_SNAPSHOT: description: > Creates ODB/SDC files prior to clock net and setup/hold repair. stages: - cts + tunable: false POST_CTS_TCL: description: > Specifies a Tcl script with commands to run after CTS is completed. stages: - cts + tunable: false FASTROUTE_TCL: description: > Specifies a Tcl script with commands to run before FastRoute. + tunable: false USE_FILL: description: > Whether to perform metal density filling. Default 0 (=off). + tunable: false SEAL_GDS: description: > Seal macro to place around the design. + tunable: false ABSTRACT_SOURCE: description: > Which .odb file to use to create abstract stages: - generate_abstract + tunable: false diff --git a/flow/util/utils.mk b/flow/util/utils.mk index c1f368bbd9..c353afb00b 100644 --- a/flow/util/utils.mk +++ b/flow/util/utils.mk @@ -167,3 +167,8 @@ ifeq ($(origin ABC_CLOCK_PERIOD_IN_PS), undefined) export ABC_CLOCK_PERIOD_IN_PS := $(shell sed -nE "s/^set\s+clk_period\s+(\S+).*|.*-period\s+(\S+).*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1}') endif endif + +# Get AutoTuner tunable variables +.PHONY: get_tunable_variables +get_tunable_variables: + @$(SCRIPTS_DIR)/tunable.py diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index 9af8da60a0..bfa24af130 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -360,42 +360,18 @@ def read_tune_pbt(name, this): return config, sdc_file, fr_file -def parse_flow_variables(): +def parse_tunable_variables(): """ - Parse the flow variables from source - - Code: Makefile `vars` target output - + Parse the tunable variables from variables.yaml TODO: Tests. - - Output: - - flow_variables: set of flow variables """ cur_path = os.path.dirname(os.path.realpath(__file__)) - - # first, generate vars.tcl makefile_path = os.path.join(cur_path, "../../../../flow/") initial_path = os.path.abspath(os.getcwd()) os.chdir(makefile_path) result = subprocess.run(["make", "vars", f"PLATFORM={args.platform}"]) - if result.returncode != 0: - print(f"[ERROR TUN-0018] Makefile failed with error code {result.returncode}.") - sys.exit(1) - if not os.path.exists("vars.tcl"): - print(f"[ERROR TUN-0019] Makefile did not generate vars.tcl.") - sys.exit(1) os.chdir(initial_path) - - # for code parsing, you need to parse from both scripts and vars.tcl file. - pattern = r"(?:::)?env\((.*?)\)" - files = glob.glob(os.path.join(cur_path, "../../../../flow/scripts/*.tcl")) - files.append(os.path.join(cur_path, "../../../../flow/vars.tcl")) - variables = set() - for file in files: - with open(file) as fp: - matches = re.findall(pattern, fp.read()) - for match in matches: - for variable in match.split("\n"): - variables.add(variable.strip().upper()) + variables = [var.strip() for var in result.split("\n")] return variables @@ -406,7 +382,7 @@ def parse_config(config, path=os.getcwd()): options = "" sdc = {} fast_route = {} - flow_variables = parse_flow_variables() + flow_variables = parse_tunable_variables() for key, value in config.items(): # Keys that begin with underscore need special handling. if key.startswith("_"): @@ -424,15 +400,12 @@ def parse_config(config, path=os.getcwd()): "[WARNING TUN-0013] Non-flatten the designs are not " "fully supported, ignoring _SYNTH_FLATTEN parameter." ) - # Default case is VAR=VALUE else: - # FIXME there is no robust way to get this metainformation from - # ORFS about the variables, so disable this code for now. - + # Default case is VAR=VALUE # Sanity check: ignore all flow variables that are not tunable - # if key not in flow_variables: - # print(f"[ERROR TUN-0017] Variable {key} is not tunable.") - # sys.exit(1) + if key not in flow_variables: + print(f"[ERROR TUN-0017] Variable {key} is not tunable.") + sys.exit(1) options += f" {key}={value}" if bool(sdc): write_sdc(sdc, path) From 5569b6b131d6c17bd2883c10a0514b8240a6df36 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Sun, 13 Oct 2024 09:52:55 +0000 Subject: [PATCH 2/7] revert non-at stuff, parse yaml directly in distributed.py Signed-off-by: Jack Luar --- docs/user/FlowVariables.md | 43 ++---- flow/scripts/generate-variables-docs.py | 152 +++++++++---------- flow/scripts/tunable.py | 15 -- flow/scripts/variables.yaml | 122 +-------------- flow/util/utils.mk | 5 - tools/AutoTuner/requirements.txt | 1 + tools/AutoTuner/src/autotuner/distributed.py | 23 ++- 7 files changed, 107 insertions(+), 254 deletions(-) delete mode 100644 flow/scripts/tunable.py diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 4265ae003e..a6785dbfa4 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -100,7 +100,6 @@ configuration file. | GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| | | GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| | | HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix.| | -| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | | IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| | | IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| | | IR_DROP_LAYER| Default metal layer to report IR drop.| | @@ -124,7 +123,6 @@ configuration file. | PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | | PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| | | PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | -| PLACE_PINS_ARGS| Arguments to place_pins| | | PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | | PLATFORM| Specifies process design kit or technology node to be used.| | | POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | @@ -133,7 +131,6 @@ configuration file. | PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | | RCX_RULES| RC Extraction rules file path.| | | RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0 | -| REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist.| | | REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | | REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | | RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| | @@ -142,7 +139,6 @@ configuration file. | RTLMP_FLOW| 1 to enable the Hierarchical RTLMP flow, default empty.| | | SC_LEF| Path to technology standard cell LEF file.| | | SDC_FILE| The path to design constraint (SDC) file.| | -| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | SEAL_GDS| Seal macro to place around the design.| | | SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations.| | | SET_RC_TCL| Metal & Via RC definition file path.| | @@ -164,8 +160,7 @@ configuration file. | VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | | VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | | VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | - -## Synth variables +## synth variables - [ABC_AREA](#ABC_AREA) - [ABC_CLOCK_PERIOD_IN_PS](#ABC_CLOCK_PERIOD_IN_PS) @@ -179,8 +174,6 @@ configuration file. - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS) - [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER) - [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER) -- [SDC_FILE](#SDC_FILE) -- [SDC_GUT](#SDC_GUT) - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) @@ -188,7 +181,7 @@ configuration file. - [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS) - [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS) -## Floorplan variables +## floorplan variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) @@ -198,7 +191,6 @@ configuration file. - [CORE_UTILIZATION](#CORE_UTILIZATION) - [DIE_AREA](#DIE_AREA) - [FLOORPLAN_DEF](#FLOORPLAN_DEF) -- [IO_CONSTRAINTS](#IO_CONSTRAINTS) - [IO_PLACER_H](#IO_PLACER_H) - [IO_PLACER_V](#IO_PLACER_V) - [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO) @@ -212,34 +204,28 @@ configuration file. - [MAKE_TRACKS](#MAKE_TRACKS) - [PDN_TCL](#PDN_TCL) - [PLACE_DENSITY](#PLACE_DENSITY) -- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [PLACE_SITE](#PLACE_SITE) -- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS) - [RTLMP_FLOW](#RTLMP_FLOW) -- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TAPCELL_TCL](#TAPCELL_TCL) - [TNS_END_PERCENT](#TNS_END_PERCENT) -## Place variables +## place variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) - [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN) - [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN) -- [IO_CONSTRAINTS](#IO_CONSTRAINTS) - [IO_PLACER_H](#IO_PLACER_H) - [IO_PLACER_V](#IO_PLACER_V) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [PLACE_DENSITY](#PLACE_DENSITY) -- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) -- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) -## Cts variables +## cts variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) @@ -253,10 +239,9 @@ configuration file. - [POST_CTS_TCL](#POST_CTS_TCL) - [REMOVE_CELLS_FOR_EQY](#REMOVE_CELLS_FOR_EQY) - [SKIP_CTS_REPAIR_TIMING](#SKIP_CTS_REPAIR_TIMING) -- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TNS_END_PERCENT](#TNS_END_PERCENT) -## Grt variables +## grt variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) @@ -264,29 +249,21 @@ configuration file. - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) -- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TNS_END_PERCENT](#TNS_END_PERCENT) -## Route variables +## route variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [DETAILED_ROUTE_ARGS](#DETAILED_ROUTE_ARGS) - [DETAILED_ROUTE_END_ITERATION](#DETAILED_ROUTE_END_ITERATION) -- [FILL_CELLS](#FILL_CELLS) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) -- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) -## Final variables +## final variables - [ADDITIONAL_FILES](#ADDITIONAL_FILES) -- [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) -- [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) -- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) -- [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) -- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) ## All stages variables @@ -309,10 +286,12 @@ configuration file. - [DPO_MAX_DISPLACEMENT](#DPO_MAX_DISPLACEMENT) - [ENABLE_DPO](#ENABLE_DPO) - [FASTROUTE_TCL](#FASTROUTE_TCL) +- [FILL_CELLS](#FILL_CELLS) - [FILL_CONFIG](#FILL_CONFIG) - [GDS_FILES](#GDS_FILES) - [GENERATE_ARTIFACTS_ON_FAILURE](#GENERATE_ARTIFACTS_ON_FAILURE) - [GLOBAL_PLACEMENT_ARGS](#GLOBAL_PLACEMENT_ARGS) +- [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) - [GUI_TIMING](#GUI_TIMING) - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [IR_DROP_LAYER](#IR_DROP_LAYER) @@ -323,19 +302,21 @@ configuration file. - [PLATFORM](#PLATFORM) - [PRESERVE_CELLS](#PRESERVE_CELLS) - [PROCESS](#PROCESS) +- [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) - [RCX_RULES](#RCX_RULES) - [RECOVER_POWER](#RECOVER_POWER) - [REPAIR_PDN_VIA_LAYER](#REPAIR_PDN_VIA_LAYER) - [SC_LEF](#SC_LEF) +- [SDC_FILE](#SDC_FILE) - [SEAL_GDS](#SEAL_GDS) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SET_RC_TCL](#SET_RC_TCL) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) - [SKIP_INCREMENTAL_REPAIR](#SKIP_INCREMENTAL_REPAIR) - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [SLEW_MARGIN](#SLEW_MARGIN) - [SYNTH_ARGS](#SYNTH_ARGS) - [TAP_CELL_NAME](#TAP_CELL_NAME) - [TECH_LEF](#TECH_LEF) - [USE_FILL](#USE_FILL) - diff --git a/flow/scripts/generate-variables-docs.py b/flow/scripts/generate-variables-docs.py index 8481e12daf..c1940b326f 100755 --- a/flow/scripts/generate-variables-docs.py +++ b/flow/scripts/generate-variables-docs.py @@ -1,97 +1,83 @@ #!/usr/bin/env python3 -""" -This script injects an autogenerated section in FlowVariables.md with -information about the variables from variables.yaml. - -variables.yaml is the single source of truth w.r.t. metainformation about -the ORFS variables. -""" +# variables.yaml is the single source of truth w.r.t. metainformation about +# the ORFS variables. +# +# This script injects an autogenerated section in FlowVariables.md with +# information about the variables from variables.yaml. import os import yaml dir_path = os.path.dirname(os.path.realpath(__file__)) -yaml_path = os.path.join(dir_path, "variables.yaml") -preferred_order = ["synth", "floorplan", "place", "cts", "grt", "route", "final"] -table_header = "| Variable | Description | Default |\n| --- | --- | --- |\n" - -def load_yaml(yaml_path: str) -> dict: - if not os.path.exists(yaml_path): - raise FileNotFoundError(f"File {yaml_path} not found") - with open(yaml_path, "r") as file: - return yaml.safe_load(file) +yaml_path = os.path.join(dir_path, "variables.yaml") +with open(yaml_path, "r") as file: + data = yaml.safe_load(file) -def preprocess(data: dict) -> list: - # convert set of stages to stages in a list in the preferred order, but - # list all stages - stages = {stage for value in data.values() for stage in value.get("stages", [])} - stages = [stage for stage in preferred_order if stage in stages] + [ - stage for stage in stages if stage not in preferred_order - ] - return stages +preferred_order = ["synth", "floorplan", "place", "cts", "grt", "route", "final"] +stages = {stage for value in data.values() for stage in value.get("stages", [])} +# convert set of stages to stages in a list in the preferred order, but +# list all stages +stages = [stage for stage in preferred_order if stage in stages] + [ + stage for stage in stages if stage not in preferred_order +] +markdown_table = "" -def generate_md(data: dict, stages: list) -> None: - # Populate overview section - markdown_table = "## Variables in alphabetic order\n\n" - table_rows = "\n".join( +markdown_table += "## Variables in alphabetic order\n\n" +table_header = "| Variable | Description | Default |\n| --- | --- | --- |\n" +table_rows = "" +for key in sorted(data): + value = data[key] + description = value.get("description", "").replace("\n", " ").strip() + table_rows += ( f'| {key}' - + f"| {value.get('description', '').replace('\n', ' ').strip()}" - + f'| {value.get("default", "")} |' - for key, value in sorted(data.items()) + + f"| {description}" + + f'| {value.get("default", "")} |\n' ) - markdown_table += table_header + table_rows + "\n\n" - # Populate stages section - for stage in stages + ["All stages", "Uncategorized"]: - markdown_table += f"## {stage.capitalize()} variables\n\n" - stage_keys = [ - key - for key in sorted(data) - if ( - ("stages" in data[key] and stage in data[key]["stages"]) - or ("stages" not in data[key] and stage == "Uncategorized") - or ( - stage == "All stages" - and set(data[key].get("stages", [])) == set(stages) - ) +markdown_table += table_header + table_rows + +for stage in stages + ["All stages", "Uncategorized"]: + markdown_table += f"## {stage} variables\n\n" + stage_keys = [ + key + for key in sorted(data) + if ( + ("stages" in data[key] and stage in data[key]["stages"]) + or ("stages" not in data[key] and stage == "Uncategorized") + or ( + stage == "All stages" + and set(data[key].get("stages", [])) == set(stages) ) - ] - markdown_table += "\n".join(map(lambda k: f"- [{k}](#{k})", stage_keys)) - markdown_table += "\n\n" - - # Read the existing content of FlowVariables.md - docs = os.path.join(dir_path, "..", "..", "docs", "user", "FlowVariables.md") - with open(docs, "r") as file: - lines = file.readlines() - - # Find the section to replace - start_marker = "# Automatically generated" - end_marker = "# " - start_index = None - end_index = len(lines) - - for i, line in enumerate(lines): - if line.startswith(start_marker): - start_index = i + 1 - elif start_index is not None and line.startswith(end_marker): - end_index = i - break - - if start_index is None: - raise ValueError("Start marker not found") - - # Replace the section with the new table - new_lines = lines[:start_index] + [markdown_table] + lines[end_index:] - - # Write the updated content back to FlowVariables.md - with open(docs, "w") as file: - file.writelines(new_lines) - - -if __name__ == "__main__": - data = load_yaml(yaml_path) - stages = preprocess(data) - generate_md(data, stages) - print("FlowVariables.md updated successfully") + ) + ] + markdown_table += "\n".join(map(lambda k: f"- [{k}](#{k})", stage_keys)) + markdown_table += "\n\n" + +docs = os.path.join(dir_path, "..", "..", "docs", "user", "FlowVariables.md") +with open(docs, "r") as file: + lines = file.readlines() + +# Find the section to replace +start_marker = "# Automatically generated" +end_marker = "# " +start_index = None +end_index = len(lines) + +for i, line in enumerate(lines): + if line.startswith(start_marker): + start_index = i + 1 + elif start_index is not None and line.startswith(end_marker): + end_index = i + break + +if start_index is None: + raise ValueError("Start marker not found") + +# Replace the section with the new table +new_lines = lines[:start_index] + [markdown_table] + lines[end_index:] + +# Write the updated content back to FlowVariables.md +with open(docs, "w") as file: + file.writelines(new_lines) diff --git a/flow/scripts/tunable.py b/flow/scripts/tunable.py deleted file mode 100644 index 6602df17d1..0000000000 --- a/flow/scripts/tunable.py +++ /dev/null @@ -1,15 +0,0 @@ -#!/usr/bin/env python3 - -import os -import yaml - -dir_path = os.path.dirname(os.path.realpath(__file__)) - -yaml_path = os.path.join(dir_path, "variables.yaml") -with open(yaml_path, "r") as file: - data = yaml.safe_load(file) - -for key, value in data.items(): - if value.get("tunable", False) is False: - continue - print(f"{key}") diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index b8327460e9..bfe0050600 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -25,7 +25,6 @@ GENERATE_ARTIFACTS_ON_FAILURE: use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server. default: 0 - tunable: false TNS_END_PERCENT: description: > Default TNS_END_PERCENT value for post CTS timing repair. @@ -34,14 +33,12 @@ TNS_END_PERCENT: Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed. default: 100 - tunable: false stages: - cts - floorplan - grt ROUTING_LAYER_ADJUSTMENT: default: 0.5 - tunable: false description: Default routing layer adjustment stages: - place @@ -52,7 +49,6 @@ RECOVER_POWER: description: > Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100]. default: 0 - tunable: false SKIP_INCREMENTAL_REPAIR: default: 0 description: > @@ -65,7 +61,6 @@ DETAILED_METRICS: If set, then calls report_metrics prior to repair operations in the CTS and global route stages default: 0 - tunable: false stages: - cts - grt @@ -73,7 +68,6 @@ EQUIVALENCE_CHECK: description: > Enable running equivalence checks to verify logical correctness of repair_timing. default: 0 - tunable: false stages: - cts CORE_UTILIZATION: @@ -81,14 +75,12 @@ CORE_UTILIZATION: The core utilization percentage (0-100). stages: - floorplan - tunable: false CORE_AREA: description: > The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). stages: - floorplan - tunable: false SKIP_REPORT_METRICS: description: > If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds. @@ -99,37 +91,29 @@ SKIP_REPORT_METRICS: - grt - route - final - tunable: false PROCESS: description: > Technology node or process in use. - tunable: false CORNER: description: > Library to select based on corner BC/TC/WC. - tunable: false TECH_LEF: description: > A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements. - tunable: false SC_LEF: description: > Path to technology standard cell LEF file. - tunable: false GDS_FILES: description: > Path to platform GDS files. - tunable: false LIB_FILES: description: > A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell. - tunable: false DONT_USE_CELLS: description: > Dont use cells eases pin access in detailed routing. - tunable: false SYNTH_GUT: description: > Load design and remove all internal logic before doing synthesis. This @@ -138,193 +122,164 @@ SYNTH_GUT: SRAMs, for instance. stages: - synth - tunable: false SYNTH_HIERARCHICAL: description: > Enable to Synthesis hierarchically, otherwise considered flat synthesis. stages: - synth - tunable: false LATCH_MAP_FILE: description: > List of latches treated as a black box by Yosys. stages: - synth - tunable: false CLKGATE_MAP_FILE: description: > List of cells for gating clock treated as a black box by Yosys. stages: - synth - tunable: false ADDER_MAP_FILE: description: > List of adders treated as a black box by Yosys. stages: - synth - tunable: false TIEHI_CELL_AND_PORT: description: > Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist. stages: - synth - place - tunable: false TIELO_CELL_AND_PORT: description: > Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. stages: - synth - place - tunable: false MIN_BUF_CELL_AND_PORTS: description: > Used to insert a buffer cell to pass through wires. Used in synthesis. stages: - synth - tunable: false ABC_CLOCK_PERIOD_IN_PS: description: > Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`. stages: - synth - tunable: false ABC_DRIVER_CELL: description: > Default driver cell used during ABC synthesis. stages: - synth - tunable: false ABC_LOAD_IN_FF: description: > During synthesis set_load value used. stages: - synth - tunable: false MAX_UNGROUP_SIZE: description: > For hierarchical synthesis, we ungroup modules of size given by this variable. stages: - synth - tunable: false FLOORPLAN_DEF: description: > Use the DEF file to initialize floorplan. stages: - floorplan - tunable: false REMOVE_ABC_BUFFERS: description: > Remove abc buffers from the netlist. stages: - floorplan - tunable: false PLACE_SITE: description: > Placement site for core cells defined in the technology LEF file. stages: - floorplan - tunable: false TAPCELL_TCL: description: > Path to Endcap and Welltie cells file. stages: - floorplan - tunable: false RTLMP_FLOW: description: > 1 to enable the Hierarchical RTLMP flow, default empty. stages: - floorplan - tunable: false MACRO_PLACEMENT: description: > Specifies the path of a file on how to place certain macros manually using read_macro_placement. stages: - floorplan - tunable: false MACRO_PLACEMENT_TCL: description: > Specifies the path of a TCL file on how to place certain macros manually. stages: - floorplan - tunable: false MACRO_PLACE_HALO: description: > Horizontal/vertical halo around macros (microns). Used by automatic macro placement. stages: - floorplan - tunable: false MACRO_PLACE_CHANNEL: description: > Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. stages: - floorplan - tunable: false MACRO_BLOCKAGE_HALO: description: > Blockage width overridden from default calculation. stages: - floorplan - tunable: false PDN_TCL: description: > File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. stages: - floorplan - tunable: false MAKE_TRACKS: description: > Tcl file that defines add routing tracks to a floorplan. stages: - floorplan - tunable: false IO_CONSTRAINTS: description: > File path to the IO constraints .tcl file. stages: - floorplan - place - tunable: false IO_PLACER_H: description: > The metal layer on which to place the I/O pins horizontally (top and bottom of the die). stages: - floorplan - place - tunable: false IO_PLACER_V: description: > The metal layer on which to place the I/O pins vertically (sides of the die). stages: - floorplan - place - tunable: false GUI_TIMING: description: > Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc. default: 1 - tunable: false + tunable: 1 FILL_CELLS: description: > Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped. stages: - route - tunable: false TAP_CELL_NAME: description: > Name of the cell to use in tap cell insertion. - tunable: false CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: description: > Cell padding on both sides in site widths to ease routability during global placement. stages: - place - floorplan - tunable: true + tunable: 1 CELL_PAD_IN_SITES_DETAIL_PLACEMENT: description: > Cell padding on both sides in site widths to ease routability in detail placement. @@ -332,14 +287,13 @@ CELL_PAD_IN_SITES_DETAIL_PLACEMENT: - place - cts - grt - tunable: true + tunable: 1 PLACE_PINS_ARGS: description: > Arguments to place_pins stages: - place - floorplan - tunable: false PLACE_DENSITY: description: > The desired placement density of cells. It reflects how spread the cells would be on the core area. @@ -347,83 +301,67 @@ PLACE_DENSITY: stages: - floorplan - place - tunable: false PLACE_DENSITY_LB_ADDON: description: > Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. - tunable: true + tunable: 1 REPAIR_PDN_VIA_LAYER: description: > Remove power grid vias which generate DRC violations after detailed routing. - tunable: false GLOBAL_PLACEMENT_ARGS: description: > Use additional tuning parameters during global placement other than default args defined in global_place.tcl. - tunable: false ENABLE_DPO: description: > Enable detail placement with improve_placement feature. - tunable: false DPO_MAX_DISPLACEMENT: description: > Specifies how far an instance can be moved when optimizing. - tunable: false GPL_TIMING_DRIVEN: description: > Specifies whether the placer should use timing driven placement. stages: - place - tunable: false GPL_ROUTABILITY_DRIVEN: description: > Specifies whether the placer should use routability driven placement. stages: - place - tunable: false CAP_MARGIN: description: > Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix. - tunable: false SLEW_MARGIN: description: > Specifies a slew margin when fixing max slew violations. This option allows you to overfix. - tunable: false CTS_ARGS: description: > Override `clock_tree_synthesis` arguments. stages: - cts - tunable: false HOLD_SLACK_MARGIN: description: > Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix. - tunable: false SETUP_SLACK_MARGIN: description: > Specifies a time margin for the slack when fixing setup violations. - tunable: false SKIP_GATE_CLONING: description: > Do not use gate cloning transform to fix timing violations (default: use gate cloning). - tunable: false SKIP_PIN_SWAP: description: > Do not use pin swapping as a transform to fix timing violations (default: use pin swapping). - tunable: false REMOVE_CELLS_FOR_EQY: description: > String patterns directly passed to write_verilog -remove_cells <> for equivalence checks. stages: - cts - tunable: false SKIP_CTS_REPAIR_TIMING: description: > Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running. stages: - cts - tunable: false MIN_ROUTING_LAYER: description: > The lowest metal layer name to be used in routing. @@ -432,7 +370,6 @@ MIN_ROUTING_LAYER: - grt - route - final - tunable: false MAX_ROUTING_LAYER: description: > The highest metal layer name to be used in routing. @@ -441,53 +378,42 @@ MAX_ROUTING_LAYER: - grt - route - final - tunable: false DETAILED_ROUTE_ARGS: description: > Add additional arguments for debugging purposes during detail route. stages: - route - tunable: false MACRO_EXTENSION: description: > Sets the number of GCells added to the blockages boundaries from macros. - tunable: false DETAILED_ROUTE_END_ITERATION: description: > Maximum number of iterations, default 64. stages: - route - tunable: false RCX_RULES: description: > RC Extraction rules file path. - tunable: false SET_RC_TCL: description: > Metal & Via RC definition file path. - tunable: false FILL_CONFIG: description: > JSON rule file for metal fill during chip finishing. - tunable: false KLAYOUT_TECH_FILE: description: > A mapping from LEF/DEF to GDS using the KLayout tool. - tunable: false IR_DROP_LAYER: description: > Default metal layer to report IR drop. - tunable: false PLATFORM: required: true description: > Specifies process design kit or technology node to be used. - tunable: false DESIGN_NAME: required: true description: > The name of the top-level module of the design. - tunable: false VERILOG_FILES: required: true description: > @@ -495,14 +421,12 @@ VERILOG_FILES: of modules (check `yosys -h write_json` for more details). stages: - synth - tunable: false SDC_FILE: required: true description: > The path to design constraint (SDC) file. stages: - synth - tunable: false SDC_GUT: description: > Load design and remove all internal logic before doing synthesis. This @@ -511,7 +435,6 @@ SDC_GUT: SRAMs, for instance. stages: - synth - tunable: false ADDITIONAL_FILES: description: > Additional files to be added to `make issue` archive. @@ -523,84 +446,67 @@ ADDITIONAL_FILES: - grt - route - final - tunable: false ADDITIONAL_LEFS: description: > Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file. - tunable: false ADDITIONAL_LIBS: description: > Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file. - tunable: false ADDITIONAL_GDS: description: > Hardened macro GDS files listed here. - tunable: false VERILOG_INCLUDE_DIRS: description: > Specifies the include directories for the Verilog input files. stages: - synth - tunable: false CORNER: description: > PVT corner library selection. Only available for ASAP7 and GF180 PDK. - tunable: false DESIGN_NICKNAME: description: > DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design. - tunable: false ABC_AREA: description: > Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED. stages: - synth - tunable: false PWR_NETS_VOLTAGES: description: > Used for IR Drop calculation. stages: - final - tunable: false GND_NETS_VOLTAGES: description: > Used for IR Drop calculation. stages: - final - tunable: false BLOCKS: description: > Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile. - tunable: false CDL_FILES: description: > Insert additional Circuit Description Language (`.cdl`) netlist files. - tunable: false DFF_LIB_FILES: description: > Technology mapping liberty files for flip-flops. - tunable: false DONT_USE_LIBS: description: > Set liberty files as `dont_use`. - tunable: false PRESERVE_CELLS: description: > Mark modules to keep from getting removed in flattening. - tunable: false SYNTH_ARGS: description: > Optional synthesis variables for yosys. - tunable: false VERILOG_TOP_PARAMS: description: > Apply toplevel params (if exist). - tunable: false stages: - synth CORE_ASPECT_RATIO: @@ -609,7 +515,6 @@ CORE_ASPECT_RATIO: is undefined. stages: - floorplan - tunable: false CORE_MARGIN: description: > The margin between the core area and die area, in multiples of SITE heights. @@ -617,89 +522,76 @@ CORE_MARGIN: is undefined. stages: - floorplan - tunable: true + tunable: 1 DIE_AREA: description: > The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). stages: - floorplan - tunable: false RESYNTH_AREA_RECOVER: description: > Enable re-synthesis for area reclaim. stages: - synth - tunable: false RESYNTH_TIMING_RECOVER: description: > Enable re-synthesis for timing optimization. stages: - synth - tunable: false MACRO_HALO_X: description: > Set macro halo for x-direction. Only available for ASAP7 PDK. stages: - floorplan - tunable: false MACRO_HALO_Y: description: > Set macro halo for y-direction. Only available for ASAP7 PDK. stages: - floorplan - tunable: false MACRO_WRAPPERS: description: > The wrapper file that replaces existing macros with their wrapped version. stages: - floorplan - tunable: false CTS_BUF_DISTANCE: description: > Distance (in microns) between buffers. stages: - cts - tunable: false CTS_CLUSTER_DIAMETER: description: > Maximum diameter (in microns) of sink cluster. Default 20. stages: - cts - tunable: true + tunable: 1 CTS_CLUSTER_SIZE: description: > Maximum number of sinks per cluster. Default 50. stages: - cts - tunable: true + tunable: 1 CTS_SNAPSHOT: description: > Creates ODB/SDC files prior to clock net and setup/hold repair. stages: - cts - tunable: false POST_CTS_TCL: description: > Specifies a Tcl script with commands to run after CTS is completed. stages: - cts - tunable: false FASTROUTE_TCL: description: > Specifies a Tcl script with commands to run before FastRoute. - tunable: false USE_FILL: description: > Whether to perform metal density filling. Default 0 (=off). - tunable: false SEAL_GDS: description: > Seal macro to place around the design. - tunable: false ABSTRACT_SOURCE: description: > Which .odb file to use to create abstract stages: - generate_abstract - tunable: false diff --git a/flow/util/utils.mk b/flow/util/utils.mk index c353afb00b..c1f368bbd9 100644 --- a/flow/util/utils.mk +++ b/flow/util/utils.mk @@ -167,8 +167,3 @@ ifeq ($(origin ABC_CLOCK_PERIOD_IN_PS), undefined) export ABC_CLOCK_PERIOD_IN_PS := $(shell sed -nE "s/^set\s+clk_period\s+(\S+).*|.*-period\s+(\S+).*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1}') endif endif - -# Get AutoTuner tunable variables -.PHONY: get_tunable_variables -get_tunable_variables: - @$(SCRIPTS_DIR)/tunable.py diff --git a/tools/AutoTuner/requirements.txt b/tools/AutoTuner/requirements.txt index 5bf65305cc..fb72219420 100644 --- a/tools/AutoTuner/requirements.txt +++ b/tools/AutoTuner/requirements.txt @@ -9,3 +9,4 @@ tensorboard>=2.14.0,<=2.16.2 protobuf==3.20.3 SQLAlchemy==1.4.17 urllib3<=1.26.15 +pyyaml==6.0.1 diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index bfa24af130..b6ca2c8c4a 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -32,6 +32,7 @@ import glob import subprocess import random +import yaml from datetime import datetime from multiprocessing import cpu_count from subprocess import run @@ -366,12 +367,24 @@ def parse_tunable_variables(): TODO: Tests. """ cur_path = os.path.dirname(os.path.realpath(__file__)) - makefile_path = os.path.join(cur_path, "../../../../flow/") + vars_path = os.path.join(cur_path, "../../../../flow/scripts") initial_path = os.path.abspath(os.getcwd()) - os.chdir(makefile_path) - result = subprocess.run(["make", "vars", f"PLATFORM={args.platform}"]) + + # Read from variables.yaml and get variables with tunable = 1 + os.chdir(vars_path) + if not os.path.exists("variables.yaml"): + print("[ERROR TUN-0018] variables.yaml not found.") + sys.exit(1) + with open("variables.yaml") as file: + try: + result = yaml.safe_load(file) + except yaml.YAMLError as exc: + print("[ERROR TUN-0019] Error parsing variables.yaml.") + sys.exit(1) + variables = {key: 1 for key, value in result.items() if value.get("tunable") == 1} + + # Return to initial path os.chdir(initial_path) - variables = [var.strip() for var in result.split("\n")] return variables @@ -403,7 +416,7 @@ def parse_config(config, path=os.getcwd()): else: # Default case is VAR=VALUE # Sanity check: ignore all flow variables that are not tunable - if key not in flow_variables: + if flow_variables.get(key, 0) == 1: print(f"[ERROR TUN-0017] Variable {key} is not tunable.") sys.exit(1) options += f" {key}={value}" From 3bbde14b63f50476ea8ace43d5c5f2cdc50c2569 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Sun, 13 Oct 2024 10:47:35 +0000 Subject: [PATCH 3/7] remove os.path checks Signed-off-by: Jack Luar --- tools/AutoTuner/src/autotuner/distributed.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index b6ca2c8c4a..d84a709dc2 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -372,14 +372,11 @@ def parse_tunable_variables(): # Read from variables.yaml and get variables with tunable = 1 os.chdir(vars_path) - if not os.path.exists("variables.yaml"): - print("[ERROR TUN-0018] variables.yaml not found.") - sys.exit(1) with open("variables.yaml") as file: try: result = yaml.safe_load(file) except yaml.YAMLError as exc: - print("[ERROR TUN-0019] Error parsing variables.yaml.") + print("[ERROR TUN-0018] Error parsing variables.yaml.") sys.exit(1) variables = {key: 1 for key, value in result.items() if value.get("tunable") == 1} From 44764cf015ee372f11e6a8f535bfb67ef33c14c7 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Mon, 14 Oct 2024 16:27:17 +0000 Subject: [PATCH 4/7] add bug fix to variable tunable check Signed-off-by: Jack Luar --- tools/AutoTuner/src/autotuner/distributed.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index d84a709dc2..7b05e9d325 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -413,7 +413,7 @@ def parse_config(config, path=os.getcwd()): else: # Default case is VAR=VALUE # Sanity check: ignore all flow variables that are not tunable - if flow_variables.get(key, 0) == 1: + if flow_variables.get(key, 0) == 0: print(f"[ERROR TUN-0017] Variable {key} is not tunable.") sys.exit(1) options += f" {key}={value}" From 7643a60e2f7379d9a1a0c0db075931e34cfb0e11 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Tue, 15 Oct 2024 12:52:12 +0000 Subject: [PATCH 5/7] add tunable 1 for fp variables Signed-off-by: Jack Luar --- flow/scripts/variables.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index bfe0050600..948d78073a 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -75,6 +75,7 @@ CORE_UTILIZATION: The core utilization percentage (0-100). stages: - floorplan + tunable: 1 CORE_AREA: description: > The core area specified as a list of lower-left and upper-right corners in microns @@ -515,6 +516,7 @@ CORE_ASPECT_RATIO: is undefined. stages: - floorplan + tunable: 1 CORE_MARGIN: description: > The margin between the core area and die area, in multiples of SITE heights. From d93180d92931c767f58cb1e4e33f0bc9b93dbfab Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Tue, 15 Oct 2024 23:47:48 +0000 Subject: [PATCH 6/7] revert flowvariables diff and remove os.chdir Signed-off-by: Jack Luar --- docs/user/FlowVariables.md | 2 +- tools/AutoTuner/src/autotuner/distributed.py | 9 ++------- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index a6785dbfa4..992aae1708 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -319,4 +319,4 @@ configuration file. - [SYNTH_ARGS](#SYNTH_ARGS) - [TAP_CELL_NAME](#TAP_CELL_NAME) - [TECH_LEF](#TECH_LEF) -- [USE_FILL](#USE_FILL) +- [USE_FILL](#USE_FILL) \ No newline at end of file diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index 7b05e9d325..77f237a9ec 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -367,21 +367,16 @@ def parse_tunable_variables(): TODO: Tests. """ cur_path = os.path.dirname(os.path.realpath(__file__)) - vars_path = os.path.join(cur_path, "../../../../flow/scripts") - initial_path = os.path.abspath(os.getcwd()) + vars_path = os.path.join(cur_path, "../../../../flow/scripts/variables.yaml") # Read from variables.yaml and get variables with tunable = 1 - os.chdir(vars_path) - with open("variables.yaml") as file: + with open(vars_path) as file: try: result = yaml.safe_load(file) except yaml.YAMLError as exc: print("[ERROR TUN-0018] Error parsing variables.yaml.") sys.exit(1) variables = {key: 1 for key, value in result.items() if value.get("tunable") == 1} - - # Return to initial path - os.chdir(initial_path) return variables From ca03a892f32b5122995cf1f52216d314c746dd86 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Sat, 19 Oct 2024 15:41:17 +0000 Subject: [PATCH 7/7] make variables a set for readability Signed-off-by: Jack Luar --- tools/AutoTuner/src/autotuner/distributed.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index 77f237a9ec..19856d1075 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -376,7 +376,7 @@ def parse_tunable_variables(): except yaml.YAMLError as exc: print("[ERROR TUN-0018] Error parsing variables.yaml.") sys.exit(1) - variables = {key: 1 for key, value in result.items() if value.get("tunable") == 1} + variables = {key for key, value in result.items() if value.get("tunable", 0) == 1} return variables @@ -408,7 +408,7 @@ def parse_config(config, path=os.getcwd()): else: # Default case is VAR=VALUE # Sanity check: ignore all flow variables that are not tunable - if flow_variables.get(key, 0) == 0: + if key in flow_variables: print(f"[ERROR TUN-0017] Variable {key} is not tunable.") sys.exit(1) options += f" {key}={value}"