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CPUProject.qsf
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CPUProject.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 22:30:17 February 07, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CPUProject_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 19:06:16 February 07, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CPUProject_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:06:16 FEBRUARY 07, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/saee_/Desktop/ComputerArchitectureProject-CPU/src/synthesis/Waveform.vwf"
set_global_assignment -name VERILOG_FILE src/SIGN_EXTENDER/SIGN_EXTENDER.v
set_global_assignment -name VERILOG_FILE src/FP_COPROCESSOR/MUX/FP_MUX.v
set_global_assignment -name VERILOG_FILE src/FP_COPROCESSOR/FP_MULT/MUX_5.v
set_global_assignment -name VERILOG_FILE src/FP_COPROCESSOR/FP_MULT/FP_MULT.v
set_global_assignment -name VERILOG_FILE src/FP_COPROCESSOR/FP_INVERSE/FP_INVERSE.v
set_global_assignment -name VERILOG_FILE src/FP_COPROCESSOR/FP_DIV/FP_DIV.v
set_global_assignment -name VERILOG_FILE src/FP_COPROCESSOR/FP_CONSTANT/A0_CONSTANT.v
set_global_assignment -name VERILOG_FILE src/FP_COPROCESSOR/FP_ADD_SUB/FP_ADD_SUB.v
set_global_assignment -name VERILOG_FILE src/INSTRUCTION_MEMORY/INSTRUCTION_MEMORY_2.v
set_global_assignment -name VERILOG_FILE src/PROGRAM_COUNTER/PC.v
set_global_assignment -name VERILOG_FILE src/CONTROL_UNIT/CONTROL_UNIT.v
set_global_assignment -name VERILOG_FILE src/AND_TWO_IN/AND_TWO_IN.v
set_global_assignment -name VERILOG_FILE src/XOR_TWO_IN/XOR_TWO_IN.v
set_global_assignment -name VERILOG_FILE src/alu_small_mux.v
set_global_assignment -name VERILOG_FILE src/alu_main_mux.v
set_global_assignment -name BDF_FILE src/ALU.bdf
set_global_assignment -name VERILOG_FILE src/MEMORY/MAIN_MEMORY.v
set_global_assignment -name VERILOG_FILE src/ZERO_EXTENDER/ZERO_EXTENDER.v
set_global_assignment -name VERILOG_FILE src/MUX/MULTIPLEXER.v
set_global_assignment -name VERILOG_FILE src/SHIFT2/SHIFT2.v
set_global_assignment -name VERILOG_FILE src/PC_ADDER/JUMP_ADDER.v
set_global_assignment -name QIP_FILE MULT.qip
set_global_assignment -name QIP_FILE DIV.qip
set_global_assignment -name QIP_FILE CMP.qip
set_global_assignment -name QIP_FILE ADDER_SUB.qip
set_global_assignment -name VERILOG_FILE SHIFT.v
set_global_assignment -name VERILOG_FILE ROTATE.v
set_global_assignment -name VERILOG_FILE MULT.v
set_global_assignment -name VERILOG_FILE DIV.v
set_global_assignment -name VERILOG_FILE CMP.v
set_global_assignment -name VERILOG_FILE ADDER_SUB.v
set_global_assignment -name VERILOG_FILE src/PC_ADDER/PC_ADDER.v
set_global_assignment -name VERILOG_FILE src/INSTRUCTION_MEMORY/INSTRUCTION_MEMORY.v
set_global_assignment -name VERILOG_FILE src/REGISTER_ARRAY/REGISTER_ARRAY.v
set_global_assignment -name BDF_FILE CPUProject.bdf
set_global_assignment -name QIP_FILE SHIFT.qip
set_global_assignment -name QIP_FILE ROTATE.qip
set_global_assignment -name BDF_FILE src/FP_COPROCESSOR/FP_COPROCESSOR.bdf
set_global_assignment -name QIP_FILE src/FP_COPROCESSOR/FP_ADD_SUB/FP_ADD_SUB.qip
set_global_assignment -name QIP_FILE src/FP_COPROCESSOR/FP_MULT/FP_MULT.qip
set_global_assignment -name QIP_FILE src/FP_COPROCESSOR/FP_DIV/FP_DIV.qip
set_global_assignment -name QIP_FILE src/FP_COPROCESSOR/MUX/FP_MUX.qip
set_global_assignment -name QIP_FILE src/PC_MUX/PC_MUX.qip
set_global_assignment -name BDF_FILE src/JUMP/JMP.bdf
set_global_assignment -name QIP_FILE src/JUMP/CONSTANT/CONSTANT.qip
set_global_assignment -name QIP_FILE src/JUMP/SHIFT/SHIFT_16BIT.qip
set_global_assignment -name QIP_FILE src/JUMP/CONSTANT/CONSTANT_18.qip
set_global_assignment -name QIP_FILE src/JUMP/ADD/ADD.qip
set_global_assignment -name QIP_FILE src/JUMP/SHIFT/SHIFT_5BIT.qip
set_global_assignment -name MIF_FILE src/INSTRUCTION_MEMORY/instructionMemoryInstructions.mif
set_global_assignment -name QIP_FILE src/SHIFT2/lpm_constant2.qip
set_global_assignment -name MIF_FILE src/MEMORY/mainMemoryInitial.mif
set_global_assignment -name VECTOR_WAVEFORM_FILE src/synthesis/Waveform.vwf
set_global_assignment -name QIP_FILE src/INSTRUCTION_MEMORY/INSTRUCTION_MEMORY_2.qip
set_global_assignment -name QIP_FILE src/MEMORY/MAIN_MEMORY_32.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top