diff --git a/CHANGELOG.md b/CHANGELOG.md index 11b06cfeb..3971acdd5 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,12 @@ # Changelog All notable changes to this project are documented in this file. +## [3.8.0] - 2024-10-17 +### Added +- Added multi-instance support in the DPPI driver. +- Added multi-instance driver for the PPIB. +- Added a function for interconnecting two DPPI domains in the GPPI helper. + ## [3.7.0] - 2024-09-27 ### Added - Added support for nRF54H20 Eng B. diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index b7cdd86f1..946d22fdb 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -50,7 +50,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "3.7" +PROJECT_NUMBER = "3.8" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a diff --git a/drivers/include/nrfx_dppi.h b/drivers/include/nrfx_dppi.h index ccfe92e29..9e09e67e0 100644 --- a/drivers/include/nrfx_dppi.h +++ b/drivers/include/nrfx_dppi.h @@ -37,6 +37,11 @@ #include #include +/* On devices with single instance (with no ID) use instance 0. */ +#if defined(NRF_DPPIC) && defined(NRFX_DPPI_ENABLED) && !defined(NRFX_DPPI0_ENABLED) +#define NRFX_DPPI0_ENABLED 1 +#endif + /** * @defgroup nrfx_dppi DPPI allocator * @{ @@ -44,12 +49,40 @@ * @brief Distributed Programmable Peripheral Interconnect (DPPI) allocator. */ +/** @brief Data structure of the Distributed programmable peripheral interconnect (DPPI) driver instance. */ +typedef struct +{ + NRF_DPPIC_Type * p_reg; ///< Pointer to a structure containing DPPIC registers. + uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only. +} nrfx_dppi_t; + +#ifndef __NRFX_DOXYGEN__ +enum { + /* List all enabled driver instances (in the format NRFX_\_INST_IDX). */ + NRFX_INSTANCE_ENUM_LIST(DPPI) + NRFX_DPPI_ENABLED_COUNT +}; +#endif + +/** @brief Macro for creating an instance of the DPPIC driver. */ +#define NRFX_DPPI_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT(NRF_, DPPIC, id), \ + .drv_inst_idx = NRFX_CONCAT(NRFX_DPPI, id, _INST_IDX), \ +} + #ifdef __cplusplus extern "C" { #endif -/** @brief Function for freeing all allocated channels and groups. */ -void nrfx_dppi_free(void); +#if NRFX_API_VER_AT_LEAST(3, 8, 0) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for freeing all allocated channels and groups. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_dppi_free(nrfx_dppi_t const * p_instance); /** * @brief Function for allocating a DPPI channel. @@ -57,12 +90,13 @@ void nrfx_dppi_free(void); * * @note Function is thread safe as it uses @ref nrfx_flag32_alloc. * - * @param[out] p_channel Pointer to the DPPI channel number that has been allocated. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[out] p_channel Pointer to the DPPI channel number that has been allocated. * * @retval NRFX_SUCCESS The channel was successfully allocated. * @retval NRFX_ERROR_NO_MEM There is no available channel to be used. */ -nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel); +nrfx_err_t nrfx_dppi_channel_alloc(nrfx_dppi_t const * p_instance, uint8_t * p_channel); /** * @brief Function for freeing a DPPI channel. @@ -71,22 +105,24 @@ nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel); * * @note Function is thread safe as it uses @ref nrfx_flag32_free. * - * @param[in] channel DPPI channel to be freed. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel DPPI channel to be freed. * * @retval NRFX_SUCCESS The channel was successfully freed. * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated. */ -nrfx_err_t nrfx_dppi_channel_free(uint8_t channel); +nrfx_err_t nrfx_dppi_channel_free(nrfx_dppi_t const * p_instance, uint8_t channel); /** * @brief Function for enabling a DPPI channel. * - * @param[in] channel DPPI channel to be enabled. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel DPPI channel to be enabled. * * @retval NRFX_SUCCESS The channel was successfully enabled. * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated. */ -nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel); +nrfx_err_t nrfx_dppi_channel_enable(nrfx_dppi_t const * p_instance, uint8_t channel); /** * @brief Function for disabling a DPPI channel. @@ -94,12 +130,13 @@ nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel); * @note Disabling channel does not modify PUBLISH/SUBSCRIBE registers configured to use * that channel. * - * @param[in] channel DPPI channel to be disabled. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel DPPI channel to be disabled. * * @retval NRFX_SUCCESS The channel was successfully disabled. * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated. */ -nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel); +nrfx_err_t nrfx_dppi_channel_disable(nrfx_dppi_t const * p_instance, uint8_t channel); /** * @brief Function for allocating a DPPI channel group. @@ -107,12 +144,14 @@ nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel); * * @note Function is thread safe as it uses @ref nrfx_flag32_alloc. * - * @param[out] p_group Pointer to the DPPI channel group that has been allocated. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[out] p_group Pointer to the DPPI channel group that has been allocated. * * @retval NRFX_SUCCESS The channel group was successfully allocated. * @retval NRFX_ERROR_NO_MEM There is no available channel group to be used. */ -nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group); +nrfx_err_t nrfx_dppi_group_alloc(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t * p_group); /** * @brief Function for freeing a DPPI channel group. @@ -120,18 +159,20 @@ nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group); * * @note Function is thread safe as it uses @ref nrfx_flag32_free. * - * @param[in] group DPPI channel group to be freed. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] group DPPI channel group to be freed. * * @retval NRFX_SUCCESS The channel group was successfully freed. * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated. */ -nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group); +nrfx_err_t nrfx_dppi_group_free(nrfx_dppi_t const * p_instance, nrf_dppi_channel_group_t group); /** * @brief Function for including a DPPI channel in a channel group. * - * @param[in] channel DPPI channel to be added. - * @param[in] group Channel group in which to include the channel. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel DPPI channel to be added. + * @param[in] group Channel group in which to include the channel. * * @warning Channel group configuration can be modified only if subscriptions for tasks * associated with this group are disabled. @@ -139,14 +180,16 @@ nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group); * @retval NRFX_SUCCESS The channel was successfully included. * @retval NRFX_ERROR_INVALID_PARAM The specified group or channel is not allocated. */ -nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, +nrfx_err_t nrfx_dppi_channel_include_in_group(nrfx_dppi_t const * p_instance, + uint8_t channel, nrf_dppi_channel_group_t group); /** * @brief Function for removing a DPPI channel from a channel group. * - * @param[in] channel DPPI channel to be removed. - * @param[in] group Channel group from which to remove the channel. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel DPPI channel to be removed. + * @param[in] group Channel group from which to remove the channel. * * @warning Channel group configuration can be modified only if subscriptions for tasks * associated with this group are disabled. @@ -154,13 +197,15 @@ nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, * @retval NRFX_SUCCESS The channel was successfully removed. * @retval NRFX_ERROR_INVALID_PARAM The specified group or channel is not allocated. */ -nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel, +nrfx_err_t nrfx_dppi_channel_remove_from_group(nrfx_dppi_t const * p_instance, + uint8_t channel, nrf_dppi_channel_group_t group); /** * @brief Function for clearing a DPPI channel group. * - * @param[in] group Channel group to be cleared. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] group Channel group to be cleared. * * @warning Channel group configuration can be modified only if subscriptions for tasks * associated with this group are disabled. @@ -168,28 +213,73 @@ nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel, * @retval NRFX_SUCCESS The group was successfully cleared. * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated. */ -nrfx_err_t nrfx_dppi_group_clear(nrf_dppi_channel_group_t group); +nrfx_err_t nrfx_dppi_group_clear(nrfx_dppi_t const * p_instance, nrf_dppi_channel_group_t group); /** * @brief Function for enabling a DPPI channel group. * - * @param[in] group Channel group to be enabled. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] group Channel group to be enabled. * * @retval NRFX_SUCCESS The group was successfully enabled. * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated. */ -nrfx_err_t nrfx_dppi_group_enable(nrf_dppi_channel_group_t group); +nrfx_err_t nrfx_dppi_group_enable(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t group); /** * @brief Function for disabling a DPPI channel group. * - * @param[in] group Channel group to be disabled. + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] group Channel group to be disabled. * * @retval NRFX_SUCCESS The group was successfully disabled. * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated. */ +nrfx_err_t nrfx_dppi_group_disable(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t group); + +#else + +#if !defined(NRF_DPPIC_INDEX) +/* Choose the instance to use in case of using deprecated single-instance driver variant. */ +#if defined(HALTIUM_XXAA) +#define NRF_DPPIC_INDEX 130 +#elif defined(LUMOS_XXAA) +#define NRF_DPPIC_INDEX 20 +#else +#define NRF_DPPIC_INDEX 0 +#endif +#endif + +void nrfx_dppi_free(void); + +nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel); + +nrfx_err_t nrfx_dppi_channel_free(uint8_t channel); + +nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel); + +nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel); + +nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group); + +nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group); + +nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, + nrf_dppi_channel_group_t group); + +nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel, + nrf_dppi_channel_group_t group); + +nrfx_err_t nrfx_dppi_group_clear(nrf_dppi_channel_group_t group); + +nrfx_err_t nrfx_dppi_group_enable(nrf_dppi_channel_group_t group); + nrfx_err_t nrfx_dppi_group_disable(nrf_dppi_channel_group_t group); +#endif + /** @} */ #ifdef __cplusplus diff --git a/drivers/include/nrfx_ppib.h b/drivers/include/nrfx_ppib.h new file mode 100644 index 000000000..6040ff9b7 --- /dev/null +++ b/drivers/include/nrfx_ppib.h @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_PPIB_H__ +#define NRFX_PPIB_H__ + +#include +#include + +/** + * @defgroup nrfx_ppib PPIB allocator + * @{ + * @ingroup nrf_ppib + * @brief Programmable Peripheral Interconnect Bridge (PPIB) allocator. + */ + +/** @brief Data structure of the Programmable Peripheral Interconnect Bridge (PPIB) driver instance. */ +typedef struct +{ + NRF_PPIB_Type * p_reg; ///< Pointer to a structure containing PPIBC registers. +} nrfx_ppib_t; + +/** @brief Data structure of the pair of PPIB driver instances. */ +typedef struct +{ + nrfx_ppib_t left; ///< First driver instance. + nrfx_ppib_t right; ///< Second driver instance. + uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only. +} nrfx_ppib_interconnect_t; + +#ifndef __NRFX_DOXYGEN__ +enum { + /* List all enabled driver instances (in the format NRFX_\_INST_IDX). */ + NRFX_INSTANCE_ENUM_LIST(PPIB) + NRFX_PPIB_ENABLED_COUNT +}; + +enum { + /* List all enabled interconnects. Smaller PPIB idx are always on the left. */ +#if defined(NRF54L15_ENGA_XXAA) || defined(NRF54L15_XXAA) || defined(NRF54L20_ENGA_XXAA) +#if NRFX_CHECK(NRFX_PPIB00_ENABLED) && NRFX_CHECK(NRFX_PPIB10_ENABLED) + NRFX_PPIB_INTERCONNECT_00_10_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_PPIB01_ENABLED) && NRFX_CHECK(NRFX_PPIB20_ENABLED) + NRFX_PPIB_INTERCONNECT_01_20_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_PPIB11_ENABLED) && NRFX_CHECK(NRFX_PPIB21_ENABLED) + NRFX_PPIB_INTERCONNECT_11_21_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_PPIB22_ENABLED) && NRFX_CHECK(NRFX_PPIB30_ENABLED) + NRFX_PPIB_INTERCONNECT_22_30_INST_IDX, +#endif +#endif +#if defined(NRF54L20_ENGA_XXAA) +#if NRFX_CHECK(NRFX_PPIB02_ENABLED) && NRFX_CHECK(NRFX_PPIB03_ENABLED) + NRFX_PPIB_INTERCONNECT_02_03_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_PPIB04_ENABLED) && NRFX_CHECK(NRFX_PPIB12_ENABLED) + NRFX_PPIB_INTERCONNECT_04_12_INST_IDX, +#endif +#endif +#if defined(HALTIUM_XXAA) +#if NRFX_CHECK(NRFX_PPIB020_ENABLED) && NRFX_CHECK(NRFX_PPIB030_ENABLED) + NRFX_PPIB_INTERCONNECT_020_030_INST_IDX, +#endif +#endif + NRFX_PPIB_INTERCONNECT_COUNT +}; +#endif + +/** @brief Macro for creating an instance of the PPIB driver. */ +#define NRFX_PPIB_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT(NRF_, PPIB, id), \ +} + +/** @brief Macro for creating an instance of the PPIB interconnect driver. */ +#define NRFX_PPIB_INTERCONNECT_INSTANCE(id_left, id_right) \ +{ \ + .left = NRFX_PPIB_INSTANCE(id_left), \ + .right = NRFX_PPIB_INSTANCE(id_right), \ + .drv_inst_idx = NRFX_CONCAT(NRFX_PPIB_INTERCONNECT_, id_left, _, id_right, _INST_IDX), \ +} + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Function for freeing all allocated channels for a given PPIB interconnection. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_ppib_free(nrfx_ppib_interconnect_t const * p_instance); + +/** + * @brief Function for allocating a PPIB channel. + * @details This function allocates the highest available PPIB channel. + * + * @note Function is thread safe as it uses @ref nrfx_flag32_alloc. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[out] p_channel Pointer to the PPIB channel number that has been allocated. + * + * @retval NRFX_SUCCESS The channel was successfully allocated. + * @retval NRFX_ERROR_NO_MEM There is no available channel to be used. + */ +nrfx_err_t nrfx_ppib_channel_alloc(nrfx_ppib_interconnect_t const * p_instance, uint8_t * p_channel); + +/** + * @brief Function for freeing a PPIB channel. + * @details This function also clears the PUBLISH/SUBSCRIBE configuration. + * + * @note Function is thread safe as it uses @ref nrfx_flag32_free. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel PPIB channel to be freed. + * + * @retval NRFX_SUCCESS The channel was successfully freed. + * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated. + */ +nrfx_err_t nrfx_ppib_channel_free(nrfx_ppib_interconnect_t const * p_instance, uint8_t channel); + +/** + * @brief Function for getting the PPIB SEND task for the specified channel. + * + * @details The returned task identifier can be used within @ref nrf_ppib_hal, + * for example, to configure a DPPI channel. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel PPIB channel. + * + * @return SEND task associated with the specified channel. + */ +NRFX_STATIC_INLINE nrf_ppib_task_t nrfx_ppib_send_task_get(nrfx_ppib_t const * p_instance, + uint8_t channel); + +/** + * @brief Function for getting the address of the PPIB SEND task for the specified channel. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel PPIB channel. + * + * @return Address of the specified SEND task. + */ +NRFX_STATIC_INLINE uint32_t nrfx_ppib_send_task_address_get(nrfx_ppib_t const * p_instance, + uint8_t channel); + +/** + * @brief Function for getting the PPIB RECEIVE event for the specified channel. + * + * @details The returned event identifier can be used within @ref nrf_ppib_hal, + * for example, to configure a DPPI channel. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel PPIB channel. + * + * @return RECEIVE event associated with the specified channel. + */ +NRFX_STATIC_INLINE nrf_ppib_event_t nrfx_ppib_receive_event_get(nrfx_ppib_t const * p_instance, + uint8_t channel); + +/** + * @brief Function for getting the address of a PPIB RECEIVE event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel PPIB channel. + * + * @return Address of the specified RECEIVE event. + */ +NRFX_STATIC_INLINE uint32_t nrfx_ppib_receive_event_address_get(nrfx_ppib_t const * p_instance, + uint8_t channel); + +/** + * @brief Function for setting the subscribe configuration for a given + * PPIB task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] task Task for which to set the configuration. + * @param[in] channel Channel through which to subscribe events. + */ +NRF_STATIC_INLINE void nrfx_ppib_subscribe_set(nrfx_ppib_t const * p_instance, + nrf_ppib_task_t task, + uint8_t channel); + +/** + * @brief Function for clearing the subscribe configuration for a given + * PPIB task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] task Task for which to clear the configuration. + */ +NRF_STATIC_INLINE void nrfx_ppib_subscribe_clear(nrfx_ppib_t const * p_instance, + nrf_ppib_task_t task); + +/** + * @brief Function for setting the publish configuration for a given event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event Event for which to set the configuration. + * @param[in] channel PPIB channel through which to publish the event. + */ +NRF_STATIC_INLINE void nrfx_ppib_publish_set(nrfx_ppib_t const * p_instance, + nrf_ppib_event_t event, + uint8_t channel); +/** + * @brief Function for clearing the publish configuration for a given event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event Event for which to clear the configuration. + */ +NRF_STATIC_INLINE void nrfx_ppib_publish_clear(nrfx_ppib_t const * p_instance, + nrf_ppib_event_t event); +#ifndef NRFX_DECLARE_ONLY + +NRFX_STATIC_INLINE nrf_ppib_task_t nrfx_ppib_send_task_get(nrfx_ppib_t const * p_instance, + uint8_t channel) +{ + (void) p_instance; + + return nrf_ppib_send_task_get(channel); +} + +NRFX_STATIC_INLINE uint32_t nrfx_ppib_send_task_address_get(nrfx_ppib_t const * p_instance, + uint8_t channel) +{ + return nrf_ppib_task_address_get(p_instance->p_reg, nrf_ppib_send_task_get(channel)); +} + +NRFX_STATIC_INLINE nrf_ppib_event_t nrfx_ppib_receive_event_get(nrfx_ppib_t const * p_instance, + uint8_t channel) +{ + (void) p_instance; + + return nrf_ppib_receive_event_get(channel); +} + +NRFX_STATIC_INLINE uint32_t nrfx_ppib_receive_event_address_get(nrfx_ppib_t const * p_instance, + uint8_t channel) +{ + return nrf_ppib_event_address_get(p_instance->p_reg, nrf_ppib_receive_event_get(channel)); +} + +NRF_STATIC_INLINE void nrfx_ppib_subscribe_set(nrfx_ppib_t const * p_instance, + nrf_ppib_task_t task, + uint8_t channel) +{ + nrf_ppib_subscribe_set(p_instance->p_reg, task, channel); +} + +NRF_STATIC_INLINE void nrfx_ppib_subscribe_clear(nrfx_ppib_t const * p_instance, + nrf_ppib_task_t task) +{ + nrf_ppib_subscribe_clear(p_instance->p_reg, task); +} + +NRF_STATIC_INLINE void nrfx_ppib_publish_set(nrfx_ppib_t const * p_instance, + nrf_ppib_event_t event, + uint8_t channel) +{ + nrf_ppib_publish_set(p_instance->p_reg, event, channel); +} + +NRF_STATIC_INLINE void nrfx_ppib_publish_clear(nrfx_ppib_t const * p_instance, + nrf_ppib_event_t event) +{ + nrf_ppib_publish_clear(p_instance->p_reg, event); +} + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_PPIB_H__ diff --git a/drivers/src/nrfx_dppi.c b/drivers/src/nrfx_dppi.c index cf1e26797..af765bd2e 100644 --- a/drivers/src/nrfx_dppi.c +++ b/drivers/src/nrfx_dppi.c @@ -34,7 +34,7 @@ #include // Driver for single instance DPPI -#if NRFX_CHECK(NRFX_DPPI_ENABLED) && (!defined(DPPIC_COUNT) || (DPPIC_COUNT == 1)) +#if NRFX_CHECK(NRFX_DPPI_ENABLED) #include #include @@ -42,198 +42,615 @@ #define NRFX_LOG_MODULE DPPI #include -#if !defined(NRFX_DPPI_CHANNELS_USED) -// Default mask of DPPI channels reserved for other modules. -#define NRFX_DPPI_CHANNELS_USED 0x00000000uL +#if defined(NRFX_DPPI_CHANNELS_USED) +#define NRFX_DPPI0_CHANNELS_USED NRFX_DPPI_CHANNELS_USED #endif -#if !defined(NRFX_DPPI_GROUPS_USED) -// Default mask of DPPI groups reserved for other modules. -#define NRFX_DPPI_GROUPS_USED 0x00000000uL +#if defined(NRFX_DPPI_GROUPS_USED) +#define NRFX_DPPI0_GROUPS_USED NRFX_DPPI_GROUPS_USED #endif -#define DPPI_AVAILABLE_CHANNELS_MASK \ - ((uint32_t)(NRFX_BIT_MASK(NRF_DPPI_CH_NUM_MAX) & (~NRFX_DPPI_CHANNELS_USED))) +#if defined(NRF_DPPIC0) -#define DPPI_AVAILABLE_GROUPS_MASK \ - (NRFX_BIT_MASK(NRF_DPPI_GROUP_NUM_MAX) & (~NRFX_DPPI_GROUPS_USED)) +#if !defined(NRFX_DPPI0_CHANNELS_USED) +/* Bitmask that defines DPPI0 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI0_CHANNELS_USED 0UL +#endif -/** @brief Set bit at given position. */ -#define DPPI_BIT_SET(pos) (1uL << (pos)) +#if !defined(NRFX_DPPI0_GROUPS_USED) +/* Bitmask that defines DPPI0 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI0_GROUPS_USED 0UL +#endif -/**< Bitmap representing channels availability. */ -static nrfx_atomic_t m_allocated_channels = DPPI_AVAILABLE_CHANNELS_MASK; -/**< Bitmap representing groups availability. */ -static nrfx_atomic_t m_allocated_groups = DPPI_AVAILABLE_GROUPS_MASK; +#endif -void nrfx_dppi_free(void) +#if defined(NRF_DPPIC1) + +#if !defined(NRFX_DPPI1_CHANNELS_USED) +/* Bitmask that defines DPPI1 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI1_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI1_GROUPS_USED) +/* Bitmask that defines DPPI1 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI1_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC00) + +#if !defined(NRFX_DPPI00_CHANNELS_USED) +/* Bitmask that defines DPPI00 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI00_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI00_GROUPS_USED) +/* Bitmask that defines DPPI00 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI00_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC01) + +#if !defined(NRFX_DPPI01_CHANNELS_USED) +/* Bitmask that defines DPPI01 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI01_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI01_GROUPS_USED) +/* Bitmask that defines DPPI01 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI01_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC10) + +#if !defined(NRFX_DPPI10_CHANNELS_USED) +/* Bitmask that defines DPPI10 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI10_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI10_GROUPS_USED) +/* Bitmask that defines DPPI10 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI10_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC20) + +#if !defined(NRFX_DPPI20_CHANNELS_USED) +/* Bitmask that defines DPPI20 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI20_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI20_GROUPS_USED) +/* Bitmask that defines DPPI20 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI20_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC30) + +#if !defined(NRFX_DPPI30_CHANNELS_USED) +/* Bitmask that defines DPPI30 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI30_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI30_GROUPS_USED) +/* Bitmask that defines DPPI30 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI30_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC020) + +#if !defined(NRFX_DPPI020_CHANNELS_USED) +/* Bitmask that defines DPPI020 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI020_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI020_GROUPS_USED) +/* Bitmask that defines DPPI020 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI020_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC030) + +#if !defined(NRFX_DPPI030_CHANNELS_USED) +/* Bitmask that defines DPPI030 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI030_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI030_GROUPS_USED) +/* Bitmask that defines DPPI030 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI030_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC120) + +#if !defined(NRFX_DPPI120_CHANNELS_USED) +/* Bitmask that defines DPPI120 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI120_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI120_GROUPS_USED) +/* Bitmask that defines DPPI120 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI120_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC130) + +#if !defined(NRFX_DPPI130_CHANNELS_USED) +/* Bitmask that defines DPPI130 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI130_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI130_GROUPS_USED) +/* Bitmask that defines DPPI130 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI130_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC131) + +#if !defined(NRFX_DPPI131_CHANNELS_USED) +/* Bitmask that defines DPPI131 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI131_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI131_GROUPS_USED) +/* Bitmask that defines DPPI131 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI131_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC132) + +#if !defined(NRFX_DPPI132_CHANNELS_USED) +/* Bitmask that defines DPPI132 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI132_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI132_GROUPS_USED) +/* Bitmask that defines DPPI132 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI132_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC133) + +#if !defined(NRFX_DPPI133_CHANNELS_USED) +/* Bitmask that defines DPPI133 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI133_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI133_GROUPS_USED) +/* Bitmask that defines DPPI133 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI133_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC134) + +#if !defined(NRFX_DPPI134_CHANNELS_USED) +/* Bitmask that defines DPPI134 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI134_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI134_GROUPS_USED) +/* Bitmask that defines DPPI134 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI134_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC135) + +#if !defined(NRFX_DPPI135_CHANNELS_USED) +/* Bitmask that defines DPPI135 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI135_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI135_GROUPS_USED) +/* Bitmask that defines DPPI135 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI135_GROUPS_USED 0UL +#endif + +#endif + +#if defined(NRF_DPPIC136) + +#if !defined(NRFX_DPPI136_CHANNELS_USED) +/* Bitmask that defines DPPI136 channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI136_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_DPPI136_GROUPS_USED) +/* Bitmask that defines DPPI136 groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI136_GROUPS_USED 0UL +#endif + +#endif + +#define DPPI_CHANNELS_NUM(idx) NRFX_BIT_MASK(NRFX_CONCAT(DPPIC, idx, _CH_NUM) +#define DPPI_CHANNELS_USED(idx) NRFX_CONCAT(NRFX_DPPI, idx, _CHANNELS_USED) +#define DPPI_AVAILABLE_CHANNELS_MASK(idx) \ + ((uint32_t)(DPPI_CHANNELS_NUM(idx)) & ~(DPPI_CHANNELS_USED(idx)))) + +#define DPPI_GROUPS_NUM(idx) NRFX_BIT_MASK(NRFX_CONCAT(DPPIC, idx, _GROUP_NUM) +#define DPPI_GROUPS_USED(idx) NRFX_CONCAT(NRFX_DPPI, idx, _GROUPS_USED) +#define DPPI_AVAILABLE_GROUPS_MASK(idx) \ + ((uint32_t)(DPPI_GROUPS_NUM(idx)) & ~(DPPI_GROUPS_USED(idx)))) + +/* Structure holding state of the pins */ +typedef struct { - uint32_t mask = DPPI_AVAILABLE_GROUPS_MASK & ~m_allocated_groups; + /**< Bitmap representing channels availability. */ + nrfx_atomic_t allocated_channels; + /**< Bitmap representing groups availability. */ + nrfx_atomic_t allocated_groups; + /**< Bitmap representing available channels. */ + const uint32_t available_channels; + /**< Bitmap representing available groups. */ + const uint32_t available_groups; +} dppic_control_block_t; + +#define _NRFX_DPPIC_CB_INITIALIZER(periph_name, prefix, idx, _) \ + [NRFX_CONCAT(NRFX_, periph_name, prefix##idx, _INST_IDX)] = { \ + .allocated_channels = (nrfx_atomic_t)DPPI_AVAILABLE_CHANNELS_MASK(prefix##idx), \ + .allocated_groups = (nrfx_atomic_t)DPPI_AVAILABLE_GROUPS_MASK(prefix##idx), \ + .available_channels = DPPI_AVAILABLE_CHANNELS_MASK(prefix##idx), \ + .available_groups = DPPI_AVAILABLE_GROUPS_MASK(prefix##idx), \ + }, + +static dppic_control_block_t m_cb[NRFX_DPPI_ENABLED_COUNT] = { + NRFX_FOREACH_ENABLED(DPPI, _NRFX_DPPIC_CB_INITIALIZER, (), ()) +}; + +static void dppi_free(nrfx_dppi_t const * p_instance) +{ + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + uint32_t mask = p_cb->available_groups & ~p_cb->allocated_groups; uint8_t group_idx = NRF_DPPI_CHANNEL_GROUP0; // Disable all channels - nrfy_dppi_channels_disable(NRF_DPPIC, DPPI_AVAILABLE_CHANNELS_MASK & ~m_allocated_channels); + nrfy_dppi_channels_disable(p_instance->p_reg, p_cb->available_channels & ~p_cb->allocated_channels); // Clear all groups configurations while (mask) { nrf_dppi_channel_group_t group = (nrf_dppi_channel_group_t)group_idx; - if (mask & DPPI_BIT_SET(group)) + if (mask & NRFX_BIT(group)) { - nrfy_dppi_group_clear(NRF_DPPIC, group); - mask &= ~DPPI_BIT_SET(group); + nrfy_dppi_group_clear(p_instance->p_reg, group); + mask &= ~NRFX_BIT(group); } group_idx++; } // Clear all allocated channels. - m_allocated_channels = DPPI_AVAILABLE_CHANNELS_MASK; + p_cb->allocated_channels = p_cb->available_channels; // Clear all allocated groups. - m_allocated_groups = DPPI_AVAILABLE_GROUPS_MASK; + p_cb->allocated_groups = p_cb->available_groups; } -nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel) +static nrfx_err_t dppi_channel_alloc(nrfx_dppi_t const * p_instance, uint8_t * p_channel) { - return nrfx_flag32_alloc(&m_allocated_channels, p_channel); + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + return nrfx_flag32_alloc(&p_cb->allocated_channels, p_channel); } -nrfx_err_t nrfx_dppi_channel_free(uint8_t channel) +static nrfx_err_t dppi_channel_free(nrfx_dppi_t const * p_instance, uint8_t channel) { - nrfy_dppi_channels_disable(NRF_DPPIC, NRFX_BIT(channel)); - return nrfx_flag32_free(&m_allocated_channels, channel); + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + nrfy_dppi_channels_disable(p_instance->p_reg, NRFX_BIT(channel)); + return nrfx_flag32_free(&p_cb->allocated_channels, channel); } -nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel) +static nrfx_err_t dppi_channel_enable(nrfx_dppi_t const * p_instance, uint8_t channel) { + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + nrfx_err_t err_code = NRFX_SUCCESS; - if (!nrfx_flag32_is_allocated(m_allocated_channels, channel)) + if (!nrfx_flag32_is_allocated(p_cb->allocated_channels, channel)) { err_code = NRFX_ERROR_INVALID_PARAM; } else { - nrfy_dppi_channels_enable(NRF_DPPIC, DPPI_BIT_SET(channel)); + nrfy_dppi_channels_enable(p_instance->p_reg, NRFX_BIT(channel)); } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } -nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel) +static nrfx_err_t dppi_channel_disable(nrfx_dppi_t const * p_instance, uint8_t channel) { + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + nrfx_err_t err_code = NRFX_SUCCESS; - if (!nrfx_flag32_is_allocated(m_allocated_channels, channel)) + if (!nrfx_flag32_is_allocated(p_cb->allocated_channels, channel)) { err_code = NRFX_ERROR_INVALID_PARAM; } else { - nrfy_dppi_channels_disable(NRF_DPPIC, DPPI_BIT_SET(channel)); + nrfy_dppi_channels_disable(p_instance->p_reg, NRFX_BIT(channel)); err_code = NRFX_SUCCESS; } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } -nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group) +static nrfx_err_t dppi_group_alloc(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t * p_group) { - return nrfx_flag32_alloc(&m_allocated_groups, (uint8_t *)p_group); + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + return nrfx_flag32_alloc(&p_cb->allocated_groups, (uint8_t *)p_group); } -nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group) +static nrfx_err_t dppi_group_free(nrfx_dppi_t const * p_instance, nrf_dppi_channel_group_t group) { - nrfy_dppi_group_disable(NRF_DPPIC, group); - return nrfx_flag32_free(&m_allocated_groups, group); + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + nrfy_dppi_group_disable(p_instance->p_reg, group); + return nrfx_flag32_free(&p_cb->allocated_groups, group); } -nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, - nrf_dppi_channel_group_t group) +static nrfx_err_t dppi_channel_include_in_group(nrfx_dppi_t const * p_instance, + uint8_t channel, + nrf_dppi_channel_group_t group) { + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; nrfx_err_t err_code = NRFX_SUCCESS; - if (!nrfx_flag32_is_allocated(m_allocated_groups, group) || - !nrfx_flag32_is_allocated(m_allocated_channels, channel)) + if (!nrfx_flag32_is_allocated(p_cb->allocated_groups, group) || + !nrfx_flag32_is_allocated(p_cb->allocated_channels, channel)) { err_code = NRFX_ERROR_INVALID_PARAM; } else { NRFY_CRITICAL_SECTION_ENTER(); - nrfy_dppi_channels_include_in_group(NRF_DPPIC, DPPI_BIT_SET(channel), group); + nrfy_dppi_channels_include_in_group(p_instance->p_reg, NRFX_BIT(channel), group); NRFY_CRITICAL_SECTION_EXIT(); } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } -nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel, - nrf_dppi_channel_group_t group) +static nrfx_err_t dppi_channel_remove_from_group(nrfx_dppi_t const * p_instance, + uint8_t channel, + nrf_dppi_channel_group_t group) { + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; nrfx_err_t err_code = NRFX_SUCCESS; - if (!nrfx_flag32_is_allocated(m_allocated_groups, group) || - !nrfx_flag32_is_allocated(m_allocated_channels, channel)) + if (!nrfx_flag32_is_allocated(p_cb->allocated_groups, group) || + !nrfx_flag32_is_allocated(p_cb->allocated_channels, channel)) { err_code = NRFX_ERROR_INVALID_PARAM; } else { NRFY_CRITICAL_SECTION_ENTER(); - nrfy_dppi_channels_remove_from_group(NRF_DPPIC, DPPI_BIT_SET(channel), group); + nrfy_dppi_channels_remove_from_group(p_instance->p_reg, NRFX_BIT(channel), group); NRFY_CRITICAL_SECTION_EXIT(); } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } -nrfx_err_t nrfx_dppi_group_clear(nrf_dppi_channel_group_t group) +static nrfx_err_t dppi_group_clear(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t group) { + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; nrfx_err_t err_code = NRFX_SUCCESS; - if (!nrfx_flag32_is_allocated(m_allocated_groups, group)) + if (!nrfx_flag32_is_allocated(p_cb->allocated_groups, group)) { err_code = NRFX_ERROR_INVALID_PARAM; } else { - nrfy_dppi_channels_remove_from_group(NRF_DPPIC, DPPI_AVAILABLE_CHANNELS_MASK, group); + nrfy_dppi_channels_remove_from_group(p_instance->p_reg, p_cb->available_channels, group); } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } -nrfx_err_t nrfx_dppi_group_enable(nrf_dppi_channel_group_t group) +static nrfx_err_t dppi_group_enable(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t group) { + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; nrfx_err_t err_code = NRFX_SUCCESS; - if (!nrfx_flag32_is_allocated(m_allocated_groups, group)) + if (!nrfx_flag32_is_allocated(p_cb->allocated_groups, group)) { err_code = NRFX_ERROR_INVALID_PARAM; } else { - nrfy_dppi_group_enable(NRF_DPPIC, group); + nrfy_dppi_group_enable(p_instance->p_reg, group); } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } -nrfx_err_t nrfx_dppi_group_disable(nrf_dppi_channel_group_t group) +static nrfx_err_t dppi_group_disable(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t group) { + dppic_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; nrfx_err_t err_code = NRFX_SUCCESS; - if (!nrfx_flag32_is_allocated(m_allocated_groups, group)) + if (!nrfx_flag32_is_allocated(p_cb->allocated_groups, group)) { err_code = NRFX_ERROR_INVALID_PARAM; } else { - nrfy_dppi_group_disable(NRF_DPPIC, group); + nrfy_dppi_group_disable(p_instance->p_reg, group); } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } -#endif // defined(DPPI_PRESENT) && defined(DPPIC_COUNT == 1) +#if NRFX_API_VER_AT_LEAST(3, 8, 0) + +void nrfx_dppi_free(nrfx_dppi_t const * p_instance) +{ + dppi_free(p_instance); +} + +nrfx_err_t nrfx_dppi_channel_alloc(nrfx_dppi_t const * p_instance, uint8_t * p_channel) +{ + return dppi_channel_alloc(p_instance, p_channel); +} + +nrfx_err_t nrfx_dppi_channel_free(nrfx_dppi_t const * p_instance, uint8_t channel) +{ + return dppi_channel_free(p_instance, channel); +} + +nrfx_err_t nrfx_dppi_channel_enable(nrfx_dppi_t const * p_instance, uint8_t channel) +{ + return dppi_channel_enable(p_instance, channel); +} + +nrfx_err_t nrfx_dppi_channel_disable(nrfx_dppi_t const * p_instance, uint8_t channel) +{ + return dppi_channel_disable(p_instance, channel); +} + +nrfx_err_t nrfx_dppi_group_alloc(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t * p_group) +{ + return dppi_group_alloc(p_instance, p_group); +} + +nrfx_err_t nrfx_dppi_group_free(nrfx_dppi_t const * p_instance, nrf_dppi_channel_group_t group) +{ + return dppi_group_free(p_instance, group); +} + +nrfx_err_t nrfx_dppi_channel_include_in_group(nrfx_dppi_t const * p_instance, + uint8_t channel, + nrf_dppi_channel_group_t group) +{ + return dppi_channel_include_in_group(p_instance, channel, group); +} + +nrfx_err_t nrfx_dppi_channel_remove_from_group(nrfx_dppi_t const * p_instance, + uint8_t channel, + nrf_dppi_channel_group_t group) +{ + return dppi_channel_remove_from_group(p_instance, channel, group); +} + +nrfx_err_t nrfx_dppi_group_clear(nrfx_dppi_t const * p_instance, nrf_dppi_channel_group_t group) +{ + return dppi_group_clear(p_instance, group); +} + +nrfx_err_t nrfx_dppi_group_enable(nrfx_dppi_t const * p_instance, nrf_dppi_channel_group_t group) +{ + return dppi_group_enable(p_instance, group); +} + +nrfx_err_t nrfx_dppi_group_disable(nrfx_dppi_t const * p_instance, + nrf_dppi_channel_group_t group) +{ + return dppi_group_disable(p_instance, group); +} + +#else + +nrfx_dppi_t const dppi_instance = NRFX_DPPI_INSTANCE(NRF_DPPIC_INDEX); + +void nrfx_dppi_free(void) +{ + dppi_free(&dppi_instance); +} + +nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel) +{ + return dppi_channel_alloc(&dppi_instance, p_channel); +} + +nrfx_err_t nrfx_dppi_channel_free(uint8_t channel) +{ + return dppi_channel_free(&dppi_instance, channel); +} + +nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel) +{ + return dppi_channel_enable(&dppi_instance, channel); +} + +nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel) +{ + return dppi_channel_disable(&dppi_instance, channel); +} + +nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group) +{ + return dppi_group_alloc(&dppi_instance, p_group); +} + +nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group) +{ + return dppi_group_free(&dppi_instance, group); +} + +nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, + nrf_dppi_channel_group_t group) +{ + return dppi_channel_include_in_group(&dppi_instance, channel, group); +} + +nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel, + nrf_dppi_channel_group_t group) +{ + return dppi_channel_remove_from_group(&dppi_instance, channel, group); +} + +nrfx_err_t nrfx_dppi_group_clear(nrf_dppi_channel_group_t group) +{ + return dppi_group_clear(&dppi_instance, group); +} + +nrfx_err_t nrfx_dppi_group_enable(nrf_dppi_channel_group_t group) +{ + return dppi_group_enable(&dppi_instance, group); +} + +nrfx_err_t nrfx_dppi_group_disable(nrf_dppi_channel_group_t group) +{ + return dppi_group_disable(&dppi_instance, group); +} + +#endif + +#endif // NRFX_CHECK(NRFX_DPPI_ENABLED) diff --git a/drivers/src/nrfx_lpcomp.c b/drivers/src/nrfx_lpcomp.c index 263bea791..67b027ea7 100644 --- a/drivers/src/nrfx_lpcomp.c +++ b/drivers/src/nrfx_lpcomp.c @@ -250,6 +250,11 @@ void nrfx_lpcomp_stop(void) NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); nrfy_lpcomp_disable(NRF_LPCOMP); nrfy_lpcomp_task_trigger(NRF_LPCOMP, NRF_LPCOMP_TASK_STOP); + nrfy_lpcomp_int_disable(NRF_LPCOMP, + NRF_LPCOMP_INT_READY_MASK | + NRF_LPCOMP_INT_DOWN_MASK | + NRF_LPCOMP_INT_UP_MASK | + NRF_LPCOMP_INT_CROSS_MASK); m_state = NRFX_DRV_STATE_INITIALIZED; NRFX_LOG_INFO("Disabled."); } diff --git a/drivers/src/nrfx_ppib.c b/drivers/src/nrfx_ppib.c new file mode 100644 index 000000000..17ebff840 --- /dev/null +++ b/drivers/src/nrfx_ppib.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#if NRFX_CHECK(NRFX_PPIB_ENABLED) + +#include +#include + +#define NRFX_LOG_MODULE PPIB +#include + +#if !defined(__NRFX_DOXYGEN__) + +#if defined(NRF54L15_ENGA_XXAA) || defined(NRF54L15_XXAA) || defined(NRF54L20_ENGA_XXAA) + +#if !defined(NRFX_PPIB_INTERCONNECT_00_10_CHANNELS_USED) +/** + * Bitmask that defines PPIB00 and PPIB10 channels that are + * reserved for use outside of the nrfx library. + */ +#define NRFX_PPIB_INTERCONNECT_00_10_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_PPIB_INTERCONNECT_01_20_CHANNELS_USED) +/** + * Bitmask that defines PPIB01 and PPIB20 channels that are + * reserved for use outside of the nrfx library. + */ +#define NRFX_PPIB_INTERCONNECT_01_20_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_PPIB_INTERCONNECT_11_21_CHANNELS_USED) +/** + * Bitmask that defines PPIB11 and PPIB21 channels that are + * reserved for use outside of the nrfx library. + */ +#define NRFX_PPIB_INTERCONNECT_11_21_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_PPIB_INTERCONNECT_22_30_CHANNELS_USED) +/** + * Bitmask that defines PPIB022 and PPIB30 channels that are + * reserved for use outside of the nrfx library. + */ +#define NRFX_PPIB_INTERCONNECT_22_30_CHANNELS_USED 0UL +#endif + +#endif + +#if defined(NRF54L20_ENGA_XXAA) + +#if !defined(NRFX_PPIB_INTERCONNECT_02_03_CHANNELS_USED) +/** + * Bitmask that defines PPIB022 and PPIB30 channels that are + * reserved for use outside of the nrfx library. + */ +#define NRFX_PPIB_INTERCONNECT_02_03_CHANNELS_USED 0UL +#endif + +#if !defined(NRFX_PPIB_INTERCONNECT_04_12_CHANNELS_USED) +/** + * Bitmask that defines PPIB022 and PPIB30 channels that are + * reserved for use outside of the nrfx library. + */ +#define NRFX_PPIB_INTERCONNECT_04_12_CHANNELS_USED 0UL +#endif + +#endif + +#if defined(HALTIUM_XXAA) + +#if !defined(NRFX_PPIB_INTERCONNECT_020_030_CHANNELS_USED) +/** + * Bitmask that defines PPIB020 and PPIB030 channels that are + * reserved for use outside of the nrfx library. + */ +#define NRFX_PPIB_INTERCONNECT_020_030_CHANNELS_USED 0UL +#endif + +#endif + +#endif // !defined(__NRFX_DOXYGEN__) + +#define PPIB_CHANNELS_NUM(idx) (NRFX_CONCAT(PPIB, idx, _NTASKSEVENTS_MAX) + 1UL) +#define PPIB_CHANNELS_MASK(left, right) \ + NRFX_BIT_MASK(NRFX_MIN(PPIB_CHANNELS_NUM(left), PPIB_CHANNELS_NUM(right)) +#define PPIB_CHANNELS_USED(left, right) \ + NRFX_CONCAT(NRFX_PPIB_INTERCONNECT_, left, _, right, _CHANNELS_USED) +#define PPIB_AVAILABLE_CHANNELS_MASK(left, right) \ + ((uint32_t)(PPIB_CHANNELS_MASK(left, right)) & ~(PPIB_CHANNELS_USED(left, right)))) + +/* Structure holding state of the PPIB instance. */ +typedef struct +{ + /**< Bitmap representing channels availability. */ + nrfx_atomic_t allocated_channels; + /**< Bitmap representing available channels. */ + const uint32_t available_channels; +} ppib_control_block_t; + +#define _NRFX_PPIBC_CB_INITIALIZER(left_idx, right_idx) \ + [NRFX_CONCAT(NRFX_PPIB_INTERCONNECT_, left_idx, _, right_idx, _INST_IDX)] = { \ + .allocated_channels = (nrfx_atomic_t)PPIB_AVAILABLE_CHANNELS_MASK(left_idx, right_idx), \ + .available_channels = PPIB_AVAILABLE_CHANNELS_MASK(left_idx, right_idx), \ + }, + +static ppib_control_block_t m_cb[NRFX_PPIB_INTERCONNECT_COUNT] = { +#if defined(NRF54L15_ENGA_XXAA) || defined(NRF54L15_XXAA) || defined(NRF54L20_ENGA_XXAA) +#if NRFX_CHECK(NRFX_PPIB00_ENABLED) && NRFX_CHECK(NRFX_PPIB10_ENABLED) + _NRFX_PPIBC_CB_INITIALIZER(00, 10) +#endif +#if NRFX_CHECK(NRFX_PPIB01_ENABLED) && NRFX_CHECK(NRFX_PPIB20_ENABLED) + _NRFX_PPIBC_CB_INITIALIZER(01, 20) +#endif +#if NRFX_CHECK(NRFX_PPIB11_ENABLED) && NRFX_CHECK(NRFX_PPIB21_ENABLED) + _NRFX_PPIBC_CB_INITIALIZER(11, 21) +#endif +#if NRFX_CHECK(NRFX_PPIB22_ENABLED) && NRFX_CHECK(NRFX_PPIB30_ENABLED) + _NRFX_PPIBC_CB_INITIALIZER(22, 30) +#endif +#endif +#if defined(NRF54L20_ENGA_XXAA) +#if NRFX_CHECK(NRFX_PPIB02_ENABLED) && NRFX_CHECK(NRFX_PPIB03_ENABLED) + _NRFX_PPIBC_CB_INITIALIZER(02, 03) +#endif +#if NRFX_CHECK(NRFX_PPIB04_ENABLED) && NRFX_CHECK(NRFX_PPIB12_ENABLED) + _NRFX_PPIBC_CB_INITIALIZER(04, 12) +#endif +#endif +#if defined(HALTIUM_XXAA) +#if NRFX_CHECK(NRFX_PPIB020_ENABLED) && NRFX_CHECK(NRFX_PPIB030_ENABLED) + _NRFX_PPIBC_CB_INITIALIZER(020, 030) +#endif +#endif +}; + +void nrfx_ppib_free(nrfx_ppib_interconnect_t const * p_instance) +{ + ppib_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + uint32_t mask = p_cb->available_channels & ~p_cb->allocated_channels; + uint8_t channel_idx = 0; + + // Clear all channel configurations + while (mask) + { + if (mask & NRFX_BIT(channel_idx)) + { + nrfx_ppib_channel_free(p_instance, channel_idx); + mask &= ~NRFX_BIT(channel_idx); + } + channel_idx++; + } +} + +nrfx_err_t nrfx_ppib_channel_alloc(nrfx_ppib_interconnect_t const * p_instance, uint8_t * p_channel) +{ + ppib_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + return nrfx_flag32_alloc(&p_cb->allocated_channels, p_channel); +} + +nrfx_err_t nrfx_ppib_channel_free(nrfx_ppib_interconnect_t const * p_instance, uint8_t channel) +{ + ppib_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + if ((p_cb->available_channels & NRFX_BIT(channel)) == 0) + { + return NRFX_ERROR_INVALID_PARAM; + } + + nrf_ppib_subscribe_clear(p_instance->left.p_reg, nrf_ppib_send_task_get(channel)); + nrf_ppib_subscribe_clear(p_instance->right.p_reg, nrf_ppib_send_task_get(channel)); + nrf_ppib_publish_clear(p_instance->left.p_reg, nrf_ppib_receive_event_get(channel)); + nrf_ppib_publish_clear(p_instance->right.p_reg, nrf_ppib_receive_event_get(channel)); + + return nrfx_flag32_free(&p_cb->allocated_channels, channel); +} + +#endif // defined(PPIB_PRESENT) diff --git a/hal/nrf_common.h b/hal/nrf_common.h index 3fe596d25..20ff04bb1 100644 --- a/hal/nrf_common.h +++ b/hal/nrf_common.h @@ -47,7 +47,7 @@ extern "C" { #endif #ifndef NRFX_CONFIG_API_VER_MINOR -#define NRFX_CONFIG_API_VER_MINOR 5 +#define NRFX_CONFIG_API_VER_MINOR 6 #endif #ifndef NRFX_CONFIG_API_VER_MICRO diff --git a/hal/nrf_dppi.h b/hal/nrf_dppi.h index e1d6dfd8b..f87dc3746 100644 --- a/hal/nrf_dppi.h +++ b/hal/nrf_dppi.h @@ -40,6 +40,20 @@ extern "C" { #endif +#if !defined(NRF_DPPIC0) && defined(NRF_DPPIC) +#define NRF_DPPIC0 NRF_DPPIC +#endif + +#if !defined(DPPIC0_CH_NUM) && defined(DPPIC_CH_NUM) && \ + (defined(NRF_DPPIC) || defined(NRF_DPPIC0)) +#define DPPIC0_CH_NUM DPPIC_CH_NUM +#endif + +#if !defined(DPPIC0_GROUP_NUM) && defined(DPPIC_GROUP_NUM) && \ + (defined(NRF_DPPIC) || defined(NRF_DPPIC0)) +#define DPPIC0_GROUP_NUM DPPIC_GROUP_NUM +#endif + /* * Macro for generating if statement code blocks that allow extracting * the number of channels associated with the specific DPPIC instance. diff --git a/hal/nrf_ppib.h b/hal/nrf_ppib.h index cc977c2fd..a7c0a5392 100644 --- a/hal/nrf_ppib.h +++ b/hal/nrf_ppib.h @@ -40,6 +40,18 @@ extern "C" { #endif +/* + * Macro for generating if statement code blocks that allow extracting + * the number of channels associated with the specific PPIB instance. + */ +#define NRF_INTERNAL_PPIB_CHAN_NUM_EXTRACT(chan_num, p_reg) \ + if (0) {} \ + NRFX_FOREACH_PRESENT(PPIB, NRF_INTERNAL_ELSE_IF_EXTRACT_1, (), (), chan_num, _NTASKSEVENTS_MAX + 1, p_reg) \ + else \ + { \ + chan_num = 0; \ + } + /** * @defgroup nrf_ppib_hal PPIB HAL * @{ @@ -173,6 +185,15 @@ typedef enum #pragma GCC diagnostic pop #endif +/** + * @brief Function for getting the total number of available channels for the given PPIB instance. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Number of available channels. + */ +NRF_STATIC_INLINE uint8_t nrf_ppib_channel_number_get(NRF_PPIB_Type const * p_reg); + /** * @brief Function for returning the specified PPIB SEND task. * @@ -182,6 +203,17 @@ typedef enum */ NRF_STATIC_INLINE nrf_ppib_task_t nrf_ppib_send_task_get(uint8_t index); +/** + * @brief Function for getting the address of the specified PPIB task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task. + * + * @return Address of the specified task. + */ +NRF_STATIC_INLINE uint32_t nrf_ppib_task_address_get(NRF_PPIB_Type const * p_reg, + nrf_ppib_task_t task); + /** * @brief Function for returning the specified PPIB RECEIVE event. * @@ -191,12 +223,23 @@ NRF_STATIC_INLINE nrf_ppib_task_t nrf_ppib_send_task_get(uint8_t index); */ NRF_STATIC_INLINE nrf_ppib_event_t nrf_ppib_receive_event_get(uint8_t index); +/** + * @brief Function for getting the address of the specified PPIB event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event. + * + * @return Address of the specified event. + */ +NRF_STATIC_INLINE uint32_t nrf_ppib_event_address_get(NRF_PPIB_Type const * p_reg, + nrf_ppib_event_t event); + /** * @brief Function for setting the subscribe configuration for a given task. * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] task Task for which to set the configuration. - * @param[in] channel DPPI channel through which to subscribe events. + * @param[in] channel PPIB channel through which to subscribe events. */ NRF_STATIC_INLINE void nrf_ppib_subscribe_set(NRF_PPIB_Type * p_reg, nrf_ppib_task_t task, @@ -215,7 +258,7 @@ NRF_STATIC_INLINE void nrf_ppib_subscribe_clear(NRF_PPIB_Type * p_reg, nrf_ppib_ * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] event Event for which to set the configuration. - * @param[in] channel DPPI channel through which to publish the event. + * @param[in] channel PPIB channel through which to publish the event. */ NRF_STATIC_INLINE void nrf_ppib_publish_set(NRF_PPIB_Type * p_reg, nrf_ppib_event_t event, @@ -252,18 +295,39 @@ NRF_STATIC_INLINE bool nrf_ppib_overflow_check(NRF_PPIB_Type const * p_reg, uint #ifndef NRF_DECLARE_ONLY +NRF_STATIC_INLINE uint8_t nrf_ppib_channel_number_get(NRF_PPIB_Type const * p_reg) +{ + (void)p_reg; + + uint8_t chan_num = 0; + NRF_INTERNAL_PPIB_CHAN_NUM_EXTRACT(chan_num, p_reg); + return chan_num; +} + NRF_STATIC_INLINE nrf_ppib_task_t nrf_ppib_send_task_get(uint8_t index) { NRFX_ASSERT(index < NRF_PPIB_TASKS_SEND_COUNT); return (nrf_ppib_task_t)NRFX_OFFSETOF(NRF_PPIB_Type, TASKS_SEND[index]); } +NRF_STATIC_INLINE uint32_t nrf_ppib_task_address_get(NRF_PPIB_Type const * p_reg, + nrf_ppib_task_t task) +{ + return ((uint32_t)p_reg + task); +} + NRF_STATIC_INLINE nrf_ppib_event_t nrf_ppib_receive_event_get(uint8_t index) { NRFX_ASSERT(index < NRF_PPIB_EVENTS_RECEIVE_COUNT); return (nrf_ppib_event_t)NRFX_OFFSETOF(NRF_PPIB_Type, EVENTS_RECEIVE[index]); } +NRF_STATIC_INLINE uint32_t nrf_ppib_event_address_get(NRF_PPIB_Type const * p_reg, + nrf_ppib_event_t event) +{ + return ((uint32_t)p_reg + event); +} + NRF_STATIC_INLINE void nrf_ppib_subscribe_set(NRF_PPIB_Type * p_reg, nrf_ppib_task_t task, uint8_t channel) diff --git a/helpers/nrfx_gppi.h b/helpers/nrfx_gppi.h index 910ae0cd0..0161d14d2 100644 --- a/helpers/nrfx_gppi.h +++ b/helpers/nrfx_gppi.h @@ -111,7 +111,7 @@ typedef enum } nrfx_gppi_task_t; #elif defined(DPPI_PRESENT) -#include +#include #define NRFX_GPPI_GROUP_NUM NRF_DPPI_GROUP_NUM_MAX #define NRFX_GPPI_GROUPS_USED NRFX_DPPI_GROUPS_USED @@ -431,6 +431,37 @@ nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group); nrfx_err_t nrfx_gppi_group_free(nrfx_gppi_channel_group_t group); /** @} */ +#if defined DPPI_PRESENT + +/** + * @brief Function for creating a connection between two edge DPPIs. + * + * This function takes a pair of edge DPPIs and creates an interconnect + * between them using a provided GPPI channel. The GPPI channel must be + * allocated with @ref nrfx_gppi_channel_alloc. + * The configuration of the edge DPPIs is not affected by this function + * or when the GPPI channel is freed with @ref nrfx_gppi_channel_free. + * + * @param[in] channel GPPI channel used to make the connection. + * @param[in] p_src_dppi Instance of the source DPPI. + * @param[in] src_channel Source DPPI channel. + * @param[in] p_dst_dppi Instance of the destination DPPI. + * @param[in] dst_channel Destination DPPI channel. + * + * @retval NRFX_SUCCESS The channel was successfully freed. + * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated or + * is not user-configurable. + * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled. + * @retval NRFX_ERROR_NO_MEM Necessary DPPI resources could not be acquired. + */ +nrfx_err_t nrfx_gppi_edge_connection_setup(uint8_t channel, + nrfx_dppi_t const * p_src_dppi, + uint8_t src_channel, + nrfx_dppi_t const * p_dst_dppi, + uint8_t dst_channel); + +#endif + #ifdef __cplusplus } #endif diff --git a/helpers/nrfx_gppi_dppi.c b/helpers/nrfx_gppi_dppi.c index df4b6eadd..ca1697bc4 100644 --- a/helpers/nrfx_gppi_dppi.c +++ b/helpers/nrfx_gppi_dppi.c @@ -35,6 +35,10 @@ #if NRFX_CHECK(NRFX_DPPI_ENABLED) && (!defined(DPPIC_COUNT) || (DPPIC_COUNT == 1)) #include + +#if NRFX_API_VER_AT_LEAST(3, 8, 0) +static nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0); +#endif #endif #if defined(DPPI_PRESENT) && (defined(NRF53_SERIES) || defined(NRF91_SERIES)) @@ -168,7 +172,11 @@ nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_channel_group_t group nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel) { #if NRFX_CHECK(NRFX_DPPI_ENABLED) && (!defined(DPPIC_COUNT) || (DPPIC_COUNT == 1)) +#if NRFX_API_VER_AT_LEAST(3, 8, 0) + return nrfx_dppi_channel_alloc(&dppi, p_channel); +#else return nrfx_dppi_channel_alloc(p_channel); +#endif #else (void)p_channel; return NRFX_ERROR_NOT_SUPPORTED; @@ -178,7 +186,11 @@ nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel) nrfx_err_t nrfx_gppi_channel_free(uint8_t channel) { #if NRFX_CHECK(NRFX_DPPI_ENABLED) && (!defined(DPPIC_COUNT) || (DPPIC_COUNT == 1)) +#if NRFX_API_VER_AT_LEAST(3, 8, 0) + return nrfx_dppi_channel_free(&dppi, channel); +#else return nrfx_dppi_channel_free(channel); +#endif #else (void)channel; return NRFX_ERROR_NOT_SUPPORTED; @@ -188,7 +200,11 @@ nrfx_err_t nrfx_gppi_channel_free(uint8_t channel) nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group) { #if NRFX_CHECK(NRFX_DPPI_ENABLED) && (!defined(DPPIC_COUNT) || (DPPIC_COUNT == 1)) +#if NRFX_API_VER_AT_LEAST(3, 8, 0) + return nrfx_dppi_group_alloc(&dppi, (nrf_dppi_channel_group_t *)p_group); +#else return nrfx_dppi_group_alloc((nrf_dppi_channel_group_t *)p_group); +#endif #else (void)p_group; return NRFX_ERROR_NOT_SUPPORTED; @@ -198,10 +214,30 @@ nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group) nrfx_err_t nrfx_gppi_group_free(nrfx_gppi_channel_group_t group) { #if NRFX_CHECK(NRFX_DPPI_ENABLED) && (!defined(DPPIC_COUNT) || (DPPIC_COUNT == 1)) +#if NRFX_API_VER_AT_LEAST(3, 8, 0) + return nrfx_dppi_group_free(&dppi, (nrf_dppi_channel_group_t)group); +#else return nrfx_dppi_group_free((nrf_dppi_channel_group_t)group); +#endif #else (void)group; return NRFX_ERROR_NOT_SUPPORTED; #endif } + +nrfx_err_t nrfx_gppi_edge_connection_setup(uint8_t channel, + nrfx_dppi_t const * p_src_dppi, + uint8_t src_channel, + nrfx_dppi_t const * p_dst_dppi, + uint8_t dst_channel) +{ + (void)channel; + (void)p_src_dppi; + (void)src_channel; + (void)p_dst_dppi; + (void)dst_channel; + + return NRFX_SUCCESS; /* No operation as there is only one DPPIC instance. */ +} + #endif // defined(DPPI_PRESENT) && (defined(NRF53_SERIES) || defined(NRF91_SERIES)) diff --git a/helpers/nrfx_gppi_dppi_ppib.c b/helpers/nrfx_gppi_dppi_ppib.c index 3ff5b8dc9..87086e694 100644 --- a/helpers/nrfx_gppi_dppi_ppib.c +++ b/helpers/nrfx_gppi_dppi_ppib.c @@ -33,7 +33,7 @@ #include -#if NRFX_CHECK(NRFX_DPPI_ENABLED) && defined(DPPIC_COUNT) && (DPPIC_COUNT > 1) +#if NRFX_CHECK(NRFX_DPPI_ENABLED) && defined(HALTIUM_XXAA) #include #include @@ -759,4 +759,20 @@ void nrfx_gppi_channels_disable(uint32_t mask) } } +nrfx_err_t nrfx_gppi_edge_connection_setup(uint8_t channel, + nrfx_dppi_t const * p_src_dppi, + uint8_t src_channel, + nrfx_dppi_t const * p_dst_dppi, + uint8_t dst_channel) +{ + (void)channel; + (void)p_src_dppi; + (void)src_channel; + (void)p_dst_dppi; + (void)dst_channel; + + /* Not supported because PPIB connections are configured through UICR. */ + return NRFX_ERROR_NOT_SUPPORTED; +} + #endif // NRFX_DPPI_ENABLED && (DPPIC_COUNT > 1) diff --git a/helpers/nrfx_gppi_dppi_ppib_lumos.c b/helpers/nrfx_gppi_dppi_ppib_lumos.c index dcc3bc8a2..68bb49c55 100644 --- a/helpers/nrfx_gppi_dppi_ppib_lumos.c +++ b/helpers/nrfx_gppi_dppi_ppib_lumos.c @@ -46,12 +46,14 @@ /** @brief Invalid channel number. */ #define NRFX_GPPI_CHANNEL_INVALID UINT8_MAX -#if defined(NRF54L15_ENGA_XXAA) || defined(NRF54L20_ENGA_XXAA) +#if defined(NRF54L15_ENGA_XXAA) #define NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG 0 #else #define NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG 1 #endif +#define INVALID_DPPI_CHANNEL 0xFFUL + static nrfx_atomic_t m_virtual_channels = NRFX_GPPI_PROG_APP_CHANNELS_MASK; static nrfx_err_t dppic_channel_get(nrfx_interconnect_dppic_t * p_dppic, @@ -81,12 +83,20 @@ static nrfx_err_t dppic_virtual_channel_set(nrfx_interconnect_dppic_t * p_dppic, static nrfx_err_t dppic_channel_alloc(nrfx_interconnect_dppic_t * p_dppic, uint8_t * p_channel) { +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) + return nrfx_dppi_channel_alloc(&p_dppic->dppic, p_channel); +#else return nrfx_flag32_alloc(&p_dppic->channels_mask, p_channel); +#endif } static nrfx_err_t dppic_channel_free(nrfx_interconnect_dppic_t * p_dppic, uint8_t channel) { +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) + return nrfx_dppi_channel_free(&p_dppic->dppic, channel); +#else return nrfx_flag32_free(&p_dppic->channels_mask, channel); +#endif } static nrfx_err_t ppib_channel_get(nrfx_interconnect_ppib_t * p_ppib, @@ -108,13 +118,13 @@ static nrfx_err_t ppib_channel_get(nrfx_interconnect_ppib_t * p_ppib, #if NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG static nrfx_err_t ppib_channel_alloc(nrfx_interconnect_ppib_t * p_ppib, uint8_t * p_channel) { - return nrfx_flag32_alloc(&p_ppib->channels_mask, p_channel); + return nrfx_ppib_channel_alloc(&p_ppib->ppib, p_channel); } #endif static nrfx_err_t ppib_channel_free(nrfx_interconnect_ppib_t * p_ppib, uint8_t channel) { - return nrfx_flag32_free(&p_ppib->channels_mask, channel); + return nrfx_ppib_channel_free(&p_ppib->ppib, channel); } static nrfx_err_t ppib_virtual_channel_set(nrfx_interconnect_ppib_t * p_ppib, @@ -136,7 +146,18 @@ static void virtual_channel_enable_set(uint8_t virtual_channel, bool enable) nrfx_err_t err = dppic_channel_get(dppic, virtual_channel, &dppi_channel); if (err == NRFX_SUCCESS) { +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) + if (enable) + { + nrfx_dppi_channel_enable(&dppic->dppic, dppi_channel); + } + else + { + nrfx_dppi_channel_disable(&dppic->dppic, dppi_channel); + } +#else nrfy_dppi_channels_set(dppic->dppic, NRFX_BIT((uint32_t)dppi_channel), enable); +#endif } } } @@ -191,17 +212,17 @@ static nrfx_err_t create_ppib_connection(uint8_t #endif ppib_virtual_channel_set(p_ppib, ppib_channel, virtual_channel); - nrf_ppib_task_t task = nrf_ppib_send_task_get(ppib_channel); - nrf_ppib_event_t event = nrf_ppib_receive_event_get(ppib_channel); + nrf_ppib_task_t task = nrfx_ppib_send_task_get(&p_ppib->ppib.left, ppib_channel); + nrf_ppib_event_t event = nrfx_ppib_receive_event_get(&p_ppib->ppib.right, ppib_channel); if (p_path->ppib_inverted == false) { - nrf_ppib_subscribe_set(p_ppib->p_ppib1, task, src_dppi_channel); - nrf_ppib_publish_set(p_ppib->p_ppib2, event, dst_dppi_channel); + nrfx_ppib_subscribe_set(&p_ppib->ppib.left, task, src_dppi_channel); + nrfx_ppib_publish_set(&p_ppib->ppib.right, event, dst_dppi_channel); } else { - nrf_ppib_subscribe_set(p_ppib->p_ppib2, task, src_dppi_channel); - nrf_ppib_publish_set(p_ppib->p_ppib1, event, dst_dppi_channel); + nrfx_ppib_subscribe_set(&p_ppib->ppib.right, task, src_dppi_channel); + nrfx_ppib_publish_set(&p_ppib->ppib.left, event, dst_dppi_channel); } return NRFX_SUCCESS; } @@ -216,7 +237,11 @@ static nrfx_err_t clear_virtual_channel_path(uint8_t virtual_channel) nrfx_err_t err = dppic_channel_get(dppic, virtual_channel, &dppi_channel); if (err == NRFX_SUCCESS) { +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) + nrfx_dppi_channel_disable(&dppic->dppic, dppi_channel); +#else nrfy_dppi_channels_set(dppic->dppic, NRFX_BIT((uint32_t)dppi_channel), false); +#endif err = dppic_channel_free(dppic, dppi_channel); if (err != NRFX_SUCCESS) @@ -242,14 +267,15 @@ static nrfx_err_t clear_virtual_channel_path(uint8_t virtual_channel) nrfx_err_t err = ppib_channel_get(p_ppib, virtual_channel, &ppib_channel); if (err == NRFX_SUCCESS) { - nrf_ppib_task_t task = nrf_ppib_send_task_get((uint32_t)ppib_channel); - nrf_ppib_event_t event = nrf_ppib_receive_event_get((uint32_t)ppib_channel); + nrf_ppib_task_t task = nrfx_ppib_send_task_get(&p_ppib->ppib.left, ppib_channel); + nrf_ppib_event_t event = nrfx_ppib_receive_event_get(&p_ppib->ppib.right, + ppib_channel); - nrf_ppib_subscribe_clear(p_ppib->p_ppib1, task); - nrf_ppib_subscribe_clear(p_ppib->p_ppib2, task); + nrfx_ppib_subscribe_clear(&p_ppib->ppib.left, task); + nrfx_ppib_subscribe_clear(&p_ppib->ppib.right, task); - nrf_ppib_publish_clear(p_ppib->p_ppib1, event); - nrf_ppib_publish_clear(p_ppib->p_ppib2, event); + nrfx_ppib_publish_clear(&p_ppib->ppib.left, event); + nrfx_ppib_publish_clear(&p_ppib->ppib.right, event); err = ppib_channel_free(p_ppib, ppib_channel); if (err != NRFX_SUCCESS) @@ -268,133 +294,70 @@ static nrfx_err_t clear_virtual_channel_path(uint8_t virtual_channel) return NRFX_SUCCESS; } -nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel) +static nrfx_err_t gppi_dppi_connection_setup(uint8_t virtual_channel, + nrf_apb_index_t src_domain, + uint8_t * p_src_dppi_channel, + nrf_apb_index_t dst_domain, + uint8_t * p_dst_dppi_channel) { - init(); - return nrfx_flag32_alloc(&m_virtual_channels, p_channel); -} - -void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep) -{ - (void)channel; - (void)eep; - // `tep` is also needed to decide whether `main_apb` is to be used. - NRFX_ASSERT(false); -} - -void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep) -{ - (void)channel; - (void)tep; - // `eep` is also needed to decide whether `main_apb` is to be used. - NRFX_ASSERT(false); -} + nrfx_err_t err = NRFX_SUCCESS; + NRFX_ASSERT(src_domain); + NRFX_ASSERT(dst_domain); + NRFX_ASSERT(p_src_dppi_channel); + NRFX_ASSERT(p_dst_dppi_channel); -void nrfx_gppi_event_endpoint_clear(uint8_t channel, uint32_t eep) -{ - (void)channel; - (void)eep; - // `tep` is also needed to decide whether `main_apb` is to be used. - NRFX_ASSERT(false); -} + uint8_t src_dppi_channel = *p_src_dppi_channel; + uint8_t dst_dppi_channel = *p_dst_dppi_channel; -void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep) -{ - (void)channel; - (void)tep; - // `eep` is also needed to decide whether `main_apb` is to be used. - NRFX_ASSERT(false); -} + nrfx_interconnect_dppic_t * p_src_dppic = nrfx_interconnect_dppic_get(src_domain); + nrfx_interconnect_dppic_t * p_dst_dppic = nrfx_interconnect_dppic_get(dst_domain); -void nrfx_gppi_fork_endpoint_setup(uint8_t channel, uint32_t fork_tep) -{ - for (uint8_t i = 0; i < NRFX_INTERCONNECT_DPPIC_COUNT; i++) + nrfx_interconnect_dppic_to_dppic_path_t path = { - nrfx_interconnect_dppic_t * dppic = nrfx_interconnect_dppic_at_index_get(i); - uint8_t dppi_channel; - nrfx_err_t err = dppic_channel_get(dppic, channel, &dppi_channel); - if (err == NRFX_SUCCESS) - { - NRF_DPPI_ENDPOINT_SETUP(fork_tep, (uint32_t)dppi_channel); - return; - } - } - NRFX_ASSERT(false); -} + .src_dppic = p_src_dppic, + .dst_dppic = p_dst_dppic, + }; -void nrfx_gppi_fork_endpoint_clear(uint8_t channel, uint32_t fork_tep) -{ - for (uint8_t i = 0; i < NRFX_INTERCONNECT_DPPIC_COUNT; i++) + /* Both channels must be either valid or not. */ + if ((src_dppi_channel == INVALID_DPPI_CHANNEL && dst_dppi_channel != INVALID_DPPI_CHANNEL) + || (src_dppi_channel != INVALID_DPPI_CHANNEL && dst_dppi_channel == INVALID_DPPI_CHANNEL)) { - nrfx_interconnect_dppic_t * dppic = nrfx_interconnect_dppic_at_index_get(i); - uint8_t dppi_channel; - nrfx_err_t err = dppic_channel_get(dppic, channel, &dppi_channel); - if (err == NRFX_SUCCESS) - { - NRF_DPPI_ENDPOINT_CLEAR(fork_tep); - return; - } + clear_virtual_channel_path(virtual_channel); + NRFX_ASSERT(false); + return NRFX_ERROR_INVALID_PARAM; } - NRFX_ASSERT(false); -} - -void nrfx_gppi_channel_endpoints_setup(uint8_t channel, uint32_t eep, uint32_t tep) -{ - nrfx_err_t err = NRFX_SUCCESS; - nrf_apb_index_t src_domain = nrfx_interconnect_apb_index_get(eep); - nrf_apb_index_t dst_domain = nrfx_interconnect_apb_index_get(tep); - NRFX_ASSERT(src_domain); - NRFX_ASSERT(dst_domain); - - uint8_t src_dppi_channel; - uint8_t dst_dppi_channel; - - if (src_domain == dst_domain) +#if !NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG + /* Without dynamic PPIB configs both source and destination must have the same number. */ + if (src_dppi_channel != dst_dppi_channel) { - nrfx_interconnect_dppic_t * dppic = nrfx_interconnect_dppic_get(src_domain); - if (dppic_channel_alloc(dppic, &src_dppi_channel) == NRFX_SUCCESS) - { - dst_dppi_channel = src_dppi_channel; - dppic_virtual_channel_set(dppic, src_dppi_channel, channel); - } - else - { - clear_virtual_channel_path(channel); - NRFX_ASSERT(false); - return; - } + clear_virtual_channel_path(virtual_channel); + NRFX_ASSERT(false); + return NRFX_ERROR_INVALID_PARAM; } - else - { - nrfx_interconnect_dppic_t * p_src_dppic = nrfx_interconnect_dppic_get(src_domain); - nrfx_interconnect_dppic_t * p_dst_dppic = nrfx_interconnect_dppic_get(dst_domain); - - nrfx_interconnect_dppic_to_dppic_path_t path = - { - .src_dppic = p_src_dppic, - .dst_dppic = p_dst_dppic, - }; +#endif - if (nrfx_interconnect_direct_connection_check(&path)) + if (nrfx_interconnect_direct_connection_check(&path)) + { + if (src_dppi_channel == INVALID_DPPI_CHANNEL) { #if !NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG nrfx_atomic_t possible_mask = path.src_dppic->channels_mask; possible_mask &= path.dst_dppic->channels_mask; - possible_mask &= path.ppib->channels_mask; + possible_mask &= + NRFX_BIT_MASK(nrf_ppib_channel_number_get(path.ppib->ppib.left.p_reg)); uint8_t common_channel; nrfx_flag32_alloc(&possible_mask, &common_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } path.src_dppic->channels_mask &= ~NRFX_BIT(common_channel); path.dst_dppic->channels_mask &= ~NRFX_BIT(common_channel); - path.ppib->channels_mask &= ~NRFX_BIT(common_channel); src_dppi_channel = common_channel; dst_dppi_channel = common_channel; @@ -402,81 +365,80 @@ void nrfx_gppi_channel_endpoints_setup(uint8_t channel, uint32_t eep, uint32_t t err = dppic_channel_alloc(p_src_dppic, &src_dppi_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } -#endif - dppic_virtual_channel_set(p_src_dppic, src_dppi_channel, channel); -#if NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG + err = dppic_channel_alloc(p_dst_dppic, &dst_dppi_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } #endif - dppic_virtual_channel_set(p_dst_dppic, dst_dppi_channel, channel); + dppic_virtual_channel_set(p_src_dppic, src_dppi_channel, virtual_channel); + dppic_virtual_channel_set(p_dst_dppic, dst_dppi_channel, virtual_channel); + } - err = create_ppib_connection(channel, - &path, - src_dppi_channel, - dst_dppi_channel); - if (err != NRFX_SUCCESS) - { - clear_virtual_channel_path(channel); - NRFX_ASSERT(false); - return; - } + err = create_ppib_connection(virtual_channel, + &path, + src_dppi_channel, + dst_dppi_channel); + if (err != NRFX_SUCCESS) + { + clear_virtual_channel_path(virtual_channel); + NRFX_ASSERT(false); + return err; } - else + } + else + { + nrfx_interconnect_dppic_t * p_main_dppic = nrfx_interconnect_dppic_main_get(); + p_src_dppic = nrfx_interconnect_dppic_get(src_domain); + p_dst_dppic = nrfx_interconnect_dppic_get(dst_domain); + + nrfx_interconnect_dppic_to_dppic_path_t path_src_to_main = { - nrfx_interconnect_dppic_t * p_main_dppic = nrfx_interconnect_dppic_main_get(); - p_src_dppic = nrfx_interconnect_dppic_get(src_domain); - p_dst_dppic = nrfx_interconnect_dppic_get(dst_domain); + .src_dppic = p_src_dppic, + .dst_dppic = p_main_dppic, + }; - nrfx_interconnect_dppic_to_dppic_path_t path_src_to_main = - { - .src_dppic = p_src_dppic, - .dst_dppic = p_main_dppic, - }; + nrfx_interconnect_dppic_to_dppic_path_t path_main_to_dst = + { + .src_dppic = p_main_dppic, + .dst_dppic = p_dst_dppic, + }; - nrfx_interconnect_dppic_to_dppic_path_t path_main_to_dst = - { - .src_dppic = p_main_dppic, - .dst_dppic = p_dst_dppic, - }; + if (nrfx_interconnect_direct_connection_check(&path_src_to_main) && + nrfx_interconnect_direct_connection_check(&path_main_to_dst)) + { + uint8_t main_dppi_channel; - if (nrfx_interconnect_direct_connection_check(&path_src_to_main) && - nrfx_interconnect_direct_connection_check(&path_main_to_dst)) + if (src_dppi_channel == INVALID_DPPI_CHANNEL) { - uint8_t main_dppi_channel; #if !NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG nrfx_atomic_t possible_mask = p_src_dppic->channels_mask; possible_mask &= p_main_dppic->channels_mask; possible_mask &= p_dst_dppic->channels_mask; - possible_mask &= path_src_to_main.ppib->channels_mask; - possible_mask &= path_main_to_dst.ppib->channels_mask; + possible_mask &= NRFX_BIT_MASK( + nrf_ppib_channel_number_get(path_src_to_main.ppib->ppib.left.p_reg)); + possible_mask &= NRFX_BIT_MASK( + nrf_ppib_channel_number_get(path_main_to_dst.ppib->ppib.left.p_reg)); uint8_t common_channel; nrfx_flag32_alloc(&possible_mask, &common_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } p_src_dppic->channels_mask &= ~NRFX_BIT(common_channel); p_main_dppic->channels_mask &= ~NRFX_BIT(common_channel); p_dst_dppic->channels_mask &= ~NRFX_BIT(common_channel); - path_src_to_main.ppib->channels_mask &= ~NRFX_BIT(common_channel); - path_main_to_dst.ppib->channels_mask &= ~NRFX_BIT(common_channel); - - dppic_virtual_channel_set(p_src_dppic, common_channel, channel); - dppic_virtual_channel_set(p_main_dppic, common_channel, channel); - dppic_virtual_channel_set(p_dst_dppic, common_channel, channel); src_dppi_channel = common_channel; dst_dppi_channel = common_channel; @@ -485,69 +447,218 @@ void nrfx_gppi_channel_endpoints_setup(uint8_t channel, uint32_t eep, uint32_t t err = dppic_channel_alloc(p_src_dppic, &src_dppi_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } -#endif - dppic_virtual_channel_set(p_src_dppic, src_dppi_channel, channel); -#if NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG + err = dppic_channel_alloc(p_main_dppic, &main_dppi_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } -#endif - dppic_virtual_channel_set(p_main_dppic, main_dppi_channel, channel); -#if NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG + err = dppic_channel_alloc(p_dst_dppic, &dst_dppi_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } #endif - dppic_virtual_channel_set(p_dst_dppic, dst_dppi_channel, channel); + dppic_virtual_channel_set(p_src_dppic, src_dppi_channel, virtual_channel); + dppic_virtual_channel_set(p_dst_dppic, dst_dppi_channel, virtual_channel); + } + else + { +#if !NRFX_GPPI_PPIB_HAS_DYNAMIC_CONFIG + nrfx_atomic_t possible_mask = NRFX_BIT(src_dppi_channel); + possible_mask &= p_main_dppic->channels_mask; + possible_mask &= NRFX_BIT(dst_dppi_channel); + possible_mask &= NRFX_BIT_MASK( + nrf_ppib_channel_number_get(path_src_to_main.ppib->ppib.left.p_reg)); + possible_mask &= NRFX_BIT_MASK( + nrf_ppib_channel_number_get(path_main_to_dst.ppib->ppib.left.p_reg)); - err = create_ppib_connection(channel, - &path_src_to_main , - src_dppi_channel, - main_dppi_channel); + uint8_t common_channel; + nrfx_flag32_alloc(&possible_mask, &common_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } - err = create_ppib_connection(channel, - &path_main_to_dst, - main_dppi_channel, - dst_dppi_channel); + p_src_dppic->channels_mask &= ~NRFX_BIT(common_channel); + p_main_dppic->channels_mask &= ~NRFX_BIT(common_channel); + p_dst_dppic->channels_mask &= ~NRFX_BIT(common_channel); + + main_dppi_channel = common_channel; +#else + err = dppic_channel_alloc(p_main_dppic, &main_dppi_channel); if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } +#endif } - else + + dppic_virtual_channel_set(p_main_dppic, main_dppi_channel, virtual_channel); + + err = create_ppib_connection(virtual_channel, + &path_src_to_main , + src_dppi_channel, + main_dppi_channel); + if (err != NRFX_SUCCESS) { - clear_virtual_channel_path(channel); + clear_virtual_channel_path(virtual_channel); NRFX_ASSERT(false); - return; + return err; } + + err = create_ppib_connection(virtual_channel, + &path_main_to_dst, + main_dppi_channel, + dst_dppi_channel); + if (err != NRFX_SUCCESS) + { + clear_virtual_channel_path(virtual_channel); + NRFX_ASSERT(false); + return err; + } + } + else + { + clear_virtual_channel_path(virtual_channel); + NRFX_ASSERT(false); + return err; + } + } + + *p_src_dppi_channel = src_dppi_channel; + *p_dst_dppi_channel = dst_dppi_channel; + + return err; +} + +nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel) +{ + init(); + return nrfx_flag32_alloc(&m_virtual_channels, p_channel); +} + +void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep) +{ + (void)channel; + (void)eep; + // `tep` is also needed to decide whether `main_apb` is to be used. + NRFX_ASSERT(false); +} + +void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep) +{ + (void)channel; + (void)tep; + // `eep` is also needed to decide whether `main_apb` is to be used. + NRFX_ASSERT(false); +} + +void nrfx_gppi_event_endpoint_clear(uint8_t channel, uint32_t eep) +{ + (void)channel; + (void)eep; + // `tep` is also needed to decide whether `main_apb` is to be used. + NRFX_ASSERT(false); +} + +void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep) +{ + (void)channel; + (void)tep; + // `eep` is also needed to decide whether `main_apb` is to be used. + NRFX_ASSERT(false); +} + +void nrfx_gppi_fork_endpoint_setup(uint8_t channel, uint32_t fork_tep) +{ + for (uint8_t i = 0; i < NRFX_INTERCONNECT_DPPIC_COUNT; i++) + { + nrfx_interconnect_dppic_t * dppic = nrfx_interconnect_dppic_at_index_get(i); + uint8_t dppi_channel; + nrfx_err_t err = dppic_channel_get(dppic, channel, &dppi_channel); + if (err == NRFX_SUCCESS) + { + NRF_DPPI_ENDPOINT_SETUP(fork_tep, (uint32_t)dppi_channel); + return; } } + NRFX_ASSERT(false); +} - if (err == NRFX_SUCCESS) +void nrfx_gppi_fork_endpoint_clear(uint8_t channel, uint32_t fork_tep) +{ + for (uint8_t i = 0; i < NRFX_INTERCONNECT_DPPIC_COUNT; i++) { - NRF_DPPI_ENDPOINT_SETUP(eep, src_dppi_channel); - NRF_DPPI_ENDPOINT_SETUP(tep, dst_dppi_channel); + nrfx_interconnect_dppic_t * dppic = nrfx_interconnect_dppic_at_index_get(i); + uint8_t dppi_channel; + nrfx_err_t err = dppic_channel_get(dppic, channel, &dppi_channel); + if (err == NRFX_SUCCESS) + { + NRF_DPPI_ENDPOINT_CLEAR(fork_tep); + return; + } } + NRFX_ASSERT(false); +} + +void nrfx_gppi_channel_endpoints_setup(uint8_t channel, uint32_t eep, uint32_t tep) +{ + nrfx_err_t err = NRFX_SUCCESS; + nrf_apb_index_t src_domain = nrfx_interconnect_apb_index_get(eep); + nrf_apb_index_t dst_domain = nrfx_interconnect_apb_index_get(tep); + + NRFX_ASSERT(src_domain); + NRFX_ASSERT(dst_domain); + + uint8_t src_dppi_channel = INVALID_DPPI_CHANNEL; + uint8_t dst_dppi_channel = INVALID_DPPI_CHANNEL; + + if (src_domain == dst_domain) + { + nrfx_interconnect_dppic_t * dppic = nrfx_interconnect_dppic_get(src_domain); + if (dppic_channel_alloc(dppic, &src_dppi_channel) == NRFX_SUCCESS) + { + dst_dppi_channel = src_dppi_channel; + dppic_virtual_channel_set(dppic, src_dppi_channel, channel); + } + else + { + clear_virtual_channel_path(channel); + NRFX_ASSERT(false); + return; + } + } + else + { + err = gppi_dppi_connection_setup(channel, + src_domain, + &src_dppi_channel, + dst_domain, + &dst_dppi_channel); + } + + if (err != NRFX_SUCCESS) + { + NRFX_ASSERT(false); + return; + } + + NRF_DPPI_ENDPOINT_SETUP(eep, src_dppi_channel); + NRF_DPPI_ENDPOINT_SETUP(tep, dst_dppi_channel); } void nrfx_gppi_channel_endpoints_clear(uint8_t channel, uint32_t eep, uint32_t tep) @@ -581,7 +692,13 @@ bool nrfx_gppi_channel_check(uint8_t channel) nrfx_err_t err = dppic_channel_get(dppic, channel, &dppi_channel); if (err == NRFX_SUCCESS) { - if (nrf_dppi_channel_check(dppic->dppic, (uint32_t)dppi_channel) == false) + NRF_DPPIC_Type *p_reg; +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) + p_reg = dppic->dppic.p_reg; +#else + p_reg = dppic->dppic; +#endif + if (nrf_dppi_channel_check(p_reg, (uint32_t)dppi_channel) == false) { return false; } @@ -626,4 +743,24 @@ void nrfx_gppi_channels_disable(uint32_t mask) } } +nrfx_err_t nrfx_gppi_edge_connection_setup(uint8_t channel, + nrfx_dppi_t const * p_src_dppi, + uint8_t src_channel, + nrfx_dppi_t const * p_dst_dppi, + uint8_t dst_channel) +{ + nrf_apb_index_t src_domain = nrfx_interconnect_apb_index_get((uint32_t)p_src_dppi->p_reg); + nrf_apb_index_t dst_domain = nrfx_interconnect_apb_index_get((uint32_t)p_dst_dppi->p_reg); + + uint8_t src_dppi_channel = src_channel; + uint8_t dst_dppi_channel = dst_channel; + + if (p_src_dppi == p_dst_dppi) + { + return NRFX_SUCCESS; /* No OP */ + } + + return gppi_dppi_connection_setup(channel, src_domain, &src_dppi_channel, dst_domain, &dst_dppi_channel); +} + #endif // defined(LUMOS_XXAA) diff --git a/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.c b/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.c index 685aeeae6..a74855e79 100644 --- a/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.c +++ b/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.c @@ -96,7 +96,13 @@ bool nrfx_interconnect_direct_connection_check(nrfx_interconnect_dppic_to_dppic_ for (uint8_t i = 0; i < NRFX_INTERCONNECT_DPPIC_PPIB_COUNT; i++) { - if (interconnect_dppic_ppib[i].dppic != p_path->src_dppic->dppic) + NRF_DPPIC_Type *p_reg; +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) + p_reg = p_path->src_dppic->dppic.p_reg; +#else + p_reg = p_path->src_dppic->dppic; +#endif + if (interconnect_dppic_ppib[i].dppic != p_reg) { continue; } @@ -105,18 +111,18 @@ bool nrfx_interconnect_direct_connection_check(nrfx_interconnect_dppic_to_dppic_ { NRF_PPIB_Type * p_dst_ppib = NULL; - if (interconnect_ppib[j].p_ppib1 == interconnect_dppic_ppib[i].ppib) + if (interconnect_ppib[j].ppib.left.p_reg == interconnect_dppic_ppib[i].ppib) { p_path->ppib = &interconnect_ppib[j]; p_path->ppib_inverted = false; - p_dst_ppib = interconnect_ppib[j].p_ppib2; + p_dst_ppib = interconnect_ppib[j].ppib.right.p_reg; } - if (interconnect_ppib[j].p_ppib2 == interconnect_dppic_ppib[i].ppib) + if (interconnect_ppib[j].ppib.right.p_reg == interconnect_dppic_ppib[i].ppib) { p_path->ppib = &interconnect_ppib[j]; p_path->ppib_inverted = true; - p_dst_ppib = interconnect_ppib[j].p_ppib1; + p_dst_ppib = interconnect_ppib[j].ppib.left.p_reg; } if (p_dst_ppib == NULL) @@ -126,8 +132,14 @@ bool nrfx_interconnect_direct_connection_check(nrfx_interconnect_dppic_to_dppic_ for (uint8_t k = 0; k < NRFX_ARRAY_SIZE(interconnect_dppic_ppib); k++) { + NRF_DPPIC_Type *p_dst_reg; +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) + p_dst_reg = p_path->dst_dppic->dppic.p_reg; +#else + p_dst_reg = p_path->dst_dppic->dppic; +#endif if ((interconnect_dppic_ppib[k].ppib == p_dst_ppib) && - (interconnect_dppic_ppib[k].dppic == p_path->dst_dppic->dppic)) + (interconnect_dppic_ppib[k].dppic == p_dst_reg)) { return true; } @@ -145,7 +157,13 @@ nrf_apb_index_t nrfx_interconnect_apb_index_get(uint32_t addr) nrfx_interconnect_dppic_t const * p_dppic = &interconnect_dppic[i]; uint8_t bus_address_area = nrf_address_bus_get(addr, p_dppic->apb_size); - if (bus_address_area == nrf_address_bus_get((uint32_t)p_dppic->dppic, p_dppic->apb_size)) + NRF_DPPIC_Type *p_reg; +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) + p_reg = p_dppic->dppic.p_reg; +#else + p_reg = p_dppic->dppic; +#endif + if (bus_address_area == nrf_address_bus_get((uint32_t)p_reg, p_dppic->apb_size)) { return (nrf_apb_index_t)bus_address_area; } diff --git a/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.h b/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.h index 8351aed9e..fa8a44991 100644 --- a/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.h +++ b/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.h @@ -34,7 +34,8 @@ #ifndef NRFX_INTERCONNECT_DPPIC_PPIB_H__ #define NRFX_INTERCONNECT_DPPIC_PPIB_H__ -#include +#include +#include #ifdef __cplusplus extern "C" { @@ -50,10 +51,8 @@ extern "C" { /** @brief PPIB interconnect properties structure. */ typedef struct { - NRF_PPIB_Type * p_ppib1; ///< First PPIB peripheral. - NRF_PPIB_Type * p_ppib2; ///< Second PPIB peripheral. - nrfx_atomic_t channels_mask; ///< Mask of configurable channels between the first and the second PPIB instance. - uint8_t allocate_flag[PPIB_CHANNEL_MAX_COUNT]; ///< Virtual channels assigned to each of PPIB channels. + nrfx_ppib_interconnect_t ppib; ///< Interconnect instance. + uint8_t allocate_flag[PPIB_CHANNEL_MAX_COUNT]; ///< Virtual channels assigned to each of PPIB channels. } nrfx_interconnect_ppib_t; /** @brief DPPIC and PPIB interconnect properties structure. */ @@ -67,8 +66,12 @@ typedef struct typedef struct { uint8_t apb_index; ///< APB index to which DPPIC belongs. +#if (NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA)) || defined(__NRFX_DOXYGEN__) + nrfx_dppi_t dppic; ///< DPPIC peripheral that belongs to a given domain. +#else NRF_DPPIC_Type * dppic; ///< DPPIC peripheral that belongs to a given domain. nrfx_atomic_t channels_mask; ///< Mask of configurable DPPIC channels. +#endif uint8_t allocate_flag[NRF_DPPI_CH_NUM_MAX]; ///< Virtual channels assigned to each of DPPIC channels. uint32_t apb_size; ///< Size of APB. } nrfx_interconnect_dppic_t; @@ -118,7 +121,7 @@ nrfx_interconnect_ppib_t * nrfx_interconnect_ppib_at_index_get(uint8_t index); /** * @brief Function for checking if path from source DPPIC to destination DPPIC exists. - * + * * @param[in] p_path Pointer to path from source DPPIC to destination DPPIC. * When path exists, @p p_path is filled with PPIB information. * @@ -128,7 +131,7 @@ bool nrfx_interconnect_direct_connection_check(nrfx_interconnect_dppic_to_dppic_ /** * @brief Function for getting @p nrf_apb_index_t from memory address. - * + * * @param[in] addr Memory address. * * @return APB index. diff --git a/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib_lumos.h b/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib_lumos.h index a3bc7b79d..9ff3dab9f 100644 --- a/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib_lumos.h +++ b/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib_lumos.h @@ -35,6 +35,7 @@ #define NRFX_INTERCONNECT_DPPIC_PPIB_LUMOS_H__ #include +#include #ifdef __cplusplus extern "C" { @@ -45,12 +46,17 @@ extern "C" { #define NRFX_INTERCONNECT_PPIB(FIRST_PPIB_INDEX, SECOND_PPIB_INDEX) \ { \ - .p_ppib1 = NRFX_CONCAT(NRF_PPIB, FIRST_PPIB_INDEX), \ - .p_ppib2 = NRFX_CONCAT(NRF_PPIB, SECOND_PPIB_INDEX), \ - .channels_mask = NRFX_BIT_MASK(NRFX_MIN(NRFX_INTERCONNECT_PPIB_TASKS_GET(FIRST_PPIB_INDEX), \ - NRFX_INTERCONNECT_PPIB_TASKS_GET(SECOND_PPIB_INDEX))), \ + .ppib = NRFX_PPIB_INTERCONNECT_INSTANCE(FIRST_PPIB_INDEX, SECOND_PPIB_INDEX), \ } +#if NRFX_API_VER_AT_LEAST(3, 8, 0) && !defined(NRF54L15_ENGA_XXAA) +#define DPPI_INSTANCE(idx) .dppic = NRFX_DPPI_INSTANCE(idx) +#else +#define DPPI_INSTANCE(idx) \ + .dppic = NRFX_CONCAT(NRF_DPPIC, idx), \ + .channels_mask = NRFX_BIT_MASK(NRFX_CONCAT(DPPIC, idx, _CH_NUM)) +#endif + #if (defined (NRF54L15_XXAA) || defined (NRF54L15_ENGA_XXAA)) #define NRFX_INTERCONNECT_PPIB_MAP \ @@ -58,7 +64,7 @@ extern "C" { NRFX_INTERCONNECT_PPIB(00, 10), \ NRFX_INTERCONNECT_PPIB(11, 21), \ NRFX_INTERCONNECT_PPIB(22, 30), \ - NRFX_INTERCONNECT_PPIB(20, 01), \ + NRFX_INTERCONNECT_PPIB(01, 20), \ } #define NRFX_INTERCONNECT_DPPIC_PPIB_MAP \ @@ -97,32 +103,28 @@ extern "C" { }, \ } -#define NRFX_INTERCONNECT_DPPIC_MAP \ -{ \ - { \ - .apb_index = NRF_APB_INDEX_MCU, \ - .dppic = NRF_DPPIC00, \ - .channels_mask = NRFX_BIT_MASK(DPPIC00_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ - { \ - .apb_index = NRF_APB_INDEX_RADIO, \ - .dppic = NRF_DPPIC10, \ - .channels_mask = NRFX_BIT_MASK(DPPIC10_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ - { \ - .apb_index = NRF_APB_INDEX_PERI, \ - .dppic = NRF_DPPIC20, \ - .channels_mask = NRFX_BIT_MASK(DPPIC20_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ - { \ - .apb_index = NRF_APB_INDEX_LP, \ - .dppic = NRF_DPPIC30, \ - .channels_mask = NRFX_BIT_MASK(DPPIC30_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ +#define NRFX_INTERCONNECT_DPPIC_MAP \ +{ \ + { \ + .apb_index = NRF_APB_INDEX_MCU, \ + DPPI_INSTANCE(00), \ + .apb_size = 0x40000 \ + }, \ + { \ + .apb_index = NRF_APB_INDEX_RADIO, \ + DPPI_INSTANCE(10), \ + .apb_size = 0x40000 \ + }, \ + { \ + .apb_index = NRF_APB_INDEX_PERI, \ + DPPI_INSTANCE(20), \ + .apb_size = 0x40000 \ + }, \ + { \ + .apb_index = NRF_APB_INDEX_LP, \ + DPPI_INSTANCE(30), \ + .apb_size = 0x40000 \ + }, \ } #elif defined (NRF54L20_ENGA_XXAA) @@ -130,11 +132,11 @@ extern "C" { #define NRFX_INTERCONNECT_PPIB_MAP \ { \ NRFX_INTERCONNECT_PPIB(00, 10), \ - NRFX_INTERCONNECT_PPIB(03, 02), \ + NRFX_INTERCONNECT_PPIB(02, 03), \ NRFX_INTERCONNECT_PPIB(04, 12), \ NRFX_INTERCONNECT_PPIB(11, 21), \ NRFX_INTERCONNECT_PPIB(22, 30), \ - NRFX_INTERCONNECT_PPIB(20, 01), \ + NRFX_INTERCONNECT_PPIB(01, 20), \ } #define NRFX_INTERCONNECT_DPPIC_PPIB_MAP \ @@ -189,38 +191,33 @@ extern "C" { }, \ } -#define NRFX_INTERCONNECT_DPPIC_MAP \ -{ \ - { \ - .apb_index = 0, \ - .dppic = NRF_DPPIC01, \ - .channels_mask = NRFX_BIT_MASK(DPPIC01_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ - { \ - .apb_index = NRF_APB_INDEX_MCU, \ - .dppic = NRF_DPPIC00, \ - .channels_mask = NRFX_BIT_MASK(DPPIC00_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ - { \ - .apb_index = NRF_APB_INDEX_RADIO, \ - .dppic = NRF_DPPIC10, \ - .channels_mask = NRFX_BIT_MASK(DPPIC10_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ - { \ - .apb_index = NRF_APB_INDEX_PERI, \ - .dppic = NRF_DPPIC20, \ - .channels_mask = NRFX_BIT_MASK(DPPIC20_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ - { \ - .apb_index = NRF_APB_INDEX_LP, \ - .dppic = NRF_DPPIC30, \ - .channels_mask = NRFX_BIT_MASK(DPPIC30_CH_NUM), \ - .apb_size = 0x40000 \ - }, \ +#define NRFX_INTERCONNECT_DPPIC_MAP \ +{ \ + { \ + .apb_index = 0, \ + DPPI_INSTANCE(01), \ + .apb_size = 0x40000 \ + }, \ + { \ + .apb_index = NRF_APB_INDEX_MCU, \ + DPPI_INSTANCE(00), \ + .apb_size = 0x40000 \ + }, \ + { \ + .apb_index = NRF_APB_INDEX_RADIO, \ + DPPI_INSTANCE(10), \ + .apb_size = 0x40000 \ + }, \ + { \ + .apb_index = NRF_APB_INDEX_PERI, \ + DPPI_INSTANCE(20), \ + .apb_size = 0x40000 \ + }, \ + { \ + .apb_index = NRF_APB_INDEX_LP, \ + DPPI_INSTANCE(30), \ + .apb_size = 0x40000 \ + }, \ } #endif diff --git a/templates/nrfx_config_common.h b/templates/nrfx_config_common.h index 496e379f2..e371142e4 100644 --- a/templates/nrfx_config_common.h +++ b/templates/nrfx_config_common.h @@ -45,7 +45,7 @@ /** @brief Symbol specifying minor version of the nrfx API to be used. */ #ifndef NRFX_CONFIG_API_VER_MINOR -#define NRFX_CONFIG_API_VER_MINOR 5 +#define NRFX_CONFIG_API_VER_MINOR 6 #endif /** @brief Symbol specifying micro version of the nrfx API to be used. */ diff --git a/templates/nrfx_config_nrf54h20_application.h b/templates/nrfx_config_nrf54h20_application.h index e439eaa62..459c2fefc 100644 --- a/templates/nrfx_config_nrf54h20_application.h +++ b/templates/nrfx_config_nrf54h20_application.h @@ -289,6 +289,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_enga_application.h b/templates/nrfx_config_nrf54h20_enga_application.h index 00f26f4c5..99506d5ae 100644 --- a/templates/nrfx_config_nrf54h20_enga_application.h +++ b/templates/nrfx_config_nrf54h20_enga_application.h @@ -289,6 +289,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_GPIOTE_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_enga_flpr.h b/templates/nrfx_config_nrf54h20_enga_flpr.h index e82bf6b26..0e55cbddc 100644 --- a/templates/nrfx_config_nrf54h20_enga_flpr.h +++ b/templates/nrfx_config_nrf54h20_enga_flpr.h @@ -244,6 +244,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_GRTC_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_enga_ppr.h b/templates/nrfx_config_nrf54h20_enga_ppr.h index 3f48a5655..80bf5d4bb 100644 --- a/templates/nrfx_config_nrf54h20_enga_ppr.h +++ b/templates/nrfx_config_nrf54h20_enga_ppr.h @@ -244,6 +244,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_GPIOTE_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_enga_radiocore.h b/templates/nrfx_config_nrf54h20_enga_radiocore.h index 67be03c2f..01f040ecb 100644 --- a/templates/nrfx_config_nrf54h20_enga_radiocore.h +++ b/templates/nrfx_config_nrf54h20_enga_radiocore.h @@ -320,6 +320,96 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI020_ENABLED +#define NRFX_DPPI020_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI030_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI030_ENABLED +#define NRFX_DPPI030_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -738,6 +828,57 @@ #define NRFX_PDM_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB020_ENABLED +#define NRFX_PPIB020_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB030_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB030_ENABLED +#define NRFX_PPIB030_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_engb_application.h b/templates/nrfx_config_nrf54h20_engb_application.h index 4b848a328..458c8f237 100644 --- a/templates/nrfx_config_nrf54h20_engb_application.h +++ b/templates/nrfx_config_nrf54h20_engb_application.h @@ -289,6 +289,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_engb_flpr.h b/templates/nrfx_config_nrf54h20_engb_flpr.h index f3bf5b7ef..cbad87e4a 100644 --- a/templates/nrfx_config_nrf54h20_engb_flpr.h +++ b/templates/nrfx_config_nrf54h20_engb_flpr.h @@ -244,6 +244,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_engb_ppr.h b/templates/nrfx_config_nrf54h20_engb_ppr.h index 1ff50be8b..429e9e9e4 100644 --- a/templates/nrfx_config_nrf54h20_engb_ppr.h +++ b/templates/nrfx_config_nrf54h20_engb_ppr.h @@ -244,6 +244,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_engb_radiocore.h b/templates/nrfx_config_nrf54h20_engb_radiocore.h index f22358251..a7b1e6920 100644 --- a/templates/nrfx_config_nrf54h20_engb_radiocore.h +++ b/templates/nrfx_config_nrf54h20_engb_radiocore.h @@ -320,6 +320,96 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI020_ENABLED +#define NRFX_DPPI020_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI030_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI030_ENABLED +#define NRFX_DPPI030_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -696,6 +786,57 @@ #define NRFX_PDM_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB020_ENABLED +#define NRFX_PPIB020_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB030_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB030_ENABLED +#define NRFX_PPIB030_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_flpr.h b/templates/nrfx_config_nrf54h20_flpr.h index cf75538c5..924796f85 100644 --- a/templates/nrfx_config_nrf54h20_flpr.h +++ b/templates/nrfx_config_nrf54h20_flpr.h @@ -244,6 +244,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_ppr.h b/templates/nrfx_config_nrf54h20_ppr.h index 5fd927092..152848ad4 100644 --- a/templates/nrfx_config_nrf54h20_ppr.h +++ b/templates/nrfx_config_nrf54h20_ppr.h @@ -244,6 +244,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_radiocore.h b/templates/nrfx_config_nrf54h20_radiocore.h index 70374f76e..2a4293946 100644 --- a/templates/nrfx_config_nrf54h20_radiocore.h +++ b/templates/nrfx_config_nrf54h20_radiocore.h @@ -320,6 +320,96 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI020_ENABLED +#define NRFX_DPPI020_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI030_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI030_ENABLED +#define NRFX_DPPI030_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -696,6 +786,57 @@ #define NRFX_PDM_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB020_ENABLED +#define NRFX_PPIB020_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB030_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB030_ENABLED +#define NRFX_PPIB030_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf54l15_application.h b/templates/nrfx_config_nrf54l15_application.h index 6f25410be..5e893be79 100644 --- a/templates/nrfx_config_nrf54l15_application.h +++ b/templates/nrfx_config_nrf54l15_application.h @@ -163,6 +163,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + /** * @brief NRFX_DPPI_CONFIG_LOG_ENABLED * @@ -187,6 +196,42 @@ #define NRFX_DPPI_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI00_ENABLED +#define NRFX_DPPI00_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI10_ENABLED +#define NRFX_DPPI10_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI20_ENABLED +#define NRFX_DPPI20_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI30_ENABLED +#define NRFX_DPPI30_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -599,6 +644,111 @@ #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB00_ENABLED +#define NRFX_PPIB00_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB01_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB01_ENABLED +#define NRFX_PPIB01_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB10_ENABLED +#define NRFX_PPIB10_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB11_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB11_ENABLED +#define NRFX_PPIB11_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB20_ENABLED +#define NRFX_PPIB20_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB21_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB21_ENABLED +#define NRFX_PPIB21_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB22_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB22_ENABLED +#define NRFX_PPIB22_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB30_ENABLED +#define NRFX_PPIB30_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf54l15_enga_application.h b/templates/nrfx_config_nrf54l15_enga_application.h index 156ad1bd8..4766bf589 100644 --- a/templates/nrfx_config_nrf54l15_enga_application.h +++ b/templates/nrfx_config_nrf54l15_enga_application.h @@ -163,6 +163,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + /** * @brief NRFX_DPPI_CONFIG_LOG_ENABLED * @@ -187,6 +196,42 @@ #define NRFX_DPPI_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI00_ENABLED +#define NRFX_DPPI00_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI10_ENABLED +#define NRFX_DPPI10_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI20_ENABLED +#define NRFX_DPPI20_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI30_ENABLED +#define NRFX_DPPI30_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -539,6 +584,111 @@ #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB00_ENABLED +#define NRFX_PPIB00_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB01_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB01_ENABLED +#define NRFX_PPIB01_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB10_ENABLED +#define NRFX_PPIB10_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB11_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB11_ENABLED +#define NRFX_PPIB11_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB20_ENABLED +#define NRFX_PPIB20_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB21_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB21_ENABLED +#define NRFX_PPIB21_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB22_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB22_ENABLED +#define NRFX_PPIB22_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB30_ENABLED +#define NRFX_PPIB30_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf54l15_enga_flpr.h b/templates/nrfx_config_nrf54l15_enga_flpr.h index 1f65115a2..7736e5346 100644 --- a/templates/nrfx_config_nrf54l15_enga_flpr.h +++ b/templates/nrfx_config_nrf54l15_enga_flpr.h @@ -172,6 +172,15 @@ #define NRFX_COREDEP_VPR_LEGACY 0 #endif +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + /** * @brief NRFX_DPPI_CONFIG_LOG_ENABLED * @@ -196,6 +205,42 @@ #define NRFX_DPPI_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI00_ENABLED +#define NRFX_DPPI00_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI10_ENABLED +#define NRFX_DPPI10_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI20_ENABLED +#define NRFX_DPPI20_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI30_ENABLED +#define NRFX_DPPI30_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -548,6 +593,111 @@ #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB00_ENABLED +#define NRFX_PPIB00_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB01_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB01_ENABLED +#define NRFX_PPIB01_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB10_ENABLED +#define NRFX_PPIB10_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB11_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB11_ENABLED +#define NRFX_PPIB11_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB20_ENABLED +#define NRFX_PPIB20_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB21_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB21_ENABLED +#define NRFX_PPIB21_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB22_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB22_ENABLED +#define NRFX_PPIB22_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB30_ENABLED +#define NRFX_PPIB30_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf54l15_flpr.h b/templates/nrfx_config_nrf54l15_flpr.h index b6ea8e03b..768e832c9 100644 --- a/templates/nrfx_config_nrf54l15_flpr.h +++ b/templates/nrfx_config_nrf54l15_flpr.h @@ -172,6 +172,15 @@ #define NRFX_COREDEP_VPR_LEGACY 0 #endif +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + /** * @brief NRFX_DPPI_CONFIG_LOG_ENABLED * @@ -196,6 +205,42 @@ #define NRFX_DPPI_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI00_ENABLED +#define NRFX_DPPI00_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI10_ENABLED +#define NRFX_DPPI10_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI20_ENABLED +#define NRFX_DPPI20_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI30_ENABLED +#define NRFX_DPPI30_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -608,6 +653,111 @@ #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB00_ENABLED +#define NRFX_PPIB00_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB01_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB01_ENABLED +#define NRFX_PPIB01_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB10_ENABLED +#define NRFX_PPIB10_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB11_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB11_ENABLED +#define NRFX_PPIB11_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB20_ENABLED +#define NRFX_PPIB20_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB21_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB21_ENABLED +#define NRFX_PPIB21_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB22_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB22_ENABLED +#define NRFX_PPIB22_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB30_ENABLED +#define NRFX_PPIB30_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf54l20_enga_application.h b/templates/nrfx_config_nrf54l20_enga_application.h index 964659663..a75384041 100644 --- a/templates/nrfx_config_nrf54l20_enga_application.h +++ b/templates/nrfx_config_nrf54l20_enga_application.h @@ -163,6 +163,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + /** * @brief NRFX_DPPI_CONFIG_LOG_ENABLED * @@ -187,6 +196,51 @@ #define NRFX_DPPI_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI00_ENABLED +#define NRFX_DPPI00_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI01_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI01_ENABLED +#define NRFX_DPPI01_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI10_ENABLED +#define NRFX_DPPI10_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI20_ENABLED +#define NRFX_DPPI20_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI30_ENABLED +#define NRFX_DPPI30_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -539,6 +593,147 @@ #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB00_ENABLED +#define NRFX_PPIB00_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB01_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB01_ENABLED +#define NRFX_PPIB01_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB02_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB02_ENABLED +#define NRFX_PPIB02_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB03_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB03_ENABLED +#define NRFX_PPIB03_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB04_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB04_ENABLED +#define NRFX_PPIB04_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB10_ENABLED +#define NRFX_PPIB10_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB11_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB11_ENABLED +#define NRFX_PPIB11_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB12_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB12_ENABLED +#define NRFX_PPIB12_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB20_ENABLED +#define NRFX_PPIB20_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB21_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB21_ENABLED +#define NRFX_PPIB21_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB22_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB22_ENABLED +#define NRFX_PPIB22_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB30_ENABLED +#define NRFX_PPIB30_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf54l20_enga_flpr.h b/templates/nrfx_config_nrf54l20_enga_flpr.h index c98d81d2b..3e723b0a4 100644 --- a/templates/nrfx_config_nrf54l20_enga_flpr.h +++ b/templates/nrfx_config_nrf54l20_enga_flpr.h @@ -172,6 +172,15 @@ #define NRFX_COREDEP_VPR_LEGACY 0 #endif +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + /** * @brief NRFX_DPPI_CONFIG_LOG_ENABLED * @@ -196,6 +205,51 @@ #define NRFX_DPPI_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_DPPI00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI00_ENABLED +#define NRFX_DPPI00_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI01_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI01_ENABLED +#define NRFX_DPPI01_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI10_ENABLED +#define NRFX_DPPI10_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI20_ENABLED +#define NRFX_DPPI20_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI30_ENABLED +#define NRFX_DPPI30_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -548,6 +602,147 @@ #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB00_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB00_ENABLED +#define NRFX_PPIB00_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB01_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB01_ENABLED +#define NRFX_PPIB01_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB02_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB02_ENABLED +#define NRFX_PPIB02_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB03_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB03_ENABLED +#define NRFX_PPIB03_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB04_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB04_ENABLED +#define NRFX_PPIB04_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB10_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB10_ENABLED +#define NRFX_PPIB10_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB11_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB11_ENABLED +#define NRFX_PPIB11_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB12_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB12_ENABLED +#define NRFX_PPIB12_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB20_ENABLED +#define NRFX_PPIB20_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB21_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB21_ENABLED +#define NRFX_PPIB21_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB22_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB22_ENABLED +#define NRFX_PPIB22_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB30_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB30_ENABLED +#define NRFX_PPIB30_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED * diff --git a/templates/nrfx_config_nrf9230_engb_application.h b/templates/nrfx_config_nrf9230_engb_application.h index ce747041f..706f2d264 100644 --- a/templates/nrfx_config_nrf9230_engb_application.h +++ b/templates/nrfx_config_nrf9230_engb_application.h @@ -289,6 +289,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * diff --git a/templates/nrfx_config_nrf9230_engb_ppr.h b/templates/nrfx_config_nrf9230_engb_ppr.h index 7c9a45a58..c2a13fd8a 100644 --- a/templates/nrfx_config_nrf9230_engb_ppr.h +++ b/templates/nrfx_config_nrf9230_engb_ppr.h @@ -244,6 +244,78 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * diff --git a/templates/nrfx_config_nrf9230_engb_radiocore.h b/templates/nrfx_config_nrf9230_engb_radiocore.h index e354aa053..f499aced5 100644 --- a/templates/nrfx_config_nrf9230_engb_radiocore.h +++ b/templates/nrfx_config_nrf9230_engb_radiocore.h @@ -320,6 +320,96 @@ #define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e #endif +/** + * @brief NRFX_DPPI020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI020_ENABLED +#define NRFX_DPPI020_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI030_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI030_ENABLED +#define NRFX_DPPI030_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI120_ENABLED +#define NRFX_DPPI120_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI130_ENABLED +#define NRFX_DPPI130_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI131_ENABLED +#define NRFX_DPPI131_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI132_ENABLED +#define NRFX_DPPI132_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI133_ENABLED +#define NRFX_DPPI133_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI134_ENABLED +#define NRFX_DPPI134_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI135_ENABLED +#define NRFX_DPPI135_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI136_ENABLED +#define NRFX_DPPI136_ENABLED 0 +#endif + /** * @brief NRFX_EGU_ENABLED * @@ -723,6 +813,57 @@ #define NRFX_PDM_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_PPIB_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_ENABLED +#define NRFX_PPIB_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED +#define NRFX_PPIB_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL +#define NRFX_PPIB_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PPIB020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB020_ENABLED +#define NRFX_PPIB020_ENABLED 0 +#endif + +/** + * @brief NRFX_PPIB030_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PPIB030_ENABLED +#define NRFX_PPIB030_ENABLED 0 +#endif + /** * @brief NRFX_PRS_ENABLED *