From 2527e3c8449cfd38aee41598e8af8492f410ed15 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Fri, 7 Apr 2023 12:23:03 +0200 Subject: [PATCH] nrfx 2.11.0 release --- .gitignore | 1 + CHANGELOG.md | 11 + LICENSE | 2 +- README.md | 6 +- doc/drv_supp_matrix.dox | 133 +- doc/generate_sphinx_doc.bat | 2 +- doc/generate_sphinx_doc.sh | 2 +- doc/{nrf9160.dox => nrf91_series.dox} | 4 +- doc/nrfx.doxyfile | 805 +- doc/sphinx/drv_supp_matrix.rst | 2 +- doc/sphinx/nrf9160.rst | 5 - doc/sphinx/nrf91_series.rst | 5 + drivers/include/nrf_bitmask.h | 2 +- drivers/include/nrfx_adc.h | 2 +- drivers/include/nrfx_clock.h | 11 +- drivers/include/nrfx_comp.h | 2 +- drivers/include/nrfx_dppi.h | 2 +- drivers/include/nrfx_egu.h | 2 +- drivers/include/nrfx_gpiote.h | 4 +- drivers/include/nrfx_i2s.h | 4 +- drivers/include/nrfx_ipc.h | 2 +- drivers/include/nrfx_lpcomp.h | 2 +- drivers/include/nrfx_nfct.h | 2 +- drivers/include/nrfx_nvmc.h | 10 +- drivers/include/nrfx_pdm.h | 6 +- drivers/include/nrfx_power.h | 2 +- drivers/include/nrfx_power_clock.h | 2 +- drivers/include/nrfx_power_compat.h | 2 +- drivers/include/nrfx_ppi.h | 2 +- drivers/include/nrfx_pwm.h | 2 +- drivers/include/nrfx_qdec.h | 2 +- drivers/include/nrfx_qspi.h | 6 +- drivers/include/nrfx_rng.h | 2 +- drivers/include/nrfx_rtc.h | 2 +- drivers/include/nrfx_saadc.h | 2 +- drivers/include/nrfx_spi.h | 2 +- drivers/include/nrfx_spim.h | 2 +- drivers/include/nrfx_spis.h | 2 +- drivers/include/nrfx_systick.h | 2 +- drivers/include/nrfx_temp.h | 2 +- drivers/include/nrfx_timer.h | 2 +- drivers/include/nrfx_twi.h | 2 +- drivers/include/nrfx_twi_twim.h | 2 +- drivers/include/nrfx_twim.h | 2 +- drivers/include/nrfx_twis.h | 2 +- drivers/include/nrfx_uart.h | 2 +- drivers/include/nrfx_uarte.h | 2 +- drivers/include/nrfx_usbd.h | 2 +- drivers/include/nrfx_usbreg.h | 2 +- drivers/include/nrfx_wdt.h | 2 +- drivers/nrfx_common.h | 2 +- drivers/nrfx_errors.h | 2 +- drivers/src/nrfx_adc.c | 2 +- drivers/src/nrfx_clock.c | 2 +- drivers/src/nrfx_comp.c | 2 +- drivers/src/nrfx_dppi.c | 2 +- drivers/src/nrfx_egu.c | 2 +- drivers/src/nrfx_gpiote.c | 2 +- drivers/src/nrfx_i2s.c | 4 +- drivers/src/nrfx_ipc.c | 2 +- drivers/src/nrfx_lpcomp.c | 2 +- drivers/src/nrfx_nfct.c | 2 +- drivers/src/nrfx_nvmc.c | 13 +- drivers/src/nrfx_pdm.c | 2 +- drivers/src/nrfx_power.c | 2 +- drivers/src/nrfx_ppi.c | 2 +- drivers/src/nrfx_pwm.c | 2 +- drivers/src/nrfx_qdec.c | 2 +- drivers/src/nrfx_qspi.c | 2 +- drivers/src/nrfx_rng.c | 2 +- drivers/src/nrfx_rtc.c | 2 +- drivers/src/nrfx_saadc.c | 2 +- drivers/src/nrfx_spi.c | 2 +- drivers/src/nrfx_spim.c | 2 +- drivers/src/nrfx_spis.c | 2 +- drivers/src/nrfx_systick.c | 2 +- drivers/src/nrfx_temp.c | 2 +- drivers/src/nrfx_timer.c | 2 +- drivers/src/nrfx_twi.c | 2 +- drivers/src/nrfx_twi_twim.c | 2 +- drivers/src/nrfx_twim.c | 2 +- drivers/src/nrfx_twis.c | 2 +- drivers/src/nrfx_uart.c | 2 +- drivers/src/nrfx_uarte.c | 10 +- drivers/src/nrfx_usbd.c | 4 +- drivers/src/nrfx_usbd_errata.h | 2 +- drivers/src/nrfx_usbreg.c | 2 +- drivers/src/nrfx_wdt.c | 2 +- drivers/src/prs/nrfx_prs.c | 2 +- drivers/src/prs/nrfx_prs.h | 4 +- hal/nrf_aar.h | 2 +- hal/nrf_acl.h | 2 +- hal/nrf_adc.h | 2 +- hal/nrf_bprot.h | 2 +- hal/nrf_cache.h | 2 +- hal/nrf_ccm.h | 2 +- hal/nrf_clock.h | 2 +- hal/nrf_common.h | 6 +- hal/nrf_comp.h | 2 +- hal/nrf_dcnf.h | 2 +- hal/nrf_dppi.h | 2 +- hal/nrf_ecb.h | 2 +- hal/nrf_egu.h | 4 +- hal/nrf_ficr.h | 2 +- hal/nrf_fpu.h | 2 +- hal/nrf_gpio.h | 2 +- hal/nrf_gpiote.h | 4 +- hal/nrf_i2s.h | 2 +- hal/nrf_ipc.h | 2 +- hal/nrf_kmu.h | 2 +- hal/nrf_lpcomp.h | 2 +- hal/nrf_mpu.h | 2 +- hal/nrf_mutex.h | 2 +- hal/nrf_mwu.h | 2 +- hal/nrf_nfct.h | 2 +- hal/nrf_nvmc.h | 12 +- hal/nrf_oscillators.h | 2 +- hal/nrf_pdm.h | 2 +- hal/nrf_power.h | 2 +- hal/nrf_ppi.h | 2 +- hal/nrf_pwm.h | 2 +- hal/nrf_qdec.h | 2 +- hal/nrf_qspi.h | 2 +- hal/nrf_radio.h | 2 +- hal/nrf_regulators.h | 2 +- hal/nrf_reset.h | 28 +- hal/nrf_rng.h | 2 +- hal/nrf_rtc.h | 2 +- hal/nrf_saadc.h | 2 +- hal/nrf_spi.h | 2 +- hal/nrf_spim.h | 2 +- hal/nrf_spis.h | 2 +- hal/nrf_spu.h | 2 +- hal/nrf_systick.h | 2 +- hal/nrf_temp.h | 2 +- hal/nrf_timer.h | 2 +- hal/nrf_twi.h | 2 +- hal/nrf_twim.h | 2 +- hal/nrf_twis.h | 2 +- hal/nrf_uart.h | 2 +- hal/nrf_uarte.h | 2 +- hal/nrf_usbd.h | 2 +- hal/nrf_usbreg.h | 2 +- hal/nrf_vmc.h | 2 +- hal/nrf_vreqctrl.h | 2 +- hal/nrf_wdt.h | 2 +- helpers/nrfx_flag32_allocator.c | 2 +- helpers/nrfx_flag32_allocator.h | 2 +- helpers/nrfx_gppi.h | 2 +- helpers/nrfx_reset_reason.h | 2 +- mdk/arm_startup_nrf51.s | 2 +- mdk/arm_startup_nrf52.s | 2 +- mdk/arm_startup_nrf52805.s | 2 +- mdk/arm_startup_nrf52810.s | 2 +- mdk/arm_startup_nrf52811.s | 2 +- mdk/arm_startup_nrf52820.s | 2 +- mdk/arm_startup_nrf52833.s | 2 +- mdk/arm_startup_nrf52840.s | 2 +- mdk/arm_startup_nrf5340_application.s | 2 +- mdk/arm_startup_nrf5340_network.s | 2 +- mdk/arm_startup_nrf9120.s | 492 + mdk/arm_startup_nrf9160.s | 2 +- mdk/compiler_abstraction.h | 186 +- mdk/gcc_startup_nrf51.S | 86 +- mdk/gcc_startup_nrf52.S | 86 +- mdk/gcc_startup_nrf52805.S | 86 +- mdk/gcc_startup_nrf52810.S | 86 +- mdk/gcc_startup_nrf52811.S | 86 +- mdk/gcc_startup_nrf52820.S | 86 +- mdk/gcc_startup_nrf52833.S | 86 +- mdk/gcc_startup_nrf52840.S | 86 +- mdk/gcc_startup_nrf5340_application.S | 86 +- mdk/gcc_startup_nrf5340_network.S | 86 +- mdk/gcc_startup_nrf9120.S | 583 + mdk/gcc_startup_nrf9160.S | 86 +- mdk/iar_startup_nrf51.s | 2 +- mdk/iar_startup_nrf52.s | 2 +- mdk/iar_startup_nrf52805.s | 2 +- mdk/iar_startup_nrf52810.s | 2 +- mdk/iar_startup_nrf52811.s | 2 +- mdk/iar_startup_nrf52820.s | 2 +- mdk/iar_startup_nrf52833.s | 2 +- mdk/iar_startup_nrf52840.s | 2 +- mdk/iar_startup_nrf5340_application.s | 2 +- mdk/iar_startup_nrf5340_network.s | 2 +- mdk/iar_startup_nrf9120.s | 559 + mdk/iar_startup_nrf9160.s | 2 +- mdk/nrf.h | 21 +- mdk/nrf51.h | 8 +- mdk/nrf51.svd | 2 +- mdk/nrf51422_peripherals.h | 2 +- mdk/nrf51422_vectors.h | 169 + mdk/nrf51422_xxaa.sct | 15 + mdk/nrf51422_xxaa_memory.h | 73 + mdk/nrf51422_xxab.sct | 15 + mdk/nrf51422_xxab_memory.h | 73 + mdk/nrf51422_xxac.sct | 15 + mdk/nrf51422_xxac_memory.h | 73 + mdk/nrf51801_peripherals.h | 2 +- mdk/nrf51801_vectors.h | 169 + mdk/nrf51801_xxab.sct | 15 + mdk/nrf51801_xxab_memory.h | 73 + mdk/nrf51802_peripherals.h | 2 +- mdk/nrf51802_vectors.h | 169 + mdk/nrf51802_xxaa.sct | 15 + mdk/nrf51802_xxaa_memory.h | 73 + mdk/nrf51822_peripherals.h | 2 +- mdk/nrf51822_vectors.h | 169 + mdk/nrf51822_xxaa.sct | 15 + mdk/nrf51822_xxaa_memory.h | 73 + mdk/nrf51822_xxab.sct | 15 + mdk/nrf51822_xxab_memory.h | 73 + mdk/nrf51822_xxac.sct | 15 + mdk/nrf51822_xxac_memory.h | 73 + mdk/nrf51824_peripherals.h | 2 +- mdk/nrf51824_vectors.h | 169 + mdk/nrf51824_xxaa.sct | 15 + mdk/nrf51824_xxaa_memory.h | 73 + mdk/nrf51_bitfields.h | 2 +- mdk/nrf51_deprecated.h | 2 +- mdk/nrf51_erratas.h | 2 +- mdk/nrf51_peripherals.h | 2 +- mdk/nrf51_to_nrf52.h | 2 +- mdk/nrf51_to_nrf52810.h | 2 +- mdk/nrf51_to_nrf52840.h | 2 +- mdk/nrf52.h | 8 +- mdk/nrf52.svd | 2 +- mdk/nrf52805.h | 8 +- mdk/nrf52805.svd | 2 +- mdk/nrf52805_bitfields.h | 2 +- mdk/nrf52805_peripherals.h | 2 +- mdk/nrf52805_vectors.h | 266 + mdk/nrf52805_xxaa.sct | 18 + mdk/nrf52805_xxaa_memory.h | 77 + mdk/nrf52810.h | 8 +- mdk/nrf52810.svd | 2 +- mdk/nrf52810_bitfields.h | 2 +- mdk/nrf52810_name_change.h | 2 +- mdk/nrf52810_peripherals.h | 2 +- mdk/nrf52810_to_nrf52811.h | 2 +- mdk/nrf52810_vectors.h | 276 + mdk/nrf52810_xxaa.sct | 18 + mdk/nrf52810_xxaa_memory.h | 77 + mdk/nrf52811.h | 8 +- mdk/nrf52811.svd | 2 +- mdk/nrf52811_bitfields.h | 2 +- mdk/nrf52811_peripherals.h | 2 +- mdk/nrf52811_vectors.h | 269 + mdk/nrf52811_xxaa.sct | 18 + mdk/nrf52811_xxaa_memory.h | 77 + mdk/nrf52820.h | 8 +- mdk/nrf52820.svd | 2 +- mdk/nrf52820_bitfields.h | 2 +- mdk/nrf52820_peripherals.h | 2 +- mdk/nrf52820_vectors.h | 268 + mdk/nrf52820_xxaa.sct | 18 + mdk/nrf52820_xxaa_memory.h | 77 + mdk/nrf52832_peripherals.h | 2 +- mdk/nrf52832_vectors.h | 279 + mdk/nrf52832_xxaa.sct | 18 + mdk/nrf52832_xxaa_memory.h | 77 + mdk/nrf52832_xxab.sct | 18 + mdk/nrf52832_xxab_memory.h | 77 + mdk/nrf52833.h | 8 +- mdk/nrf52833.svd | 2 +- mdk/nrf52833_bitfields.h | 2 +- mdk/nrf52833_peripherals.h | 2 +- mdk/nrf52833_to_nrf52820.h | 2 +- mdk/nrf52833_vectors.h | 283 + mdk/nrf52833_xxaa.sct | 18 + mdk/nrf52833_xxaa_memory.h | 77 + mdk/nrf52840.h | 8 +- mdk/nrf52840.svd | 2 +- mdk/nrf52840_bitfields.h | 2 +- mdk/nrf52840_peripherals.h | 2 +- mdk/nrf52840_vectors.h | 285 + mdk/nrf52840_xxaa.sct | 21 + mdk/nrf52840_xxaa_memory.h | 81 + mdk/nrf52_bitfields.h | 2 +- mdk/nrf52_erratas.h | 152 +- mdk/nrf52_name_change.h | 2 +- mdk/nrf52_to_nrf52810.h | 2 +- mdk/nrf52_to_nrf52833.h | 2 +- mdk/nrf52_to_nrf52840.h | 2 +- mdk/nrf5340_application.h | 10 +- mdk/nrf5340_application.svd | 4 +- mdk/nrf5340_application_bitfields.h | 2 +- mdk/nrf5340_application_name_change.h | 2 +- mdk/nrf5340_application_peripherals.h | 2 +- mdk/nrf5340_application_vectors.h | 416 + mdk/nrf5340_network.h | 10 +- mdk/nrf5340_network.svd | 4 +- mdk/nrf5340_network_bitfields.h | 2 +- mdk/nrf5340_network_name_change.h | 2 +- mdk/nrf5340_network_peripherals.h | 2 +- mdk/nrf5340_network_vectors.h | 279 + mdk/nrf5340_xxaa_application.sct | 23 + mdk/nrf5340_xxaa_application_memory.h | 85 + mdk/nrf5340_xxaa_network.sct | 28 + mdk/nrf5340_xxaa_network_memory.h | 89 + mdk/nrf53_erratas.h | 165 +- mdk/nrf9120.h | 2335 + mdk/nrf9120.svd | 35780 ++++++++++++++++ mdk/nrf9120_bitfields.h | 11195 +++++ mdk/nrf9120_peripherals.h | 232 + mdk/nrf9120_vectors.h | 406 + mdk/nrf9120_xxaa.ld | 13 + mdk/nrf9120_xxaa.sct | 15 + mdk/nrf9120_xxaa_memory.h | 77 + mdk/nrf9160.h | 13 +- mdk/nrf9160.svd | 104 +- mdk/nrf9160_bitfields.h | 34 +- mdk/nrf9160_name_change.h | 43 +- mdk/nrf9160_peripherals.h | 5 +- mdk/nrf9160_vectors.h | 406 + mdk/nrf9160_xxaa.sct | 15 + mdk/nrf9160_xxaa_memory.h | 77 + mdk/nrf91_erratas.h | 622 +- mdk/nrf91_name_change.h | 85 + mdk/nrf_common.ld | 376 +- mdk/nrf_erratas.h | 2 +- mdk/nrf_mem.h | 121 + mdk/nrf_peripherals.h | 6 +- mdk/nrf_vectors.h | 85 + mdk/ses_startup_nrf9120.s | 420 + mdk/startup_nrf_common.c | 237 + mdk/system_nrf.h | 30 +- mdk/system_nrf51.c | 14 +- mdk/system_nrf51.h | 30 +- mdk/system_nrf52.c | 101 +- mdk/system_nrf52.h | 30 +- mdk/system_nrf52805.c | 2 +- mdk/system_nrf52805.h | 30 +- mdk/system_nrf52810.c | 2 +- mdk/system_nrf52810.h | 30 +- mdk/system_nrf52811.c | 2 +- mdk/system_nrf52811.h | 30 +- mdk/system_nrf52820.c | 2 +- mdk/system_nrf52820.h | 30 +- mdk/system_nrf52833.c | 2 +- mdk/system_nrf52833.h | 30 +- mdk/system_nrf52840.c | 2 +- mdk/system_nrf52840.h | 30 +- mdk/system_nrf52_approtect.h | 2 +- mdk/system_nrf53.h | 30 +- mdk/system_nrf5340_application.c | 29 +- mdk/system_nrf5340_application.h | 30 +- mdk/system_nrf5340_network.c | 28 +- mdk/system_nrf5340_network.h | 30 +- mdk/system_nrf53_approtect.h | 2 +- mdk/system_nrf91.c | 148 +- mdk/system_nrf91.h | 30 +- mdk/system_nrf9120.h | 61 + mdk/system_nrf9160.c | 2 +- mdk/system_nrf9160.h | 30 +- mdk/system_nrf91_approtect.h | 87 + nrfx.h | 2 +- soc/nrfx_atomic.c | 2 +- soc/nrfx_atomic.h | 2 +- soc/nrfx_atomic_internal.h | 2 +- soc/nrfx_coredep.h | 4 +- soc/nrfx_irqs.h | 6 +- soc/nrfx_irqs_nrf51.h | 2 +- soc/nrfx_irqs_nrf52805.h | 2 +- soc/nrfx_irqs_nrf52810.h | 2 +- soc/nrfx_irqs_nrf52811.h | 2 +- soc/nrfx_irqs_nrf52820.h | 2 +- soc/nrfx_irqs_nrf52832.h | 2 +- soc/nrfx_irqs_nrf52833.h | 2 +- soc/nrfx_irqs_nrf52840.h | 2 +- soc/nrfx_irqs_nrf5340_application.h | 2 +- soc/nrfx_irqs_nrf5340_network.h | 2 +- ...{nrfx_irqs_nrf9160.h => nrfx_irqs_nrf91.h} | 8 +- templates/nrfx_config.h | 6 +- templates/nrfx_config_common.h | 7 +- templates/nrfx_config_nrf51.h | 2 +- templates/nrfx_config_nrf52805.h | 2 +- templates/nrfx_config_nrf52810.h | 2 +- templates/nrfx_config_nrf52811.h | 2 +- templates/nrfx_config_nrf52820.h | 2 +- templates/nrfx_config_nrf52832.h | 2 +- templates/nrfx_config_nrf52833.h | 2 +- templates/nrfx_config_nrf52840.h | 2 +- templates/nrfx_config_nrf5340_application.h | 2 +- templates/nrfx_config_nrf5340_network.h | 2 +- ...x_config_nrf9160.h => nrfx_config_nrf91.h} | 8 +- templates/nrfx_glue.h | 2 +- templates/nrfx_log.h | 2 +- 388 files changed, 62189 insertions(+), 1448 deletions(-) rename doc/{nrf9160.dox => nrf91_series.dox} (78%) delete mode 100644 doc/sphinx/nrf9160.rst create mode 100644 doc/sphinx/nrf91_series.rst create mode 100644 mdk/arm_startup_nrf9120.s create mode 100644 mdk/gcc_startup_nrf9120.S create mode 100644 mdk/iar_startup_nrf9120.s create mode 100644 mdk/nrf51422_vectors.h create mode 100644 mdk/nrf51422_xxaa.sct create mode 100644 mdk/nrf51422_xxaa_memory.h create mode 100644 mdk/nrf51422_xxab.sct create mode 100644 mdk/nrf51422_xxab_memory.h create mode 100644 mdk/nrf51422_xxac.sct create mode 100644 mdk/nrf51422_xxac_memory.h create mode 100644 mdk/nrf51801_vectors.h create mode 100644 mdk/nrf51801_xxab.sct create mode 100644 mdk/nrf51801_xxab_memory.h create mode 100644 mdk/nrf51802_vectors.h create mode 100644 mdk/nrf51802_xxaa.sct create mode 100644 mdk/nrf51802_xxaa_memory.h create mode 100644 mdk/nrf51822_vectors.h create mode 100644 mdk/nrf51822_xxaa.sct create mode 100644 mdk/nrf51822_xxaa_memory.h create mode 100644 mdk/nrf51822_xxab.sct create mode 100644 mdk/nrf51822_xxab_memory.h create mode 100644 mdk/nrf51822_xxac.sct create mode 100644 mdk/nrf51822_xxac_memory.h create mode 100644 mdk/nrf51824_vectors.h create mode 100644 mdk/nrf51824_xxaa.sct create mode 100644 mdk/nrf51824_xxaa_memory.h create mode 100644 mdk/nrf52805_vectors.h create mode 100644 mdk/nrf52805_xxaa.sct create mode 100644 mdk/nrf52805_xxaa_memory.h create mode 100644 mdk/nrf52810_vectors.h create mode 100644 mdk/nrf52810_xxaa.sct create mode 100644 mdk/nrf52810_xxaa_memory.h create mode 100644 mdk/nrf52811_vectors.h create mode 100644 mdk/nrf52811_xxaa.sct create mode 100644 mdk/nrf52811_xxaa_memory.h create mode 100644 mdk/nrf52820_vectors.h create mode 100644 mdk/nrf52820_xxaa.sct create mode 100644 mdk/nrf52820_xxaa_memory.h create mode 100644 mdk/nrf52832_vectors.h create mode 100644 mdk/nrf52832_xxaa.sct create mode 100644 mdk/nrf52832_xxaa_memory.h create mode 100644 mdk/nrf52832_xxab.sct create mode 100644 mdk/nrf52832_xxab_memory.h create mode 100644 mdk/nrf52833_vectors.h create mode 100644 mdk/nrf52833_xxaa.sct create mode 100644 mdk/nrf52833_xxaa_memory.h create mode 100644 mdk/nrf52840_vectors.h create mode 100644 mdk/nrf52840_xxaa.sct create mode 100644 mdk/nrf52840_xxaa_memory.h create mode 100644 mdk/nrf5340_application_vectors.h create mode 100644 mdk/nrf5340_network_vectors.h create mode 100644 mdk/nrf5340_xxaa_application.sct create mode 100644 mdk/nrf5340_xxaa_application_memory.h create mode 100644 mdk/nrf5340_xxaa_network.sct create mode 100644 mdk/nrf5340_xxaa_network_memory.h create mode 100644 mdk/nrf9120.h create mode 100644 mdk/nrf9120.svd create mode 100644 mdk/nrf9120_bitfields.h create mode 100644 mdk/nrf9120_peripherals.h create mode 100644 mdk/nrf9120_vectors.h create mode 100644 mdk/nrf9120_xxaa.ld create mode 100644 mdk/nrf9120_xxaa.sct create mode 100644 mdk/nrf9120_xxaa_memory.h create mode 100644 mdk/nrf9160_vectors.h create mode 100644 mdk/nrf9160_xxaa.sct create mode 100644 mdk/nrf9160_xxaa_memory.h create mode 100644 mdk/nrf91_name_change.h create mode 100644 mdk/nrf_mem.h create mode 100644 mdk/nrf_vectors.h create mode 100644 mdk/ses_startup_nrf9120.s create mode 100644 mdk/startup_nrf_common.c create mode 100644 mdk/system_nrf9120.h create mode 100644 mdk/system_nrf91_approtect.h rename soc/{nrfx_irqs_nrf9160.h => nrfx_irqs_nrf91.h} (97%) rename templates/{nrfx_config_nrf9160.h => nrfx_config_nrf91.h} (99%) diff --git a/.gitignore b/.gitignore index 8d5c3ace3..b1b55d411 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,4 @@ doc/html/* doc/html_sphinx/* doc/xml/* doc/warnings_nrfx.txt +doc/warnings_sphinx_nrfx.txt diff --git a/CHANGELOG.md b/CHANGELOG.md index 48c5be3cc..e5450b0ba 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,17 @@ # Changelog All notable changes to this project are documented in this file. +## [2.11.0] - 2023-04-07 +### Added +- Added support for the nRF9161 and nRF9131 SiPs. Use `NRF9120_XXAA` as the compilation symbol. +- Implemented a workaround for the anomaly 161 on the nRF5340 SoC in the RESET HAL. + +### Changed +- Updated MDK to version 8.53.1. + +### Fixed +- Removed a spurious function call causing aborting of endpoints in the SUSPEND event for the USBD driver. + ## [2.10.0] - 2022-10-25 ### Added - Added NRFX_CONFIG_API_VER_2_9 and NRFX_CONFIG_API_VER_2_10 symbols that guard API-breaking changes. Deprecated API is used by default. diff --git a/LICENSE b/LICENSE index 77fe14ea5..a64fa0bf1 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Copyright (c) 2017 - 2022, Nordic Semiconductor ASA +Copyright (c) 2017 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/README.md b/README.md index 9e123f136..2bd03fe50 100644 --- a/README.md +++ b/README.md @@ -3,14 +3,14 @@ ## Overview nrfx is a standalone set of drivers for peripherals present in Nordic -Semiconductor's SoCs. It originated as an extract from the nRF5 SDK. +Semiconductor's SoCs and SiPs. It originated as an extract from the nRF5 SDK. The intention was to provide drivers that can be used in various environments without the necessity to integrate other parts of the SDK into them. For the user's convenience, the drivers come with the MDK package. This package contains definitions of register structures and bitfields for all supported SoCs, as well as startup and initialization files for them. -## Supported SoCs +## Supported SoCs and SiPs * nRF51 Series * nRF52805 @@ -21,7 +21,9 @@ SoCs, as well as startup and initialization files for them. * nRF52833 * nRF52840 * nRF5340 +* nRF9131 * nRF9160 +* nRF9161 ## Directories diff --git a/doc/drv_supp_matrix.dox b/doc/drv_supp_matrix.dox index 99eb621b8..2b17b43d6 100644 --- a/doc/drv_supp_matrix.dox +++ b/doc/drv_supp_matrix.dox @@ -1,72 +1,93 @@ /** @page nrfx_drv_supp_matrix Driver support overview -This page lists nrfx driver components supported by each SoC: +This page lists MDK symbols to be used and nrfx driver components supported by particular SoCs and SiPs: +- @ref nrfx_mdk_symbols_table "MDK symbols table" - @ref nrfx_drv_supp_matrix_table "Driver support matrix" - @ref nrfx_drv_supp_matrix_list "Driver support lists" +@anchor nrfx_mdk_symbols_table +@par MDK symbols table + +The following table presents MDK symbol used for a specific device. +@warning The MDK symbol used to build nrfx for a specific device may not necessarily correspond to the device name. + +| Device | MDK symbol | +|--------------------|--------------------------------------------------| +| nRF51 Series | NRF51 | +| nRF52805 | NRF52805_XXAA | +| nRF52810 | NRF52810_XXAA | +| nRF52811 | NRF52811_XXAA | +| nRF52820 | NRF52820_XXAA | +| nRF52832 | NRF52832_XXAA
NRF52832_XXAB | +| nRF52833 | NRF52833_XXAA | +| nRF52840 | NRF52840_XXAA | +| nRF5340 | NRF5340_XXAA_APPLICATION
NRF5340_XXAA_NETWORK | +| nRF9131
nRF9161 | NRF9120_XXAA | +| nRF9160 | NRF9160_XXAA | + @anchor nrfx_drv_supp_matrix_table @par Driver support matrix -The following matrix provides a comparative overview of which drivers are supported by specific Nordic SoCs. +The following matrix provides a comparative overview of which drivers are supported by specific Nordic SoCs and SiPs. -| Driver | nRF51 Series | nRF52805 | nRF52810/nRF52811 | nRF52820 | nRF52832 | nRF52833 | nRF52840 | nRF5340 | nRF9160 | -|------------------|--------------|--------------|-------------------|--------------|--------------|--------------|--------------|--------------|--------------| -| @ref nrf_aar |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -| @ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -| @ref nrf_cache |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -| @ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_comp |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_dcnf |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -| @ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_egu |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_ficr |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_fpu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -| @ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_i2s |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_ipc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -| @ref nrf_mutex |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -| @ref nrf_mwu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_nfct |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_pdm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_pwm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| Driver | nRF51 Series | nRF52805 | nRF52810
nRF52811 | nRF52820 | nRF52832 | nRF52833 | nRF52840 | nRF5340 | nRF91 Series | +|------------------|--------------|--------------|----------------------|--------------|--------------|--------------|--------------|--------------|--------------| +| @ref nrf_aar |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_cache |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_comp |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_dcnf |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_egu |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_ficr |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_fpu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_i2s |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_ipc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_mutex |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_mwu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_nfct |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_pdm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_pwm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | @anchor nrfx_drv_supp_matrix_list @par Driver support lists -The following pages list supported drivers by SoC: +The following pages list the drivers supported by respective SoCs and SiPs: - @subpage nrf51_series_drivers - @subpage nrf52805_drivers @@ -76,6 +97,6 @@ The following pages list supported drivers by SoC: - @subpage nrf52833_drivers - @subpage nrf52840_drivers - @subpage nrf5340_drivers -- @subpage nrf9160_drivers +- @subpage nrf91_series_drivers */ diff --git a/doc/generate_sphinx_doc.bat b/doc/generate_sphinx_doc.bat index f409d7dac..8ae713fb1 100644 --- a/doc/generate_sphinx_doc.bat +++ b/doc/generate_sphinx_doc.bat @@ -1,3 +1,3 @@ del html\*.* xml\*.* html_sphinx\*.* /Q doxygen nrfx.doxyfile -sphinx-build -b html sphinx html_sphinx \ No newline at end of file +sphinx-build -b html sphinx html_sphinx -w warnings_sphinx_nrfx.txt diff --git a/doc/generate_sphinx_doc.sh b/doc/generate_sphinx_doc.sh index 46203db56..a3b492842 100755 --- a/doc/generate_sphinx_doc.sh +++ b/doc/generate_sphinx_doc.sh @@ -1,3 +1,3 @@ rm -rf html xml html_sphinx doxygen nrfx.doxyfile -sphinx-build -b html sphinx html_sphinx +sphinx-build -b html sphinx html_sphinx -w warnings_sphinx_nrfx.txt diff --git a/doc/nrf9160.dox b/doc/nrf91_series.dox similarity index 78% rename from doc/nrf9160.dox rename to doc/nrf91_series.dox index 360774d90..4a024ea45 100644 --- a/doc/nrf9160.dox +++ b/doc/nrf91_series.dox @@ -1,7 +1,7 @@ /** -@page nrf9160_drivers nRF9160 drivers +@page nrf91_series_drivers nRF91 Series drivers -This page lists nrfx driver components supported by the nRF9160 SoC. +This page lists nrfx driver components supported by the nRF91 Series SoCs. For a complete overview, see @ref nrfx_drv_supp_matrix. @{ diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index 29d6c76ca..07593ccad 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -1,4 +1,4 @@ -# Doxyfile 1.8.14 +# Doxyfile 1.9.6 # This file describes the settings to be used by the documentation system # doxygen (www.doxygen.org) for a project. @@ -12,15 +12,25 @@ # For lists, items can also be appended using: # TAG += value [value, ...] # Values that contain spaces should be placed between quotes (\" \"). +# +# Note: +# +# Use doxygen to compare the used configuration file with the template +# configuration file: +# doxygen -x [configFile] +# Use doxygen to compare the used configuration file with the template +# configuration file without replacing the environment variables or CMake type +# replacement variables: +# doxygen -x_noenv [configFile] #--------------------------------------------------------------------------- # Project related configuration options #--------------------------------------------------------------------------- -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all text -# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv -# built into libc) for the transcoding. See +# This tag specifies the encoding used for all characters in the configuration +# file that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See # https://www.gnu.org/software/libiconv/ for the list of possible encodings. # The default value is: UTF-8. @@ -40,7 +50,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "2.10" +PROJECT_NUMBER = "2.11" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a @@ -64,37 +74,49 @@ PROJECT_LOGO = buildfiles/nordic_small.png OUTPUT_DIRECTORY = -# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub- -# directories (in 2 levels) under the output directory of each output format and -# will distribute the generated files over these directories. Enabling this +# If the CREATE_SUBDIRS tag is set to YES then doxygen will create up to 4096 +# sub-directories (in 2 levels) under the output directory of each output format +# and will distribute the generated files over these directories. Enabling this # option can be useful when feeding doxygen a huge amount of source files, where # putting all generated files in the same directory would otherwise causes -# performance problems for the file system. +# performance problems for the file system. Adapt CREATE_SUBDIRS_LEVEL to +# control the number of sub-directories. # The default value is: NO. ### EDIT THIS ### CREATE_SUBDIRS = NO +# Controls the number of sub-directories that will be created when +# CREATE_SUBDIRS tag is set to YES. Level 0 represents 16 directories, and every +# level increment doubles the number of directories, resulting in 4096 +# directories at level 8 which is the default and also the maximum value. The +# sub-directories are organized in 2 levels, the first level always has a fixed +# number of 16 directories. +# Minimum value: 0, maximum value: 8, default value: 8. +# This tag requires that the tag CREATE_SUBDIRS is set to YES. + +CREATE_SUBDIRS_LEVEL = 8 + # If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII # characters to appear in the names of generated files. If set to NO, non-ASCII # characters will be escaped, for example _xE3_x81_x84 will be used for Unicode # U+3044. # The default value is: NO. -#ALLOW_UNICODE_NAMES = NO +ALLOW_UNICODE_NAMES = NO # The OUTPUT_LANGUAGE tag is used to specify the language in which all # documentation generated by doxygen is written. Doxygen will use this # information to generate all constant output in the proper language. -# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese, -# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States), -# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian, -# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages), -# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian, -# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian, -# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish, -# Ukrainian and Vietnamese. +# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Bulgarian, +# Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch, English +# (United States), Esperanto, Farsi (Persian), Finnish, French, German, Greek, +# Hindi, Hungarian, Indonesian, Italian, Japanese, Japanese-en (Japanese with +# English messages), Korean, Korean-en (Korean with English messages), Latvian, +# Lithuanian, Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, +# Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, +# Swedish, Turkish, Ukrainian and Vietnamese. # The default value is: English. OUTPUT_LANGUAGE = English @@ -185,6 +207,16 @@ SHORT_NAMES = NO JAVADOC_AUTOBRIEF = NO +# If the JAVADOC_BANNER tag is set to YES then doxygen will interpret a line +# such as +# /*************** +# as being the beginning of a Javadoc-style comment "banner". If set to NO, the +# Javadoc-style will behave just like regular comments and it will not be +# interpreted by doxygen. +# The default value is: NO. + +JAVADOC_BANNER = NO + # If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first # line (until the first dot) of a Qt-style comment as the brief description. If # set to NO, the Qt-style will behave just like regular Qt-style comments (thus @@ -205,6 +237,14 @@ QT_AUTOBRIEF = NO MULTILINE_CPP_IS_BRIEF = NO +# By default Python docstrings are displayed as preformatted text and doxygen's +# special commands cannot be used. By setting PYTHON_DOCSTRING to NO the +# doxygen's special commands can be used and the contents of the docstring +# documentation blocks is shown as doxygen documentation. +# The default value is: YES. + +PYTHON_DOCSTRING = YES + # If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the # documentation from any documented member that it re-implements. # The default value is: YES. @@ -228,23 +268,21 @@ TAB_SIZE = 4 # the documentation. An alias has the form: # name=value # For example adding -# "sideeffect=@par Side Effects:\n" +# "sideeffect=@par Side Effects:^^" # will allow you to put the command \sideeffect (or @sideeffect) in the # documentation, which will result in a user-defined paragraph with heading -# "Side Effects:". You can put \n's in the value part of an alias to insert -# newlines (in the resulting output). You can put ^^ in the value part of an -# alias to insert a newline as if a physical newline was in the original file. +# "Side Effects:". Note that you cannot put \n's in the value part of an alias +# to insert newlines (in the resulting output). You can put ^^ in the value part +# of an alias to insert a newline as if a physical newline was in the original +# file. When you need a literal { or } or , in the value part of an alias you +# have to escape them by means of a backslash (\), this can lead to conflicts +# with the commands \{ and \} for these it is advised to use the version @{ and +# @} or use a double escape (\\{ and \\}) ALIASES = "tagGreenTick=\htmlonly
✔
\endhtmlonly \xmlonlyembed:rst:inline :green:`✔`\endxmlonly" \ "tagRedCross=\htmlonly
✖
\endhtmlonly \xmlonlyembed:rst:inline :red:`✖`\endxmlonly" \ "nRF5340pinAssignmentsURL=\"https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf5340%2Fchapters%2Fpin.html\"" -# This tag can be used to specify a number of word-keyword mappings (TCL only). -# A mapping has the form "name=value". For example adding "class=itcl::class" -# will allow you to use the command class in the itcl::class meaning. - -# TCL_SUBST = - # Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources # only. Doxygen will then generate output that is more tailored for C. For # instance, some of the names that are used will be different. The list of all @@ -273,28 +311,40 @@ OPTIMIZE_FOR_FORTRAN = NO OPTIMIZE_OUTPUT_VHDL = NO +# Set the OPTIMIZE_OUTPUT_SLICE tag to YES if your project consists of Slice +# sources only. Doxygen will then generate output that is more tailored for that +# language. For instance, namespaces will be presented as modules, types will be +# separated into more groups, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_SLICE = NO + # Doxygen selects the parser to use depending on the extension of the files it # parses. With this tag you can assign which parser to use for a given # extension. Doxygen has a built-in mapping, but you can override or extend it # using this tag. The format is ext=language, where ext is a file extension, and -# language is one of the parsers supported by doxygen: IDL, Java, Javascript, -# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran: -# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran: -# Fortran. In the later case the parser tries to guess whether the code is fixed -# or free formatted code, this is the default for Fortran type files), VHDL. For -# instance to make doxygen treat .inc files as Fortran files (default is PHP), -# and .f files as C (default is Fortran), use: inc=Fortran f=C. +# language is one of the parsers supported by doxygen: IDL, Java, JavaScript, +# Csharp (C#), C, C++, Lex, D, PHP, md (Markdown), Objective-C, Python, Slice, +# VHDL, Fortran (fixed format Fortran: FortranFixed, free formatted Fortran: +# FortranFree, unknown formatted Fortran: Fortran. In the later case the parser +# tries to guess whether the code is fixed or free formatted code, this is the +# default for Fortran type files). For instance to make doxygen treat .inc files +# as Fortran files (default is PHP), and .f files as C (default is Fortran), +# use: inc=Fortran f=C. # # Note: For files without extension you can use no_extension as a placeholder. # # Note that for custom extensions you also need to set FILE_PATTERNS otherwise -# the files are not read by doxygen. +# the files are not read by doxygen. When specifying no_extension you should add +# * to the FILE_PATTERNS. +# +# Note see also the list of default file extension mappings. EXTENSION_MAPPING = # If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments # according to the Markdown format, which allows for more readable -# documentation. See http://daringfireball.net/projects/markdown/ for details. +# documentation. See https://daringfireball.net/projects/markdown/ for details. # The output of markdown processing is further processed by doxygen, so you can # mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in # case of backward compatibilities issues. @@ -306,10 +356,10 @@ MARKDOWN_SUPPORT = YES # to that level are automatically included in the table of contents, even if # they do not have an id attribute. # Note: This feature currently applies only to Markdown headings. -# Minimum value: 0, maximum value: 99, default value: 0. +# Minimum value: 0, maximum value: 99, default value: 5. # This tag requires that the tag MARKDOWN_SUPPORT is set to YES. -#TOC_INCLUDE_HEADINGS = 0 +TOC_INCLUDE_HEADINGS = 5 # When enabled doxygen tries to link words that correspond to documented # classes, or namespaces to their corresponding documentation. Such a link can @@ -366,7 +416,7 @@ DISTRIBUTE_GROUP_DOC = NO # is disabled and one has to add nested compounds explicitly via \ingroup. # The default value is: NO. -#GROUP_NESTED_COMPOUNDS = NO +GROUP_NESTED_COMPOUNDS = NO # Set the SUBGROUPING tag to YES to allow class member groups of the same type # (for instance a group of public functions) to be put as a subgroup of that @@ -422,6 +472,19 @@ TYPEDEF_HIDES_STRUCT = NO LOOKUP_CACHE_SIZE = 0 +# The NUM_PROC_THREADS specifies the number of threads doxygen is allowed to use +# during processing. When set to 0 doxygen will based this on the number of +# cores available in the system. You can set it explicitly to a value larger +# than 0 to get more control over the balance between CPU load and processing +# speed. At this moment only the input processing can be done using multiple +# threads. Since this is still an experimental feature the default is set to 1, +# which effectively disables parallel processing. Please report any issues you +# encounter. Generating dot graphs in parallel is controlled by the +# DOT_NUM_THREADS setting. +# Minimum value: 0, maximum value: 32, default value: 1. + +NUM_PROC_THREADS = 1 + #--------------------------------------------------------------------------- # Build related configuration options #--------------------------------------------------------------------------- @@ -442,6 +505,12 @@ EXTRACT_ALL = NO EXTRACT_PRIVATE = NO +# If the EXTRACT_PRIV_VIRTUAL tag is set to YES, documented private virtual +# methods of a class will be included in the documentation. +# The default value is: NO. + +EXTRACT_PRIV_VIRTUAL = NO + # If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal # scope will be included in the documentation. # The default value is: NO. @@ -479,6 +548,13 @@ EXTRACT_LOCAL_METHODS = NO EXTRACT_ANON_NSPACES = NO +# If this flag is set to YES, the name of an unnamed parameter in a declaration +# will be determined by the corresponding definition. By default unnamed +# parameters remain unnamed in the output. +# The default value is: YES. + +RESOLVE_UNNAMED_PARAMS = YES + # If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all # undocumented members inside documented classes or files. If set to NO these # members will be included in the various overviews, but no documentation @@ -490,14 +566,15 @@ HIDE_UNDOC_MEMBERS = NO # If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all # undocumented classes that are normally visible in the class hierarchy. If set # to NO, these classes will be included in the various overviews. This option -# has no effect if EXTRACT_ALL is enabled. +# will also hide undocumented C++ concepts if enabled. This option has no effect +# if EXTRACT_ALL is enabled. # The default value is: NO. HIDE_UNDOC_CLASSES = NO # If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend -# (class|struct|union) declarations. If set to NO, these declarations will be -# included in the documentation. +# declarations. If set to NO, these declarations will be included in the +# documentation. # The default value is: NO. HIDE_FRIEND_COMPOUNDS = NO @@ -516,12 +593,20 @@ HIDE_IN_BODY_DOCS = NO INTERNAL_DOCS = NO -# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file -# names in lower-case letters. If set to YES, upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. -# The default value is: system dependent. +# With the correct setting of option CASE_SENSE_NAMES doxygen will better be +# able to match the capabilities of the underlying filesystem. In case the +# filesystem is case sensitive (i.e. it supports files in the same directory +# whose names only differ in casing), the option must be set to YES to properly +# deal with such files in case they appear in the input. For filesystems that +# are not case sensitive the option should be set to NO to properly deal with +# output files written for symbols that only differ in casing, such as for two +# classes, one named CLASS and the other named Class, and to also support +# references to files without having to specify the exact matching casing. On +# Windows (including Cygwin) and MacOS, users should typically set this option +# to NO, whereas on Linux or other Unix flavors it should typically be set to +# YES. +# Possible values are: SYSTEM, NO and YES. +# The default value is: SYSTEM. CASE_SENSE_NAMES = NO @@ -537,7 +622,13 @@ HIDE_SCOPE_NAMES = NO # YES the compound reference will be hidden. # The default value is: NO. -#HIDE_COMPOUND_REFERENCE= NO +HIDE_COMPOUND_REFERENCE= NO + +# If the SHOW_HEADERFILE tag is set to YES then the documentation for a class +# will show which file needs to be included to use the class. +# The default value is: YES. + +SHOW_HEADERFILE = YES # If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of # the files that are included by a file in the documentation of that file. @@ -550,7 +641,7 @@ SHOW_INCLUDE_FILES = YES # which file to include in order to use the member. # The default value is: NO. -#SHOW_GROUPED_MEMB_INC = NO +SHOW_GROUPED_MEMB_INC = NO # If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include # files with double quotes in the documentation rather than with sharp brackets. @@ -696,7 +787,8 @@ FILE_VERSION_FILTER = # output files in an output format independent way. To create the layout file # that represents doxygen's defaults, run doxygen with the -l option. You can # optionally specify a file name after the option, if omitted DoxygenLayout.xml -# will be used as the name of the layout file. +# will be used as the name of the layout file. See also section "Changing the +# layout of pages" for information. # # Note that if you run doxygen from a directory containing a file called # DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE @@ -742,26 +834,46 @@ WARNINGS = YES WARN_IF_UNDOCUMENTED = YES # If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some parameters -# in a documented function, or documenting parameters that don't exist or using -# markup commands wrongly. +# potential errors in the documentation, such as documenting some parameters in +# a documented function twice, or documenting parameters that don't exist or +# using markup commands wrongly. # The default value is: YES. WARN_IF_DOC_ERROR = YES +# If WARN_IF_INCOMPLETE_DOC is set to YES, doxygen will warn about incomplete +# function parameter documentation. If set to NO, doxygen will accept that some +# parameters have no documentation without warning. +# The default value is: YES. + +WARN_IF_INCOMPLETE_DOC = YES + # This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that # are documented, but have no documentation for their parameters or return -# value. If set to NO, doxygen will only warn about wrong or incomplete -# parameter documentation, but not about the absence of documentation. +# value. If set to NO, doxygen will only warn about wrong parameter +# documentation, but not about the absence of documentation. If EXTRACT_ALL is +# set to YES then this flag will automatically be disabled. See also +# WARN_IF_INCOMPLETE_DOC # The default value is: NO. WARN_NO_PARAMDOC = YES +# If WARN_IF_UNDOC_ENUM_VAL option is set to YES, doxygen will warn about +# undocumented enumeration values. If set to NO, doxygen will accept +# undocumented enumeration values. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: NO. + +WARN_IF_UNDOC_ENUM_VAL = NO + # If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when -# a warning is encountered. +# a warning is encountered. If the WARN_AS_ERROR tag is set to FAIL_ON_WARNINGS +# then doxygen will continue running as if WARN_AS_ERROR tag is set to NO, but +# at the end of the doxygen process doxygen will return with a non-zero status. +# Possible values are: NO, YES and FAIL_ON_WARNINGS. # The default value is: NO. -#WARN_AS_ERROR = NO +WARN_AS_ERROR = NO # The WARN_FORMAT tag determines the format of the warning messages that doxygen # can produce. The string should contain the $file, $line, and $text tags, which @@ -769,13 +881,27 @@ WARN_NO_PARAMDOC = YES # and the warning text. Optionally the format may contain $version, which will # be replaced by the version of the file (if it could be obtained via # FILE_VERSION_FILTER) +# See also: WARN_LINE_FORMAT # The default value is: $file:$line: $text. WARN_FORMAT = "$file:$line: $text" +# In the $text part of the WARN_FORMAT command it is possible that a reference +# to a more specific place is given. To make it easier to jump to this place +# (outside of doxygen) the user can define a custom "cut" / "paste" string. +# Example: +# WARN_LINE_FORMAT = "'vi $file +$line'" +# See also: WARN_FORMAT +# The default value is: at line $line of file $file. + +WARN_LINE_FORMAT = "at line $line of file $file" + # The WARN_LOGFILE tag can be used to specify a file to which warning and error # messages should be written. If left blank the output is written to standard -# error (stderr). +# error (stderr). In case the file specified cannot be opened for writing the +# warning and error messages are written to standard error. When as file - is +# specified the warning and error messages are written to standard output +# (stdout). WARN_LOGFILE = warnings_nrfx.txt @@ -795,7 +921,8 @@ INPUT = ../helpers \ ../drivers \ ../hal \ ../soc \ - ../templates \ + ../templates/nrfx_glue.h \ + ../templates/nrfx_log.h \ ../CHANGELOG.md \ config_dox \ . @@ -803,12 +930,23 @@ INPUT = ../helpers \ # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses # libiconv (or the iconv built into libc) for the transcoding. See the libiconv -# documentation (see: https://www.gnu.org/software/libiconv/) for the list of -# possible encodings. +# documentation (see: +# https://www.gnu.org/software/libiconv/) for the list of possible encodings. +# See also: INPUT_FILE_ENCODING # The default value is: UTF-8. INPUT_ENCODING = UTF-8 +# This tag can be used to specify the character encoding of the source files +# that doxygen parses The INPUT_FILE_ENCODING tag can be used to specify +# character encoding on a per file pattern basis. Doxygen will compare the file +# name with each pattern and apply the encoding instead of the default +# INPUT_ENCODING) if there is a match. The character encodings are a list of the +# form: pattern=encoding (like *.php=ISO-8859-1). See cfg_input_encoding +# "INPUT_ENCODING" for further information on supported encodings. + +INPUT_FILE_ENCODING = + # If the value of the INPUT tag contains directories, you can use the # FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and # *.h) to filter out the source-files in the directories. @@ -817,11 +955,15 @@ INPUT_ENCODING = UTF-8 # need to set EXTENSION_MAPPING for the extension otherwise the files are not # read by doxygen. # +# Note the list of default checked file patterns might differ from the list of +# default file extension mappings. +# # If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, # *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, -# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, -# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, -# *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf and *.qsf. +# *.hh, *.hxx, *.hpp, *.h++, *.l, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, +# *.inc, *.m, *.markdown, *.md, *.mm, *.dox (to be provided as doxygen C +# comment), *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, *.f18, *.f, *.for, *.vhd, +# *.vhdl, *.ucf, *.qsf and *.ice. FILE_PATTERNS = *.h \ *.dox @@ -861,7 +1003,7 @@ EXCLUDE_PATTERNS = # (namespaces, classes, functions, etc.) that should be excluded from the # output. The symbol name can be a fully qualified name, a word, or if the # wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test +# ANamespace::AClass, ANamespace::*Test # # Note that the wildcards are matched against the file with absolute path, so to # exclude all test directories use the pattern */test/* @@ -909,6 +1051,11 @@ IMAGE_PATH = # code is scanned, but not when the output code is generated. If lines are added # or removed, the anchors will not be placed correctly. # +# Note that doxygen will use the data processed and written to standard output +# for further processing, therefore nothing else, like debug statements or used +# commands (so in case of a Windows batch file always use @echo OFF), should be +# written to standard output. +# # Note that for custom extensions or not directly supported extensions you also # need to set EXTENSION_MAPPING for the extension otherwise the files are not # properly processed by doxygen. @@ -950,6 +1097,15 @@ FILTER_SOURCE_PATTERNS = USE_MDFILE_AS_MAINPAGE = +# The Fortran standard specifies that for fixed formatted Fortran code all +# characters from position 72 are to be considered as comment. A common +# extension is to allow longer lines before the automatic comment starts. The +# setting FORTRAN_COMMENT_AFTER will also make it possible that longer lines can +# be processed before the automatic comment starts. +# Minimum value: 7, maximum value: 10000, default value: 72. + +FORTRAN_COMMENT_AFTER = 72 + #--------------------------------------------------------------------------- # Configuration options related to source browsing #--------------------------------------------------------------------------- @@ -977,7 +1133,7 @@ INLINE_SOURCES = NO STRIP_CODE_COMMENTS = NO # If the REFERENCED_BY_RELATION tag is set to YES then for each documented -# function all documented functions referencing it will be listed. +# entity all documented functions referencing it will be listed. # The default value is: NO. REFERENCED_BY_RELATION = NO @@ -1004,7 +1160,7 @@ REFERENCES_LINK_SOURCE = YES # The default value is: YES. # This tag requires that the tag SOURCE_BROWSER is set to YES. -#SOURCE_TOOLTIPS = YES +SOURCE_TOOLTIPS = YES # If the USE_HTAGS tag is set to YES then the references to source code will # point to the HTML generated by the htags(1) tool instead of doxygen built-in @@ -1014,7 +1170,7 @@ REFERENCES_LINK_SOURCE = YES # # To use it do the following: # - Install the latest version of global -# - Enable SOURCE_BROWSER and USE_HTAGS in the config file +# - Enable SOURCE_BROWSER and USE_HTAGS in the configuration file # - Make sure the INPUT points to the root of the source tree # - Run doxygen as normal # @@ -1036,36 +1192,6 @@ USE_HTAGS = NO VERBATIM_HEADERS = NO -# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the -# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the -# cost of reduced performance. This can be particularly helpful with template -# rich C++ code for which doxygen's built-in parser lacks the necessary type -# information. -# Note: The availability of this option depends on whether or not doxygen was -# generated with the -Duse-libclang=ON option for CMake. -# The default value is: NO. - -#CLANG_ASSISTED_PARSING = NO - -# If clang assisted parsing is enabled you can provide the compiler with command -# line options that you would normally use when invoking the compiler. Note that -# the include paths will already be set by doxygen for the files and directories -# specified with INPUT and INCLUDE_PATH. -# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES. - -#CLANG_OPTIONS = - -# If clang assisted parsing is enabled you can provide the clang parser with the -# path to the compilation database (see: -# http://clang.llvm.org/docs/HowToSetupToolingForLLVM.html) used when the files -# were built. This is equivalent to specifying the "-p" option to a clang tool, -# such as clang-check. These options will then be passed to the parser. -# Note: The availability of this option depends on whether or not doxygen was -# generated with the -Duse-libclang=ON option for CMake. -# The default value is: 0. - -#CLANG_COMPILATION_DATABASE_PATH = 0 - #--------------------------------------------------------------------------- # Configuration options related to the alphabetical class index #--------------------------------------------------------------------------- @@ -1077,17 +1203,11 @@ VERBATIM_HEADERS = NO ALPHABETICAL_INDEX = NO -# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in -# which the alphabetical index list will be split. -# Minimum value: 1, maximum value: 20, default value: 5. -# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. - -# COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all classes will -# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag -# can be used to specify a prefix (or a list of prefixes) that should be ignored -# while generating the index headers. +# The IGNORE_PREFIX tag can be used to specify a prefix (or a list of prefixes) +# that should be ignored while generating the index headers. The IGNORE_PREFIX +# tag works for classes, function and member names. The entity will be placed in +# the alphabetical list under the first letter of the entity name that remains +# after removing the prefix. # This tag requires that the tag ALPHABETICAL_INDEX is set to YES. IGNORE_PREFIX = @@ -1166,7 +1286,12 @@ HTML_STYLESHEET = # Doxygen will copy the style sheet files to the output directory. # Note: The order of the extra style sheet files is of importance (e.g. the last # style sheet in the list overrules the setting of the previous ones in the -# list). For an example see the documentation. +# list). +# Note: Since the styling of scrollbars can currently not be overruled in +# Webkit/Chromium, the styling will be left out of the default doxygen.css if +# one or more extra stylesheets have been specified. So if scrollbar +# customization is desired it has to be added explicitly. For an example see the +# documentation. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_EXTRA_STYLESHEET = buildfiles/extra_stylesheet.css @@ -1181,9 +1306,22 @@ HTML_EXTRA_STYLESHEET = buildfiles/extra_stylesheet.css HTML_EXTRA_FILES = buildfiles/favicon.ico +# The HTML_COLORSTYLE tag can be used to specify if the generated HTML output +# should be rendered with a dark or light theme. +# Possible values are: LIGHT always generate light mode output, DARK always +# generate dark mode output, AUTO_LIGHT automatically set the mode according to +# the user preference, use light mode if no preference is set (the default), +# AUTO_DARK automatically set the mode according to the user preference, use +# dark mode if no preference is set and TOGGLE allow to user to switch between +# light and dark mode via a button. +# The default value is: AUTO_LIGHT. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE = AUTO_LIGHT + # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen # will adjust the colors in the style sheet and background images according to -# this color. Hue is specified as an angle on a colorwheel, see +# this color. Hue is specified as an angle on a color-wheel, see # https://en.wikipedia.org/wiki/Hue for more information. For instance the value # 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 # purple, and 360 is red again. @@ -1193,7 +1331,7 @@ HTML_EXTRA_FILES = buildfiles/favicon.ico HTML_COLORSTYLE_HUE = 196 # The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors -# in the HTML output. For a value of 0 the output will use grayscales only. A +# in the HTML output. For a value of 0 the output will use gray-scales only. A # value of 255 will produce the most vivid colors. # Minimum value: 0, maximum value: 255, default value: 100. # This tag requires that the tag GENERATE_HTML is set to YES. @@ -1222,14 +1360,14 @@ HTML_TIMESTAMP = YES # If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML # documentation will contain a main index with vertical navigation menus that -# are dynamically created via Javascript. If disabled, the navigation index will +# are dynamically created via JavaScript. If disabled, the navigation index will # consists of multiple levels of tabs that are statically embedded in every HTML -# page. Disable this option to support browsers that do not have Javascript, +# page. Disable this option to support browsers that do not have JavaScript, # like the Qt help browser. # The default value is: YES. # This tag requires that the tag GENERATE_HTML is set to YES. -#HTML_DYNAMIC_MENUS = YES +HTML_DYNAMIC_MENUS = YES # If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML # documentation will contain sections that can be hidden and shown after the @@ -1254,13 +1392,14 @@ HTML_INDEX_NUM_ENTRIES = 100 # If the GENERATE_DOCSET tag is set to YES, additional index files will be # generated that can be used as input for Apple's Xcode 3 integrated development -# environment (see: https://developer.apple.com/tools/xcode/), introduced with -# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a -# Makefile in the HTML output directory. Running make will produce the docset in -# that directory and running make install will install the docset in +# environment (see: +# https://developer.apple.com/xcode/), introduced with OSX 10.5 (Leopard). To +# create a documentation set, doxygen will generate a Makefile in the HTML +# output directory. Running make will produce the docset in that directory and +# running make install will install the docset in # ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at -# startup. See https://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. +# startup. See https://developer.apple.com/library/archive/featuredarticles/Doxy +# genXcode/_index.html for more information. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. @@ -1274,6 +1413,13 @@ GENERATE_DOCSET = NO DOCSET_FEEDNAME = "Doxygen generated docs" +# This tag determines the URL of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDURL = + # This tag specifies a string that should uniquely identify the documentation # set bundle. This should be a reverse domain-name style string, e.g. # com.mycompany.MyDocSet. Doxygen will append .docset to the name. @@ -1299,8 +1445,12 @@ DOCSET_PUBLISHER_NAME = Publisher # If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three # additional HTML index files: index.hhp, index.hhc, and index.hhk. The # index.hhp is a project file that can be read by Microsoft's HTML Help Workshop -# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on -# Windows. +# on Windows. In the beginning of 2021 Microsoft took the original page, with +# a.o. the download links, offline the HTML help workshop was already many years +# in maintenance mode). You can download the HTML help workshop from the web +# archives at Installation executable (see: +# http://web.archive.org/web/20160201063255/http://download.microsoft.com/downlo +# ad/0/A/9/0A939EF6-E31C-430F-A3DF-DFAE7960D564/htmlhelp.exe). # # The HTML Help Workshop contains a compiler that can convert all HTML output # generated by doxygen into a single compiled HTML file (.chm). Compiled HTML @@ -1330,7 +1480,7 @@ CHM_FILE = HHC_LOCATION = # The GENERATE_CHI flag controls if a separate .chi index file is generated -# (YES) or that it should be included in the master .chm file (NO). +# (YES) or that it should be included in the main .chm file (NO). # The default value is: NO. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. @@ -1375,7 +1525,8 @@ QCH_FILE = # The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help # Project output. For more information please see Qt Help Project / Namespace -# (see: http://doc.qt.io/qt-4.8/qthelpproject.html#namespace). +# (see: +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#namespace). # The default value is: org.doxygen.Project. # This tag requires that the tag GENERATE_QHP is set to YES. @@ -1383,7 +1534,8 @@ QHP_NAMESPACE = org.doxygen.Project # The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt # Help Project output. For more information please see Qt Help Project / Virtual -# Folders (see: http://doc.qt.io/qt-4.8/qthelpproject.html#virtual-folders). +# Folders (see: +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#virtual-folders). # The default value is: doc. # This tag requires that the tag GENERATE_QHP is set to YES. @@ -1391,28 +1543,30 @@ QHP_VIRTUAL_FOLDER = doc # If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom # filter to add. For more information please see Qt Help Project / Custom -# Filters (see: http://doc.qt.io/qt-4.8/qthelpproject.html#custom-filters). +# Filters (see: +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_CUST_FILTER_NAME = # The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the # custom filter to add. For more information please see Qt Help Project / Custom -# Filters (see: http://doc.qt.io/qt-4.8/qthelpproject.html#custom-filters). +# Filters (see: +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_CUST_FILTER_ATTRS = # The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this # project's filter section matches. Qt Help Project / Filter Attributes (see: -# http://doc.qt.io/qt-4.8/qthelpproject.html#filter-attributes). +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#filter-attributes). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_SECT_FILTER_ATTRS = -# The QHG_LOCATION tag can be used to specify the location of Qt's -# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the -# generated .qhp file. +# The QHG_LOCATION tag can be used to specify the location (absolute path +# including file name) of Qt's qhelpgenerator. If non-empty doxygen will try to +# run qhelpgenerator on the generated .qhp file. # This tag requires that the tag GENERATE_QHP is set to YES. QHG_LOCATION = @@ -1457,16 +1611,28 @@ DISABLE_INDEX = YES # to work a browser that supports JavaScript, DHTML, CSS and frames is required # (i.e. any modern browser). Windows users are probably better off using the # HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can -# further fine-tune the look of the index. As an example, the default style -# sheet generated by doxygen has an example that shows how to put an image at -# the root of the tree instead of the PROJECT_NAME. Since the tree basically has -# the same information as the tab index, you could consider setting -# DISABLE_INDEX to YES when enabling this option. +# further fine tune the look of the index (see "Fine-tuning the output"). As an +# example, the default style sheet generated by doxygen has an example that +# shows how to put an image at the root of the tree instead of the PROJECT_NAME. +# Since the tree basically has the same information as the tab index, you could +# consider setting DISABLE_INDEX to YES when enabling this option. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_TREEVIEW = YES +# When both GENERATE_TREEVIEW and DISABLE_INDEX are set to YES, then the +# FULL_SIDEBAR option determines if the side bar is limited to only the treeview +# area (value NO) or if it should extend to the full height of the window (value +# YES). Setting this to YES gives a layout similar to +# https://docs.readthedocs.io with more room for contents, but less room for the +# project logo, title, and description. If either GENERATE_TREEVIEW or +# DISABLE_INDEX is set to NO, this option has no effect. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FULL_SIDEBAR = NO + # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that # doxygen will group on one line in the generated HTML documentation. # @@ -1491,6 +1657,24 @@ TREEVIEW_WIDTH = 250 EXT_LINKS_IN_WINDOW = NO +# If the OBFUSCATE_EMAILS tag is set to YES, doxygen will obfuscate email +# addresses. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +OBFUSCATE_EMAILS = YES + +# If the HTML_FORMULA_FORMAT option is set to svg, doxygen will use the pdf2svg +# tool (see https://github.com/dawbarton/pdf2svg) or inkscape (see +# https://inkscape.org) to generate formulas as SVG images instead of PNGs for +# the HTML output. These images will generally look nicer at scaled resolutions. +# Possible values are: png (the default) and svg (looks nicer but requires the +# pdf2svg or inkscape tool). +# The default value is: png. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FORMULA_FORMAT = png + # Use this tag to change the font size of LaTeX formulas included as images in # the HTML documentation. When you change the font size after a successful # doxygen run you need to manually remove any form_*.png images from the HTML @@ -1500,19 +1684,14 @@ EXT_LINKS_IN_WINDOW = NO FORMULA_FONTSIZE = 10 -# Use the FORMULA_TRANSPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are not -# supported properly for IE 6.0, but are supported on all modern browsers. -# -# Note that when changing this option you need to delete any form_*.png files in -# the HTML output directory before the changes have effect. -# The default value is: YES. -# This tag requires that the tag GENERATE_HTML is set to YES. +# The FORMULA_MACROFILE can contain LaTeX \newcommand and \renewcommand commands +# to create new LaTeX commands to be used in formulas as building blocks. See +# the section "Including formulas" for details. -FORMULA_TRANSPARENT = YES +FORMULA_MACROFILE = # Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# https://www.mathjax.org) which uses client side Javascript for the rendering +# https://www.mathjax.org) which uses client side JavaScript for the rendering # instead of using pre-rendered bitmaps. Use this if you do not have LaTeX # installed or if you want to formulas look prettier in the HTML output. When # enabled you may also need to install MathJax separately and configure the path @@ -1522,11 +1701,29 @@ FORMULA_TRANSPARENT = YES USE_MATHJAX = YES +# With MATHJAX_VERSION it is possible to specify the MathJax version to be used. +# Note that the different versions of MathJax have different requirements with +# regards to the different settings, so it is possible that also other MathJax +# settings have to be changed when switching between the different MathJax +# versions. +# Possible values are: MathJax_2 and MathJax_3. +# The default value is: MathJax_2. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_VERSION = MathJax_2 + # When MathJax is enabled you can set the default output format to be used for -# the MathJax output. See the MathJax site (see: -# http://docs.mathjax.org/en/latest/output.html) for more details. +# the MathJax output. For more details about the output format see MathJax +# version 2 (see: +# http://docs.mathjax.org/en/v2.7-latest/output.html) and MathJax version 3 +# (see: +# http://docs.mathjax.org/en/latest/web/components/output.html). # Possible values are: HTML-CSS (which is slower, but has the best -# compatibility), NativeMML (i.e. MathML) and SVG. +# compatibility. This is the name for Mathjax version 2, for MathJax version 3 +# this will be translated into chtml), NativeMML (i.e. MathML. Only supported +# for NathJax 2. For MathJax version 3 chtml will be used instead.), chtml (This +# is the name for Mathjax version 3, for MathJax version 2 this will be +# translated into HTML-CSS) and SVG. # The default value is: HTML-CSS. # This tag requires that the tag USE_MATHJAX is set to YES. @@ -1539,26 +1736,33 @@ MATHJAX_FORMAT = HTML-CSS # MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax # Content Delivery Network so you can quickly see the result without installing # MathJax. However, it is strongly recommended to install a local copy of -# MathJax from https://www.mathjax.org before deployment. -# The default value is: https://cdnjs.cloudflare.com/ajax/libs/mathjax/2.7.2/. +# MathJax from https://www.mathjax.org before deployment. The default value is: +# - in case of MathJax version 2: https://cdn.jsdelivr.net/npm/mathjax@2 +# - in case of MathJax version 3: https://cdn.jsdelivr.net/npm/mathjax@3 # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest # The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax # extension names that should be enabled during MathJax rendering. For example +# for MathJax version 2 (see +# https://docs.mathjax.org/en/v2.7-latest/tex.html#tex-and-latex-extensions): # MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# For example for MathJax version 3 (see +# http://docs.mathjax.org/en/latest/input/tex/extensions/index.html): +# MATHJAX_EXTENSIONS = ams # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_EXTENSIONS = # The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces # of code that will be used on startup of the MathJax code. See the MathJax site -# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# (see: +# http://docs.mathjax.org/en/v2.7-latest/output.html) for more details. For an # example see the documentation. # This tag requires that the tag USE_MATHJAX is set to YES. -#MATHJAX_CODEFILE = +MATHJAX_CODEFILE = # When the SEARCHENGINE tag is enabled doxygen will generate a search box for # the HTML output. The underlying search engine uses javascript and DHTML and @@ -1582,7 +1786,7 @@ MATHJAX_EXTENSIONS = SEARCHENGINE = YES # When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a web server instead of a web client using Javascript. There +# implemented using a web server instead of a web client using JavaScript. There # are two flavors of web server based searching depending on the EXTERNAL_SEARCH # setting. When disabled, doxygen will generate a PHP script for searching and # an index file used by the script. When EXTERNAL_SEARCH is enabled the indexing @@ -1601,7 +1805,8 @@ SERVER_BASED_SEARCH = NO # # Doxygen ships with an example indexer (doxyindexer) and search engine # (doxysearch.cgi) which are based on the open source search engine library -# Xapian (see: https://xapian.org/). +# Xapian (see: +# https://xapian.org/). # # See the section "External Indexing and Searching" for details. # The default value is: NO. @@ -1614,8 +1819,9 @@ EXTERNAL_SEARCH = NO # # Doxygen ships with an example indexer (doxyindexer) and search engine # (doxysearch.cgi) which are based on the open source search engine library -# Xapian (see: https://xapian.org/). See the section "External Indexing and -# Searching" for details. +# Xapian (see: +# https://xapian.org/). See the section "External Indexing and Searching" for +# details. # This tag requires that the tag SEARCHENGINE is set to YES. SEARCHENGINE_URL = @@ -1666,21 +1872,35 @@ LATEX_OUTPUT = latex # The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be # invoked. # -# Note that when enabling USE_PDFLATEX this option is only used for generating -# bitmaps for formulas in the HTML output, but not in the Makefile that is -# written to the output directory. -# The default file is: latex. +# Note that when not enabling USE_PDFLATEX the default is latex when enabling +# USE_PDFLATEX the default is pdflatex and when in the later case latex is +# chosen this is overwritten by pdflatex. For specific output languages the +# default can have been set differently, this depends on the implementation of +# the output language. # This tag requires that the tag GENERATE_LATEX is set to YES. LATEX_CMD_NAME = latex # The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate # index for LaTeX. +# Note: This tag is used in the Makefile / make.bat. +# See also: LATEX_MAKEINDEX_CMD for the part in the generated output file +# (.tex). # The default file is: makeindex. # This tag requires that the tag GENERATE_LATEX is set to YES. MAKEINDEX_CMD_NAME = makeindex +# The LATEX_MAKEINDEX_CMD tag can be used to specify the command name to +# generate index for LaTeX. In case there is no backslash (\) as first character +# it will be automatically added in the LaTeX code. +# Note: This tag is used in the generated output file (.tex). +# See also: MAKEINDEX_CMD_NAME for the part in the Makefile / make.bat. +# The default value is: makeindex. +# This tag requires that the tag GENERATE_LATEX is set to YES. + +LATEX_MAKEINDEX_CMD = makeindex + # If the COMPACT_LATEX tag is set to YES, doxygen generates more compact LaTeX # documents. This may be useful for small projects and may help to save some # trees in general. @@ -1710,29 +1930,31 @@ PAPER_TYPE = a4 EXTRA_PACKAGES = -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the -# generated LaTeX document. The header should contain everything until the first -# chapter. If it is left blank doxygen will generate a standard header. See -# section "Doxygen usage" for information on how to let doxygen write the -# default header to a separate file. +# The LATEX_HEADER tag can be used to specify a user-defined LaTeX header for +# the generated LaTeX document. The header should contain everything until the +# first chapter. If it is left blank doxygen will generate a standard header. It +# is highly recommended to start with a default header using +# doxygen -w latex new_header.tex new_footer.tex new_stylesheet.sty +# and then modify the file new_header.tex. See also section "Doxygen usage" for +# information on how to generate the default header that doxygen normally uses. # -# Note: Only use a user-defined header if you know what you are doing! The -# following commands have a special meaning inside the header: $title, -# $datetime, $date, $doxygenversion, $projectname, $projectnumber, -# $projectbrief, $projectlogo. Doxygen will replace $title with the empty -# string, for the replacement values of the other commands the user is referred -# to HTML_HEADER. +# Note: Only use a user-defined header if you know what you are doing! +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. The following +# commands have a special meaning inside the header (and footer): For a +# description of the possible markers and block names see the documentation. # This tag requires that the tag GENERATE_LATEX is set to YES. LATEX_HEADER = -# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the -# generated LaTeX document. The footer should contain everything after the last -# chapter. If it is left blank doxygen will generate a standard footer. See +# The LATEX_FOOTER tag can be used to specify a user-defined LaTeX footer for +# the generated LaTeX document. The footer should contain everything after the +# last chapter. If it is left blank doxygen will generate a standard footer. See # LATEX_HEADER for more information on how to generate a default footer and what -# special commands can be used inside the footer. -# -# Note: Only use a user-defined footer if you know what you are doing! +# special commands can be used inside the footer. See also section "Doxygen +# usage" for information on how to generate the default footer that doxygen +# normally uses. Note: Only use a user-defined footer if you know what you are +# doing! # This tag requires that the tag GENERATE_LATEX is set to YES. LATEX_FOOTER = @@ -1746,7 +1968,7 @@ LATEX_FOOTER = # list). # This tag requires that the tag GENERATE_LATEX is set to YES. -#LATEX_EXTRA_STYLESHEET = +LATEX_EXTRA_STYLESHEET = # The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or # other source files which should be copied to the LATEX_OUTPUT output @@ -1754,7 +1976,7 @@ LATEX_FOOTER = # markers available. # This tag requires that the tag GENERATE_LATEX is set to YES. -#LATEX_EXTRA_FILES = +LATEX_EXTRA_FILES = # If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is # prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will @@ -1765,9 +1987,11 @@ LATEX_FOOTER = PDF_HYPERLINKS = YES -# If the USE_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate -# the PDF file directly from the LaTeX files. Set this option to YES, to get a -# higher quality PDF documentation. +# If the USE_PDFLATEX tag is set to YES, doxygen will use the engine as +# specified with LATEX_CMD_NAME to generate the PDF file directly from the LaTeX +# files. Set this option to YES, to get a higher quality PDF documentation. +# +# See also section LATEX_CMD_NAME for selecting the engine. # The default value is: YES. # This tag requires that the tag GENERATE_LATEX is set to YES. @@ -1775,8 +1999,7 @@ USE_PDFLATEX = YES # If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode # command to the generated LaTeX files. This will instruct LaTeX to keep running -# if errors occur, instead of asking the user for help. This option is also used -# when generating formulas in HTML. +# if errors occur, instead of asking the user for help. # The default value is: NO. # This tag requires that the tag GENERATE_LATEX is set to YES. @@ -1803,7 +2026,15 @@ LATEX_BIB_STYLE = plain # The default value is: NO. # This tag requires that the tag GENERATE_LATEX is set to YES. -#LATEX_TIMESTAMP = NO +LATEX_TIMESTAMP = NO + +# The LATEX_EMOJI_DIRECTORY tag is used to specify the (relative or absolute) +# path from which the emoji images will be read. If a relative path is entered, +# it will be relative to the LATEX_OUTPUT directory. If left blank the +# LATEX_OUTPUT directory will be used. +# This tag requires that the tag GENERATE_LATEX is set to YES. + +LATEX_EMOJI_DIRECTORY = #--------------------------------------------------------------------------- # Configuration options related to the RTF output @@ -1844,9 +2075,9 @@ COMPACT_RTF = NO RTF_HYPERLINKS = NO -# Load stylesheet definitions from file. Syntax is similar to doxygen's config -# file, i.e. a series of assignments. You only have to provide replacements, -# missing definitions are set to their default value. +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# configuration file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. # # See also section "Doxygen usage" for information on how to generate the # default style sheet that doxygen normally uses. @@ -1855,22 +2086,12 @@ RTF_HYPERLINKS = NO RTF_STYLESHEET_FILE = # Set optional variables used in the generation of an RTF document. Syntax is -# similar to doxygen's config file. A template extensions file can be generated -# using doxygen -e rtf extensionFile. +# similar to doxygen's configuration file. A template extensions file can be +# generated using doxygen -e rtf extensionFile. # This tag requires that the tag GENERATE_RTF is set to YES. RTF_EXTENSIONS_FILE = -# If the RTF_SOURCE_CODE tag is set to YES then doxygen will include source code -# with syntax highlighting in the RTF output. -# -# Note that which sources are shown also depends on other settings such as -# SOURCE_BROWSER. -# The default value is: NO. -# This tag requires that the tag GENERATE_RTF is set to YES. - -#RTF_SOURCE_CODE = NO - #--------------------------------------------------------------------------- # Configuration options related to the man page output #--------------------------------------------------------------------------- @@ -1904,7 +2125,7 @@ MAN_EXTENSION = .3 # MAN_EXTENSION with the initial . removed. # This tag requires that the tag GENERATE_MAN is set to YES. -#MAN_SUBDIR = +MAN_SUBDIR = # If the MAN_LINKS tag is set to YES and doxygen generates man output, then it # will generate one additional man file for each entity documented in the real @@ -1942,6 +2163,13 @@ XML_OUTPUT = xml XML_PROGRAMLISTING = YES +# If the XML_NS_MEMB_FILE_SCOPE tag is set to YES, doxygen will include +# namespace members in file scope as well, matching the HTML output. +# The default value is: NO. +# This tag requires that the tag GENERATE_XML is set to YES. + +XML_NS_MEMB_FILE_SCOPE = NO + #--------------------------------------------------------------------------- # Configuration options related to the DOCBOOK output #--------------------------------------------------------------------------- @@ -1950,7 +2178,7 @@ XML_PROGRAMLISTING = YES # that can be used to generate PDF. # The default value is: NO. -#GENERATE_DOCBOOK = NO +GENERATE_DOCBOOK = NO # The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be put in @@ -1958,16 +2186,7 @@ XML_PROGRAMLISTING = YES # The default directory is: docbook. # This tag requires that the tag GENERATE_DOCBOOK is set to YES. -#DOCBOOK_OUTPUT = docbook - -# If the DOCBOOK_PROGRAMLISTING tag is set to YES, doxygen will include the -# program listings (including syntax highlighting and cross-referencing -# information) to the DOCBOOK output. Note that enabling this will significantly -# increase the size of the DOCBOOK output. -# The default value is: NO. -# This tag requires that the tag GENERATE_DOCBOOK is set to YES. - -#DOCBOOK_PROGRAMLISTING = NO +DOCBOOK_OUTPUT = docbook #--------------------------------------------------------------------------- # Configuration options for the AutoGen Definitions output @@ -2055,7 +2274,8 @@ SEARCH_INCLUDES = YES # The INCLUDE_PATH tag can be used to specify one or more directories that # contain include files that are not input files but should be processed by the -# preprocessor. +# preprocessor. Note that the INCLUDE_PATH is not recursive, so the setting of +# RECURSIVE has no effect here. # This tag requires that the tag SEARCH_INCLUDES is set to YES. INCLUDE_PATH = @@ -2144,42 +2364,18 @@ EXTERNAL_GROUPS = NO # be listed. # The default value is: YES. -#EXTERNAL_PAGES = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of 'which perl'). -# The default file (with absolute path) is: /usr/bin/perl. - -# PERL_PATH = /usr/bin/perl +EXTERNAL_PAGES = YES #--------------------------------------------------------------------------- # Configuration options related to the dot tool #--------------------------------------------------------------------------- -# If the CLASS_DIAGRAMS tag is set to YES, doxygen will generate a class diagram -# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to -# NO turns the diagrams off. Note that this option also works with HAVE_DOT -# disabled, but it is recommended to install and use dot, since it yields more -# powerful graphs. -# The default value is: YES. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see: -# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -# MSCGEN_PATH = - # You can include diagrams made with dia in doxygen documentation. Doxygen will # then run dia to produce the diagram and insert it in the documentation. The # DIA_PATH tag allows you to specify the directory where the dia binary resides. # If left empty dia is assumed to be found in the default search path. -#DIA_PATH = +DIA_PATH = # If set to YES the inheritance and collaboration graphs will hide inheritance # and usage relations if the target is undocumented or is not a class. @@ -2206,35 +2402,50 @@ HAVE_DOT = NO DOT_NUM_THREADS = 0 -# When you want a differently looking font in the dot files that doxygen -# generates you can specify the font name using DOT_FONTNAME. You need to make -# sure dot is able to find the font, which can be done by putting it in a -# standard location or by setting the DOTFONTPATH environment variable or by -# setting DOT_FONTPATH to the directory containing the font. -# The default value is: Helvetica. +# DOT_COMMON_ATTR is common attributes for nodes, edges and labels of +# subgraphs. When you want a differently looking font in the dot files that +# doxygen generates you can specify fontname, fontcolor and fontsize attributes. +# For details please see Node, +# Edge and Graph Attributes specification You need to make sure dot is able +# to find the font, which can be done by putting it in a standard location or by +# setting the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the +# directory containing the font. Default graphviz fontsize is 14. +# The default value is: fontname=Helvetica,fontsize=10. +# This tag requires that the tag HAVE_DOT is set to YES. + +DOT_COMMON_ATTR = "fontname=Helvetica,fontsize=10" + +# DOT_EDGE_ATTR is concatenated with DOT_COMMON_ATTR. For elegant style you can +# add 'arrowhead=open, arrowtail=open, arrowsize=0.5'. Complete documentation about +# arrows shapes. +# The default value is: labelfontname=Helvetica,labelfontsize=10. # This tag requires that the tag HAVE_DOT is set to YES. -DOT_FONTNAME = Helvetica +DOT_EDGE_ATTR = "labelfontname=Helvetica,labelfontsize=10" -# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of -# dot graphs. -# Minimum value: 4, maximum value: 24, default value: 10. +# DOT_NODE_ATTR is concatenated with DOT_COMMON_ATTR. For view without boxes +# around nodes set 'shape=plain' or 'shape=plaintext' Shapes specification +# The default value is: shape=box,height=0.2,width=0.4. # This tag requires that the tag HAVE_DOT is set to YES. -DOT_FONTSIZE = 10 +DOT_NODE_ATTR = "shape=box,height=0.2,width=0.4" -# By default doxygen will tell dot to use the default font as specified with -# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set -# the path where dot can find it using this tag. +# You can set the path where dot can find font specified with fontname in +# DOT_COMMON_ATTR and others dot attributes. # This tag requires that the tag HAVE_DOT is set to YES. DOT_FONTPATH = -# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for -# each documented class showing the direct and indirect inheritance relations. -# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO. +# If the CLASS_GRAPH tag is set to YES (or GRAPH) then doxygen will generate a +# graph for each documented class showing the direct and indirect inheritance +# relations. In case HAVE_DOT is set as well dot will be used to draw the graph, +# otherwise the built-in generator will be used. If the CLASS_GRAPH tag is set +# to TEXT the direct and indirect inheritance relations will be shown as texts / +# links. +# Possible values are: NO, YES, TEXT and GRAPH. # The default value is: YES. -# This tag requires that the tag HAVE_DOT is set to YES. CLASS_GRAPH = YES @@ -2248,7 +2459,8 @@ CLASS_GRAPH = YES COLLABORATION_GRAPH = YES # If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for -# groups, showing the direct groups dependencies. +# groups, showing the direct groups dependencies. See also the chapter Grouping +# in the manual. # The default value is: YES. # This tag requires that the tag HAVE_DOT is set to YES. @@ -2271,10 +2483,32 @@ UML_LOOK = NO # but if the number exceeds 15, the total amount of fields shown is limited to # 10. # Minimum value: 0, maximum value: 100, default value: 10. -# This tag requires that the tag HAVE_DOT is set to YES. +# This tag requires that the tag UML_LOOK is set to YES. UML_LIMIT_NUM_FIELDS = 10 +# If the DOT_UML_DETAILS tag is set to NO, doxygen will show attributes and +# methods without types and arguments in the UML graphs. If the DOT_UML_DETAILS +# tag is set to YES, doxygen will add type and arguments for attributes and +# methods in the UML graphs. If the DOT_UML_DETAILS tag is set to NONE, doxygen +# will not generate fields with class member information in the UML graphs. The +# class diagrams will look similar to the default class diagrams but using UML +# notation for the relationships. +# Possible values are: NO, YES and NONE. +# The default value is: NO. +# This tag requires that the tag UML_LOOK is set to YES. + +DOT_UML_DETAILS = NO + +# The DOT_WRAP_THRESHOLD tag can be used to set the maximum number of characters +# to display on a single line. If the actual line length exceeds this threshold +# significantly it will wrapped across multiple lines. Some heuristics are apply +# to avoid ugly line breaks. +# Minimum value: 0, maximum value: 1000, default value: 17. +# This tag requires that the tag HAVE_DOT is set to YES. + +DOT_WRAP_THRESHOLD = 17 + # If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and # collaboration graphs will show the relations between templates and their # instances. @@ -2341,6 +2575,13 @@ GRAPHICAL_HIERARCHY = YES DIRECTORY_GRAPH = YES +# The DIR_GRAPH_MAX_DEPTH tag can be used to limit the maximum number of levels +# of child directories generated in directory dependency graphs by dot. +# Minimum value: 1, maximum value: 25, default value: 1. +# This tag requires that the tag DIRECTORY_GRAPH is set to YES. + +DIR_GRAPH_MAX_DEPTH = 1 + # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images # generated by dot. For an explanation of the image formats see the section # output formats in the documentation of the dot tool (Graphviz (see: @@ -2391,25 +2632,25 @@ MSCFILE_DIRS = # contain dia files that are included in the documentation (see the \diafile # command). -#DIAFILE_DIRS = +DIAFILE_DIRS = # When using plantuml, the PLANTUML_JAR_PATH tag should be used to specify the -# path where java can find the plantuml.jar file. If left blank, it is assumed -# PlantUML is not used or called during a preprocessing step. Doxygen will -# generate a warning when it encounters a \startuml command in this case and -# will not generate output for the diagram. +# path where java can find the plantuml.jar file or to the filename of jar file +# to be used. If left blank, it is assumed PlantUML is not used or called during +# a preprocessing step. Doxygen will generate a warning when it encounters a +# \startuml command in this case and will not generate output for the diagram. -#PLANTUML_JAR_PATH = +PLANTUML_JAR_PATH = # When using plantuml, the PLANTUML_CFG_FILE tag can be used to specify a # configuration file for plantuml. -#PLANTUML_CFG_FILE = +PLANTUML_CFG_FILE = # When using plantuml, the specified paths are searched for files specified by # the !include statement in a plantuml block. -#PLANTUML_INCLUDE_PATH = +PLANTUML_INCLUDE_PATH = # The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes # that will be shown in the graph. If the number of nodes in a graph becomes @@ -2435,18 +2676,6 @@ DOT_GRAPH_MAX_NODES = 50 MAX_DOT_GRAPH_DEPTH = 0 -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not seem -# to support this out of the box. -# -# Warning: Depending on the platform used, enabling this option may lead to -# badly anti-aliased labels on the edges of a graph (i.e. they become hard to -# read). -# The default value is: NO. -# This tag requires that the tag HAVE_DOT is set to YES. - -DOT_TRANSPARENT = NO - # Set the DOT_MULTI_TARGETS tag to YES to allow dot to generate multiple output # files in one run (i.e. multiple -o and -T options on the command line). This # makes dot run faster, but since only newer versions of dot (>1.8.10) support @@ -2459,14 +2688,18 @@ DOT_MULTI_TARGETS = NO # If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page # explaining the meaning of the various boxes and arrows in the dot generated # graphs. +# Note: This tag requires that UML_LOOK isn't set, i.e. the doxygen internal +# graphical representation for inheritance and collaboration diagrams is used. # The default value is: YES. # This tag requires that the tag HAVE_DOT is set to YES. GENERATE_LEGEND = YES -# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate dot +# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate # files that are used to generate the various graphs. +# +# Note: This setting is not only used for dot files but also for msc temporary +# files. # The default value is: YES. -# This tag requires that the tag HAVE_DOT is set to YES. DOT_CLEANUP = YES diff --git a/doc/sphinx/drv_supp_matrix.rst b/doc/sphinx/drv_supp_matrix.rst index 0f8b71c89..4c15fe591 100644 --- a/doc/sphinx/drv_supp_matrix.rst +++ b/doc/sphinx/drv_supp_matrix.rst @@ -12,7 +12,7 @@ Driver support overview nrf52833 nrf52840 nrf5340 - nrf9160 + nrf91_series .. role:: red .. role:: green diff --git a/doc/sphinx/nrf9160.rst b/doc/sphinx/nrf9160.rst deleted file mode 100644 index 720254113..000000000 --- a/doc/sphinx/nrf9160.rst +++ /dev/null @@ -1,5 +0,0 @@ -nRF9160 drivers -=============== - -.. doxygenpage:: nrf9160_drivers - :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrf91_series.rst b/doc/sphinx/nrf91_series.rst new file mode 100644 index 000000000..21dcdf99f --- /dev/null +++ b/doc/sphinx/nrf91_series.rst @@ -0,0 +1,5 @@ +nRF91 Series drivers +==================== + +.. doxygenpage:: nrf91_series_drivers + :content-only: \ No newline at end of file diff --git a/drivers/include/nrf_bitmask.h b/drivers/include/nrf_bitmask.h index 0c840927f..757ec080f 100644 --- a/drivers/include/nrf_bitmask.h +++ b/drivers/include/nrf_bitmask.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_adc.h b/drivers/include/nrfx_adc.h index 9dc4dbc2d..4665519bb 100644 --- a/drivers/include/nrfx_adc.h +++ b/drivers/include/nrfx_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_clock.h b/drivers/include/nrfx_clock.h index ec6d1c391..20f3dc39b 100644 --- a/drivers/include/nrfx_clock.h +++ b/drivers/include/nrfx_clock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -119,7 +119,8 @@ void nrfx_clock_stop(nrf_clock_domain_t domain); */ NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src); -#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M || \ + defined(__NRFX_DOXYGEN__) /** * @brief Function for setting the specified clock domain divider. * @@ -193,7 +194,7 @@ NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void); NRFX_STATIC_INLINE bool nrfx_clock_hfclk_is_running(void); -#if NRF_CLOCK_HAS_HFCLKAUDIO +#if NRF_CLOCK_HAS_HFCLKAUDIO || defined(__NRFX_DOXYGEN__) /** * @brief Function for setting the HFCLKAUDIO configuration. * @@ -273,7 +274,7 @@ NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event); #ifndef NRFX_DECLARE_ONLY -#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M NRFX_STATIC_INLINE nrf_clock_hfclk_div_t nrfx_clock_divider_get(nrf_clock_domain_t domain) { switch (domain) @@ -291,7 +292,7 @@ NRFX_STATIC_INLINE nrf_clock_hfclk_div_t nrfx_clock_divider_get(nrf_clock_domain return (nrf_clock_hfclk_div_t)0; } } -#endif // defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M +#endif // defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M NRFX_STATIC_INLINE void nrfx_clock_lfclk_start(void) { diff --git a/drivers/include/nrfx_comp.h b/drivers/include/nrfx_comp.h index 45b49af82..9d7e5f2b7 100644 --- a/drivers/include/nrfx_comp.h +++ b/drivers/include/nrfx_comp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_dppi.h b/drivers/include/nrfx_dppi.h index a99a28e2e..827609393 100644 --- a/drivers/include/nrfx_dppi.h +++ b/drivers/include/nrfx_dppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_egu.h b/drivers/include/nrfx_egu.h index df894c6ea..d4830c775 100644 --- a/drivers/include/nrfx_egu.h +++ b/drivers/include/nrfx_egu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_gpiote.h b/drivers/include/nrfx_gpiote.h index 85a7158a5..42f8ed0df 100644 --- a/drivers/include/nrfx_gpiote.h +++ b/drivers/include/nrfx_gpiote.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -771,7 +771,7 @@ void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin); void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin); #endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) -#if NRF_GPIOTE_HAS_LATENCY +#if NRF_GPIOTE_HAS_LATENCY || defined(__NRFX_DOXYGEN__) /** * @brief Function for setting the latency setting. * diff --git a/drivers/include/nrfx_i2s.h b/drivers/include/nrfx_i2s.h index 065fe170c..0a9c292e5 100644 --- a/drivers/include/nrfx_i2s.h +++ b/drivers/include/nrfx_i2s.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -78,7 +78,7 @@ typedef struct nrf_i2s_channels_t channels; ///< Enabled channels. nrf_i2s_mck_t mck_setup; ///< Master clock setup. nrf_i2s_ratio_t ratio; ///< MCK/LRCK ratio. -#if NRF_I2S_HAS_CLKCONFIG +#if NRF_I2S_HAS_CLKCONFIG || defined(__NRFX_DOXYGEN__) nrf_i2s_clksrc_t clksrc; ///< Clock source selection. bool enable_bypass; ///< Bypass clock generator. MCK will be equal to source input. #endif diff --git a/drivers/include/nrfx_ipc.h b/drivers/include/nrfx_ipc.h index 85f4aacd1..56904f118 100644 --- a/drivers/include/nrfx_ipc.h +++ b/drivers/include/nrfx_ipc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_lpcomp.h b/drivers/include/nrfx_lpcomp.h index a994010e0..a16c285cc 100644 --- a/drivers/include/nrfx_lpcomp.h +++ b/drivers/include/nrfx_lpcomp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_nfct.h b/drivers/include/nrfx_nfct.h index 307c44417..c0d1d8388 100644 --- a/drivers/include/nrfx_nfct.h +++ b/drivers/include/nrfx_nfct.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_nvmc.h b/drivers/include/nrfx_nvmc.h index 28cef860d..daff15029 100644 --- a/drivers/include/nrfx_nvmc.h +++ b/drivers/include/nrfx_nvmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -85,7 +85,7 @@ nrfx_err_t nrfx_nvmc_uicr_erase(void); */ void nrfx_nvmc_all_erase(void); -#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) +#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) || defined(__NRFX_DOXYGEN__) /** * @brief Function for initiating a complete page erase split into parts (also known as partial erase). * @@ -124,7 +124,7 @@ nrfx_err_t nrfx_nvmc_page_partial_erase_init(uint32_t address, uint32_t duration */ bool nrfx_nvmc_page_partial_erase_continue(void); -#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) +#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) || defined(__NRFX_DOXYGEN__) /** * @brief Function for checking whether a byte is writable at the specified address. @@ -306,7 +306,7 @@ uint32_t nrfx_nvmc_flash_page_count_get(void); */ NRFX_STATIC_INLINE bool nrfx_nvmc_write_done_check(void); -#if defined(NVMC_FEATURE_CACHE_PRESENT) +#if defined(NVMC_FEATURE_CACHE_PRESENT) || defined(__NRFX_DOXYGEN__) /** * @brief Function for enabling the Instruction Cache (ICache). * @@ -318,7 +318,7 @@ NRFX_STATIC_INLINE void nrfx_nvmc_icache_enable(void); /** @brief Function for disabling ICache. */ NRFX_STATIC_INLINE void nrfx_nvmc_icache_disable(void); -#endif // defined(NVMC_FEATURE_CACHE_PRESENT) +#endif #ifndef NRFX_DECLARE_ONLY NRFX_STATIC_INLINE bool nrfx_nvmc_write_done_check(void) diff --git a/drivers/include/nrfx_pdm.h b/drivers/include/nrfx_pdm.h index 0aa926e4e..cdfb882cf 100644 --- a/drivers/include/nrfx_pdm.h +++ b/drivers/include/nrfx_pdm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -77,10 +77,10 @@ typedef struct nrf_pdm_gain_t gain_l; ///< Left channel gain. nrf_pdm_gain_t gain_r; ///< Right channel gain. uint8_t interrupt_priority; ///< Interrupt priority. -#if NRF_PDM_HAS_RATIO_CONFIG +#if NRF_PDM_HAS_RATIO_CONFIG || defined(__NRFX_DOXYGEN__) nrf_pdm_ratio_t ratio; ///< Ratio between PDM_CLK and output sample rate. #endif -#if NRF_PDM_HAS_MCLKCONFIG +#if NRF_PDM_HAS_MCLKCONFIG || defined(__NRFX_DOXYGEN__) nrf_pdm_mclksrc_t mclksrc; ///< Master clock source selection. #endif bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. diff --git a/drivers/include/nrfx_power.h b/drivers/include/nrfx_power.h index dabbb6274..51713f3a5 100644 --- a/drivers/include/nrfx_power.h +++ b/drivers/include/nrfx_power.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_power_clock.h b/drivers/include/nrfx_power_clock.h index 87ee8ca82..86efa4082 100644 --- a/drivers/include/nrfx_power_clock.h +++ b/drivers/include/nrfx_power_clock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_power_compat.h b/drivers/include/nrfx_power_compat.h index adf332afa..2af670fcf 100644 --- a/drivers/include/nrfx_power_compat.h +++ b/drivers/include/nrfx_power_compat.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_ppi.h b/drivers/include/nrfx_ppi.h index c8360fef9..f8ec329ba 100644 --- a/drivers/include/nrfx_ppi.h +++ b/drivers/include/nrfx_ppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_pwm.h b/drivers/include/nrfx_pwm.h index 519fb4fa7..858ca06f0 100644 --- a/drivers/include/nrfx_pwm.h +++ b/drivers/include/nrfx_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_qdec.h b/drivers/include/nrfx_qdec.h index d78f4c9d7..ca991e91a 100644 --- a/drivers/include/nrfx_qdec.h +++ b/drivers/include/nrfx_qdec.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_qspi.h b/drivers/include/nrfx_qspi.h index ca4c7285f..e51f01924 100644 --- a/drivers/include/nrfx_qspi.h +++ b/drivers/include/nrfx_qspi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -424,7 +424,7 @@ nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer, size_t transfer_length, bool finalize); -#if NRF_QSPI_HAS_XIP_ENC +#if NRF_QSPI_HAS_XIP_ENC || defined(__NRFX_DOXYGEN__) /** * @brief Function for setting the XIP encryption. * @@ -437,7 +437,7 @@ nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer, nrfx_err_t nrfx_qspi_xip_encrypt(nrf_qspi_encryption_t const * p_config); #endif -#if NRF_QSPI_HAS_DMA_ENC +#if NRF_QSPI_HAS_DMA_ENC || defined(__NRFX_DOXYGEN__) /** * @brief Function for setting the EasyDMA encryption. * diff --git a/drivers/include/nrfx_rng.h b/drivers/include/nrfx_rng.h index b9f7402dd..fd1b2f33c 100644 --- a/drivers/include/nrfx_rng.h +++ b/drivers/include/nrfx_rng.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_rtc.h b/drivers/include/nrfx_rtc.h index ef5ee0d3c..62bd02bda 100644 --- a/drivers/include/nrfx_rtc.h +++ b/drivers/include/nrfx_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_saadc.h b/drivers/include/nrfx_saadc.h index 6dc9d4590..9cdc35571 100644 --- a/drivers/include/nrfx_saadc.h +++ b/drivers/include/nrfx_saadc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_spi.h b/drivers/include/nrfx_spi.h index 966092ad5..8ec85fb8f 100644 --- a/drivers/include/nrfx_spi.h +++ b/drivers/include/nrfx_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_spim.h b/drivers/include/nrfx_spim.h index ad3f3312f..a33b89df0 100644 --- a/drivers/include/nrfx_spim.h +++ b/drivers/include/nrfx_spim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_spis.h b/drivers/include/nrfx_spis.h index 363d5c95e..e139c4ac4 100644 --- a/drivers/include/nrfx_spis.h +++ b/drivers/include/nrfx_spis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_systick.h b/drivers/include/nrfx_systick.h index 49763f9cf..003f4558f 100644 --- a/drivers/include/nrfx_systick.h +++ b/drivers/include/nrfx_systick.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_temp.h b/drivers/include/nrfx_temp.h index 4e07e269a..267aad3ff 100644 --- a/drivers/include/nrfx_temp.h +++ b/drivers/include/nrfx_temp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_timer.h b/drivers/include/nrfx_timer.h index 8781b73d6..910c50337 100644 --- a/drivers/include/nrfx_timer.h +++ b/drivers/include/nrfx_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_twi.h b/drivers/include/nrfx_twi.h index a1e28d703..230a58fe3 100644 --- a/drivers/include/nrfx_twi.h +++ b/drivers/include/nrfx_twi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_twi_twim.h b/drivers/include/nrfx_twi_twim.h index e666ced41..9cc7faa22 100644 --- a/drivers/include/nrfx_twi_twim.h +++ b/drivers/include/nrfx_twi_twim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_twim.h b/drivers/include/nrfx_twim.h index da83ecce9..7c10e7cd6 100644 --- a/drivers/include/nrfx_twim.h +++ b/drivers/include/nrfx_twim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_twis.h b/drivers/include/nrfx_twis.h index 91fc5c907..e47b8b944 100644 --- a/drivers/include/nrfx_twis.h +++ b/drivers/include/nrfx_twis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_uart.h b/drivers/include/nrfx_uart.h index 178aabeb1..d4f81adfd 100644 --- a/drivers/include/nrfx_uart.h +++ b/drivers/include/nrfx_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_uarte.h b/drivers/include/nrfx_uarte.h index 51a0b9156..4a8a4cb56 100644 --- a/drivers/include/nrfx_uarte.h +++ b/drivers/include/nrfx_uarte.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_usbd.h b/drivers/include/nrfx_usbd.h index 9097bb956..3e7463fa2 100644 --- a/drivers/include/nrfx_usbd.h +++ b/drivers/include/nrfx_usbd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_usbreg.h b/drivers/include/nrfx_usbreg.h index 2257829ae..3c07cf52c 100644 --- a/drivers/include/nrfx_usbreg.h +++ b/drivers/include/nrfx_usbreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/include/nrfx_wdt.h b/drivers/include/nrfx_wdt.h index b052b0680..9ca3f8cdd 100644 --- a/drivers/include/nrfx_wdt.h +++ b/drivers/include/nrfx_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/nrfx_common.h b/drivers/nrfx_common.h index 6db8cc7b6..dd5206f2d 100644 --- a/drivers/nrfx_common.h +++ b/drivers/nrfx_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/nrfx_errors.h b/drivers/nrfx_errors.h index a9725e7f1..d5c791cd2 100644 --- a/drivers/nrfx_errors.h +++ b/drivers/nrfx_errors.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_adc.c b/drivers/src/nrfx_adc.c index 83af91a26..f7a103dde 100644 --- a/drivers/src/nrfx_adc.c +++ b/drivers/src/nrfx_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_clock.c b/drivers/src/nrfx_clock.c index 4847d75bc..63d3d438e 100644 --- a/drivers/src/nrfx_clock.c +++ b/drivers/src/nrfx_clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_comp.c b/drivers/src/nrfx_comp.c index aaa7f75eb..821735d1d 100644 --- a/drivers/src/nrfx_comp.c +++ b/drivers/src/nrfx_comp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_dppi.c b/drivers/src/nrfx_dppi.c index 375158036..775a941a8 100644 --- a/drivers/src/nrfx_dppi.c +++ b/drivers/src/nrfx_dppi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_egu.c b/drivers/src/nrfx_egu.c index 7247d84aa..ffe3be865 100644 --- a/drivers/src/nrfx_egu.c +++ b/drivers/src/nrfx_egu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_gpiote.c b/drivers/src/nrfx_gpiote.c index 79015c5a3..9a8679687 100644 --- a/drivers/src/nrfx_gpiote.c +++ b/drivers/src/nrfx_gpiote.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_i2s.c b/drivers/src/nrfx_i2s.c index 2c7b2af92..dd6562702 100644 --- a/drivers/src/nrfx_i2s.c +++ b/drivers/src/nrfx_i2s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -48,7 +48,7 @@ "UNKNOWN EVENT"))) #if !defined(USE_WORKAROUND_FOR_I2S_STOP_ANOMALY) && \ - (defined(NRF52_SERIES) || defined(NRF9160_XXAA)) + (defined(NRF52_SERIES) || defined(NRF91_SERIES)) // Enable workaround for nRF52 Series anomaly 194 / nRF9160 anomaly 1 // (STOP task does not switch off all resources). #define USE_WORKAROUND_FOR_I2S_STOP_ANOMALY 1 diff --git a/drivers/src/nrfx_ipc.c b/drivers/src/nrfx_ipc.c index 16464f846..b8153cf05 100644 --- a/drivers/src/nrfx_ipc.c +++ b/drivers/src/nrfx_ipc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_lpcomp.c b/drivers/src/nrfx_lpcomp.c index 546e54130..c88e0badd 100644 --- a/drivers/src/nrfx_lpcomp.c +++ b/drivers/src/nrfx_lpcomp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_nfct.c b/drivers/src/nrfx_nfct.c index db48a28cb..74dfc06b6 100644 --- a/drivers/src/nrfx_nfct.c +++ b/drivers/src/nrfx_nfct.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_nvmc.c b/drivers/src/nrfx_nvmc.c index 04515780e..44f39e263 100644 --- a/drivers/src/nrfx_nvmc.c +++ b/drivers/src/nrfx_nvmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -58,7 +58,7 @@ * This symbol is needed to determine NVM page count for chips that cannot * always access FICR for this information. */ -#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA_APPLICATION) +#if defined(NRF5340_XXAA_APPLICATION) || defined(NRF9120_XXAA) || defined(NRF9160_XXAA) #define NVMC_FLASH_PAGE_COUNT 256 #elif defined(NRF5340_XXAA_NETWORK) #define NVMC_FLASH_PAGE_COUNT 128 @@ -70,7 +70,7 @@ * This symbol is needed to determine NVM page size for chips that cannot * always access FICR for this information. */ -#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA_APPLICATION) +#if defined(NRF5340_XXAA_APPLICATION) || defined(NRF9120_XXAA) || defined(NRF9160_XXAA) #define NVMC_FLASH_PAGE_SIZE 0x1000 ///< 4 kB #elif defined(NRF5340_XXAA_NETWORK) #define NVMC_FLASH_PAGE_SIZE 0x800 ///< 2 kB @@ -85,8 +85,9 @@ #if defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || \ defined(NRF52811_XXAA) || defined(NRF52840_XXAA) #define NVMC_PAGE_ERASE_DURATION_MS 85 -#elif defined(NRF52820_XXAA) || defined(NRF52833_XXAA) || defined(NRF9160_XXAA) || \ - defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) +#elif defined(NRF52820_XXAA) || defined(NRF52833_XXAA) || \ + defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) || \ + defined(NRF9120_XXAA) || defined(NRF9160_XXAA) #define NVMC_PAGE_ERASE_DURATION_MS 87 #else #error "Page partial erase present but could not determine its total duration for given SoC" @@ -237,7 +238,7 @@ static void nvmc_erase_mode_set(void) static void nvmc_word_write(uint32_t addr, uint32_t value) { -#if defined(NRF9160_XXAA) +#if defined(NRF91_SERIES) while (!nrf_nvmc_write_ready_check(NRF_NVMC)) {} #else diff --git a/drivers/src/nrfx_pdm.c b/drivers/src/nrfx_pdm.c index 7614c983b..ae77b1939 100644 --- a/drivers/src/nrfx_pdm.c +++ b/drivers/src/nrfx_pdm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_power.c b/drivers/src/nrfx_power.c index 06ca885c6..7c27a8140 100644 --- a/drivers/src/nrfx_power.c +++ b/drivers/src/nrfx_power.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_ppi.c b/drivers/src/nrfx_ppi.c index 3efdf1617..4c3e2c5d2 100644 --- a/drivers/src/nrfx_ppi.c +++ b/drivers/src/nrfx_ppi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_pwm.c b/drivers/src/nrfx_pwm.c index b00fe22a6..95aae4c32 100644 --- a/drivers/src/nrfx_pwm.c +++ b/drivers/src/nrfx_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_qdec.c b/drivers/src/nrfx_qdec.c index f5576b2b9..b8054593a 100644 --- a/drivers/src/nrfx_qdec.c +++ b/drivers/src/nrfx_qdec.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_qspi.c b/drivers/src/nrfx_qspi.c index e3ffb6f26..bdd039038 100644 --- a/drivers/src/nrfx_qspi.c +++ b/drivers/src/nrfx_qspi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_rng.c b/drivers/src/nrfx_rng.c index 02da95b71..067bb9532 100644 --- a/drivers/src/nrfx_rng.c +++ b/drivers/src/nrfx_rng.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_rtc.c b/drivers/src/nrfx_rtc.c index 936ab1c82..880e89a32 100644 --- a/drivers/src/nrfx_rtc.c +++ b/drivers/src/nrfx_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_saadc.c b/drivers/src/nrfx_saadc.c index 96d22f214..7de92f2c9 100644 --- a/drivers/src/nrfx_saadc.c +++ b/drivers/src/nrfx_saadc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_spi.c b/drivers/src/nrfx_spi.c index 715f6cd2d..c2338379d 100644 --- a/drivers/src/nrfx_spi.c +++ b/drivers/src/nrfx_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_spim.c b/drivers/src/nrfx_spim.c index 352f334cd..905bf203d 100644 --- a/drivers/src/nrfx_spim.c +++ b/drivers/src/nrfx_spim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_spis.c b/drivers/src/nrfx_spis.c index ffa975caa..6226e6166 100644 --- a/drivers/src/nrfx_spis.c +++ b/drivers/src/nrfx_spis.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2013 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_systick.c b/drivers/src/nrfx_systick.c index dbde7bfa0..88ca1a6a0 100644 --- a/drivers/src/nrfx_systick.c +++ b/drivers/src/nrfx_systick.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_temp.c b/drivers/src/nrfx_temp.c index 4ccd84a35..623273334 100644 --- a/drivers/src/nrfx_temp.c +++ b/drivers/src/nrfx_temp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_timer.c b/drivers/src/nrfx_timer.c index da00b928c..82cb01804 100644 --- a/drivers/src/nrfx_timer.c +++ b/drivers/src/nrfx_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_twi.c b/drivers/src/nrfx_twi.c index 968a4ac3c..3ff66017b 100644 --- a/drivers/src/nrfx_twi.c +++ b/drivers/src/nrfx_twi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_twi_twim.c b/drivers/src/nrfx_twi_twim.c index 1d8f47388..27724b1ab 100644 --- a/drivers/src/nrfx_twi_twim.c +++ b/drivers/src/nrfx_twi_twim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_twim.c b/drivers/src/nrfx_twim.c index aaf110046..a52f3bce6 100644 --- a/drivers/src/nrfx_twim.c +++ b/drivers/src/nrfx_twim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_twis.c b/drivers/src/nrfx_twis.c index 8651fb5fe..3a4a6231b 100644 --- a/drivers/src/nrfx_twis.c +++ b/drivers/src/nrfx_twis.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_uart.c b/drivers/src/nrfx_uart.c index 1f1e528ed..a149ea166 100644 --- a/drivers/src/nrfx_uart.c +++ b/drivers/src/nrfx_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_uarte.c b/drivers/src/nrfx_uarte.c index e492c3a88..ec3cb6425 100644 --- a/drivers/src/nrfx_uarte.c +++ b/drivers/src/nrfx_uarte.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -221,10 +221,10 @@ static void pins_to_default(nrfx_uarte_t const * p_instance) static void apply_workaround_for_enable_anomaly(nrfx_uarte_t const * p_instance) { -#if defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA) +#if defined(NRF53_SERIES) || defined(NRF91_SERIES) // Apply workaround for anomalies: - // - nRF9160 - anomaly 23 - // - nRF5340 - anomaly 44 + // - nRF91 - anomaly 23 + // - nRF53 - anomaly 44 volatile uint32_t const * rxenable_reg = (volatile uint32_t *)(((uint32_t)p_instance->p_reg) + 0x564); volatile uint32_t const * txenable_reg = @@ -256,7 +256,7 @@ static void apply_workaround_for_enable_anomaly(nrfx_uarte_t const * p_instance) } #else (void)(p_instance); -#endif // defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA) +#endif // defined(NRF53_SERIES) || defined(NRF91_SERIES) } nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance, diff --git a/drivers/src/nrfx_usbd.c b/drivers/src/nrfx_usbd.c index a121d73b9..d91db3411 100644 --- a/drivers/src/nrfx_usbd.c +++ b/drivers/src/nrfx_usbd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -1865,8 +1865,6 @@ bool nrfx_usbd_suspend(void) NRFX_CRITICAL_SECTION_ENTER(); if (m_bus_suspend) { - usbd_ep_abort_all(); - if (!(nrf_usbd_eventcause_get(NRF_USBD) & NRF_USBD_EVENTCAUSE_RESUME_MASK)) { nrf_usbd_lowpower_enable(NRF_USBD); diff --git a/drivers/src/nrfx_usbd_errata.h b/drivers/src/nrfx_usbd_errata.h index 1301aaddd..6fc2a3bb5 100644 --- a/drivers/src/nrfx_usbd_errata.h +++ b/drivers/src/nrfx_usbd_errata.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_usbreg.c b/drivers/src/nrfx_usbreg.c index 484807741..d8aeac6e4 100644 --- a/drivers/src/nrfx_usbreg.c +++ b/drivers/src/nrfx_usbreg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/nrfx_wdt.c b/drivers/src/nrfx_wdt.c index b4ffbc173..01344cb88 100644 --- a/drivers/src/nrfx_wdt.c +++ b/drivers/src/nrfx_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/prs/nrfx_prs.c b/drivers/src/prs/nrfx_prs.c index 79258ee84..afd3d4193 100644 --- a/drivers/src/prs/nrfx_prs.c +++ b/drivers/src/prs/nrfx_prs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/drivers/src/prs/nrfx_prs.h b/drivers/src/prs/nrfx_prs.h index cae15ad9a..2a67d930f 100644 --- a/drivers/src/prs/nrfx_prs.h +++ b/drivers/src/prs/nrfx_prs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -100,7 +100,7 @@ extern "C" { #elif defined(NRF5340_XXAA_NETWORK) // SPIM0, SPIS0, TWIM0, TWIS0, UARTE0 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 -#elif defined(NRF9160_XXAA) +#elif defined(NRF91_SERIES) // UARTE0, SPIM0, SPIS0, TWIM0, TWIS0 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 // UARTE1, SPIM1, SPIS1, TWIM1, TWIS1 diff --git a/hal/nrf_aar.h b/hal/nrf_aar.h index d2aa75e37..621332966 100644 --- a/hal/nrf_aar.h +++ b/hal/nrf_aar.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_acl.h b/hal/nrf_acl.h index c30aeb993..392e8846c 100644 --- a/hal/nrf_acl.h +++ b/hal/nrf_acl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_adc.h b/hal/nrf_adc.h index 765f47dbb..ea7a1eb02 100644 --- a/hal/nrf_adc.h +++ b/hal/nrf_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_bprot.h b/hal/nrf_bprot.h index 8cdb8eae0..5e313708e 100644 --- a/hal/nrf_bprot.h +++ b/hal/nrf_bprot.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_cache.h b/hal/nrf_cache.h index 7b161d059..88a943ca2 100644 --- a/hal/nrf_cache.h +++ b/hal/nrf_cache.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_ccm.h b/hal/nrf_ccm.h index 5743231f5..d3a8f2951 100644 --- a/hal/nrf_ccm.h +++ b/hal/nrf_ccm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_clock.h b/hal/nrf_clock.h index ad3a640df..458f913f7 100644 --- a/hal/nrf_clock.h +++ b/hal/nrf_clock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_common.h b/hal/nrf_common.h index 9e3f2cca2..808399e54 100644 --- a/hal/nrf_common.h +++ b/hal/nrf_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -42,7 +42,9 @@ extern "C" { #define NRFX_EVENT_READBACK_ENABLED 1 #endif -#if !defined(NRFX_CONFIG_API_VER_2_9) && !defined(NRFX_CONFIG_API_VER_2_10) +#if !defined(NRFX_CONFIG_API_VER_2_9) && \ + !defined(NRFX_CONFIG_API_VER_2_10) && \ + !defined(NRFX_CONFIG_API_VER_2_11) #define NRFX_CONFIG_API_VER_2_9 1 #endif diff --git a/hal/nrf_comp.h b/hal/nrf_comp.h index 143fde2b2..cb2cc975e 100644 --- a/hal/nrf_comp.h +++ b/hal/nrf_comp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_dcnf.h b/hal/nrf_dcnf.h index 15fba155c..b7f9938e8 100644 --- a/hal/nrf_dcnf.h +++ b/hal/nrf_dcnf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_dppi.h b/hal/nrf_dppi.h index a9f8284a6..a10988d96 100644 --- a/hal/nrf_dppi.h +++ b/hal/nrf_dppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_ecb.h b/hal/nrf_ecb.h index 75d007dcd..ed5c401ca 100644 --- a/hal/nrf_ecb.h +++ b/hal/nrf_ecb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_egu.h b/hal/nrf_egu.h index 9154191f0..6c5780c20 100644 --- a/hal/nrf_egu.h +++ b/hal/nrf_egu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -159,7 +159,7 @@ NRF_STATIC_INLINE uint32_t nrf_egu_task_address_get(NRF_EGU_Type const * p_reg, NRF_STATIC_INLINE nrf_egu_task_t nrf_egu_trigger_task_get(uint8_t channel); /** - * @brief Function for retrieving the state of the UARTE event. + * @brief Function for retrieving the state of the EGU event. * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] egu_event EGU event to be checked. diff --git a/hal/nrf_ficr.h b/hal/nrf_ficr.h index 049513d6f..8fda7bd16 100644 --- a/hal/nrf_ficr.h +++ b/hal/nrf_ficr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_fpu.h b/hal/nrf_fpu.h index 93ad12061..fd75520fb 100644 --- a/hal/nrf_fpu.h +++ b/hal/nrf_fpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_gpio.h b/hal/nrf_gpio.h index 57ab35f50..696b83d3d 100644 --- a/hal/nrf_gpio.h +++ b/hal/nrf_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_gpiote.h b/hal/nrf_gpiote.h index 59050bd41..fe7a1e996 100644 --- a/hal/nrf_gpiote.h +++ b/hal/nrf_gpiote.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -615,7 +615,7 @@ NRF_STATIC_INLINE void nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg, NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx) { p_reg->CONFIG[idx] = 0; -#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA) +#if defined(NRF53_SERIES) || defined(NRF91_SERIES) p_reg->CONFIG[idx] = 0; #endif } diff --git a/hal/nrf_i2s.h b/hal/nrf_i2s.h index f5eb3efb5..aebc2b0e7 100644 --- a/hal/nrf_i2s.h +++ b/hal/nrf_i2s.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_ipc.h b/hal/nrf_ipc.h index 6070b766e..b6773db10 100644 --- a/hal/nrf_ipc.h +++ b/hal/nrf_ipc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_kmu.h b/hal/nrf_kmu.h index ad539f908..c61af62fe 100644 --- a/hal/nrf_kmu.h +++ b/hal/nrf_kmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_lpcomp.h b/hal/nrf_lpcomp.h index b48aa1737..a597e50a8 100644 --- a/hal/nrf_lpcomp.h +++ b/hal/nrf_lpcomp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_mpu.h b/hal/nrf_mpu.h index 16be045c8..ed6b8ef80 100644 --- a/hal/nrf_mpu.h +++ b/hal/nrf_mpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_mutex.h b/hal/nrf_mutex.h index be46b6546..b9c6065ce 100644 --- a/hal/nrf_mutex.h +++ b/hal/nrf_mutex.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_mwu.h b/hal/nrf_mwu.h index 644eeb412..ba5d086d0 100644 --- a/hal/nrf_mwu.h +++ b/hal/nrf_mwu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_nfct.h b/hal/nrf_nfct.h index 137a248b9..a1de3dda9 100644 --- a/hal/nrf_nfct.h +++ b/hal/nrf_nfct.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_nvmc.h b/hal/nrf_nvmc.h index 94d5cf253..78904c68a 100644 --- a/hal/nrf_nvmc.h +++ b/hal/nrf_nvmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -302,7 +302,7 @@ NRF_STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, } #elif defined(NRF52_SERIES) p_reg->ERASEPAGE = page_addr; -#elif defined(NRF9160_XXAA) || defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) +#elif defined(NRF53_SERIES) || defined(NRF91_SERIES) *(volatile uint32_t *)page_addr = 0xFFFFFFFF; (void)p_reg; #else @@ -339,7 +339,7 @@ NRF_STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, { #if defined(NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk) p_reg->ERASEPAGEPARTIAL = page_addr; -#elif defined(NRF9160_XXAA) || defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) +#elif defined(NRF53_SERIES) || defined(NRF91_SERIES) nrf_nvmc_page_erase_start(p_reg, page_addr); #else #error "Unknown device." @@ -351,10 +351,10 @@ NRF_STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, NRF_STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg, nrf_nvmc_icache_config_t config) { -#if defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA) +#if defined(NRF5340_XXAA_NETWORK) || defined(NRF91_SERIES) // Apply workaround for the anomalies: - // - 6 for the nRF5340. - // - 21 for the nRF9160. + // - 6 for the nRF53. + // - 21 for the nRF91. if (config == NRF_NVMC_ICACHE_DISABLE) { NRFX_CRITICAL_SECTION_ENTER(); diff --git a/hal/nrf_oscillators.h b/hal/nrf_oscillators.h index 5390b1621..6ecefacd1 100644 --- a/hal/nrf_oscillators.h +++ b/hal/nrf_oscillators.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_pdm.h b/hal/nrf_pdm.h index afd9e1722..5d866bd93 100644 --- a/hal/nrf_pdm.h +++ b/hal/nrf_pdm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_power.h b/hal/nrf_power.h index 254770c09..ed1899af2 100644 --- a/hal/nrf_power.h +++ b/hal/nrf_power.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_ppi.h b/hal/nrf_ppi.h index 1657bdf77..91f423c10 100644 --- a/hal/nrf_ppi.h +++ b/hal/nrf_ppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_pwm.h b/hal/nrf_pwm.h index 9745a193f..6d7ef154e 100644 --- a/hal/nrf_pwm.h +++ b/hal/nrf_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_qdec.h b/hal/nrf_qdec.h index afaabc0bf..c5dc29bda 100644 --- a/hal/nrf_qdec.h +++ b/hal/nrf_qdec.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_qspi.h b/hal/nrf_qspi.h index f0a8112d2..165ef4932 100644 --- a/hal/nrf_qspi.h +++ b/hal/nrf_qspi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_radio.h b/hal/nrf_radio.h index 20bb8d5aa..3a7eace35 100644 --- a/hal/nrf_radio.h +++ b/hal/nrf_radio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_regulators.h b/hal/nrf_regulators.h index aaa352f35..4a92108dc 100644 --- a/hal/nrf_regulators.h +++ b/hal/nrf_regulators.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_reset.h b/hal/nrf_reset.h index 219192158..be9a17f90 100644 --- a/hal/nrf_reset.h +++ b/hal/nrf_reset.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -35,6 +35,7 @@ #define NRF_RESET_H__ #include +#include #ifdef __cplusplus extern "C" { @@ -136,8 +137,29 @@ NRF_STATIC_INLINE void nrf_reset_resetreas_clear(NRF_RESET_Type * p_reg, uint32_ #if NRF_RESET_HAS_APPLICATION NRF_STATIC_INLINE void nrf_reset_network_force_off(NRF_RESET_Type * p_reg, bool hold) { - p_reg->NETWORK.FORCEOFF = (hold ? RESET_NETWORK_FORCEOFF_FORCEOFF_Hold : - RESET_NETWORK_FORCEOFF_FORCEOFF_Release); + if (hold) + { + p_reg->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Hold << + RESET_NETWORK_FORCEOFF_FORCEOFF_Pos; + } + else if (nrf53_errata_161()) + { + *(volatile uint32_t *)0x50005618UL = 1UL; + p_reg->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release << + RESET_NETWORK_FORCEOFF_FORCEOFF_Pos; + NRFX_DELAY_US(5); + p_reg->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Hold << + RESET_NETWORK_FORCEOFF_FORCEOFF_Pos; + NRFX_DELAY_US(1); + p_reg->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release << + RESET_NETWORK_FORCEOFF_FORCEOFF_Pos; + *(volatile uint32_t *)0x50005618UL = 0UL; + } + else + { + p_reg->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release << + RESET_NETWORK_FORCEOFF_FORCEOFF_Pos; + } } #endif // NRF_RESET_HAS_APPLICATION diff --git a/hal/nrf_rng.h b/hal/nrf_rng.h index 54da5b163..7af014c08 100644 --- a/hal/nrf_rng.h +++ b/hal/nrf_rng.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_rtc.h b/hal/nrf_rtc.h index 126af564c..359cac2b3 100644 --- a/hal/nrf_rtc.h +++ b/hal/nrf_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_saadc.h b/hal/nrf_saadc.h index 89c722913..70c110c23 100644 --- a/hal/nrf_saadc.h +++ b/hal/nrf_saadc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_spi.h b/hal/nrf_spi.h index 39f368c0e..dc37700f3 100644 --- a/hal/nrf_spi.h +++ b/hal/nrf_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_spim.h b/hal/nrf_spim.h index d7cd1ed08..1aaf783da 100644 --- a/hal/nrf_spim.h +++ b/hal/nrf_spim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_spis.h b/hal/nrf_spis.h index 7dc267493..a0275eacf 100644 --- a/hal/nrf_spis.h +++ b/hal/nrf_spis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_spu.h b/hal/nrf_spu.h index 23266a63f..3863c3923 100644 --- a/hal/nrf_spu.h +++ b/hal/nrf_spu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_systick.h b/hal/nrf_systick.h index faa264d73..e66b5977f 100644 --- a/hal/nrf_systick.h +++ b/hal/nrf_systick.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_temp.h b/hal/nrf_temp.h index d254742ed..9c238f400 100644 --- a/hal/nrf_temp.h +++ b/hal/nrf_temp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_timer.h b/hal/nrf_timer.h index e98c7bd6b..a779c190e 100644 --- a/hal/nrf_timer.h +++ b/hal/nrf_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_twi.h b/hal/nrf_twi.h index e86c9d2b3..010fae074 100644 --- a/hal/nrf_twi.h +++ b/hal/nrf_twi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_twim.h b/hal/nrf_twim.h index 3a0d68b28..580c4a725 100644 --- a/hal/nrf_twim.h +++ b/hal/nrf_twim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_twis.h b/hal/nrf_twis.h index 949a5b584..d9a2f4fca 100644 --- a/hal/nrf_twis.h +++ b/hal/nrf_twis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_uart.h b/hal/nrf_uart.h index d40d4cdc9..e9166ff39 100644 --- a/hal/nrf_uart.h +++ b/hal/nrf_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_uarte.h b/hal/nrf_uarte.h index 58c8d3a5b..ad53c4bd1 100644 --- a/hal/nrf_uarte.h +++ b/hal/nrf_uarte.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_usbd.h b/hal/nrf_usbd.h index de37abd7a..c42cf4caf 100644 --- a/hal/nrf_usbd.h +++ b/hal/nrf_usbd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_usbreg.h b/hal/nrf_usbreg.h index 70be39542..1d4b683ca 100644 --- a/hal/nrf_usbreg.h +++ b/hal/nrf_usbreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_vmc.h b/hal/nrf_vmc.h index f610d7501..1f96ea829 100644 --- a/hal/nrf_vmc.h +++ b/hal/nrf_vmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_vreqctrl.h b/hal/nrf_vreqctrl.h index b9a1fd825..5d4af4966 100644 --- a/hal/nrf_vreqctrl.h +++ b/hal/nrf_vreqctrl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/hal/nrf_wdt.h b/hal/nrf_wdt.h index 9cd3a2a12..87e9ae615 100644 --- a/hal/nrf_wdt.h +++ b/hal/nrf_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/helpers/nrfx_flag32_allocator.c b/helpers/nrfx_flag32_allocator.c index 41fdf4c86..35e6ee617 100644 --- a/helpers/nrfx_flag32_allocator.c +++ b/helpers/nrfx_flag32_allocator.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2021 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/helpers/nrfx_flag32_allocator.h b/helpers/nrfx_flag32_allocator.h index d8315480d..979ec56ca 100644 --- a/helpers/nrfx_flag32_allocator.h +++ b/helpers/nrfx_flag32_allocator.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2021 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/helpers/nrfx_gppi.h b/helpers/nrfx_gppi.h index 9555ce267..ab084c438 100644 --- a/helpers/nrfx_gppi.h +++ b/helpers/nrfx_gppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/helpers/nrfx_reset_reason.h b/helpers/nrfx_reset_reason.h index c87758398..5ab1df0bd 100644 --- a/helpers/nrfx_reset_reason.h +++ b/helpers/nrfx_reset_reason.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/arm_startup_nrf51.s b/mdk/arm_startup_nrf51.s index 8e7895978..f239781e7 100644 --- a/mdk/arm_startup_nrf51.s +++ b/mdk/arm_startup_nrf51.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52.s b/mdk/arm_startup_nrf52.s index d727f6c23..da8499d18 100644 --- a/mdk/arm_startup_nrf52.s +++ b/mdk/arm_startup_nrf52.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52805.s b/mdk/arm_startup_nrf52805.s index a42334564..8bf400226 100644 --- a/mdk/arm_startup_nrf52805.s +++ b/mdk/arm_startup_nrf52805.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52810.s b/mdk/arm_startup_nrf52810.s index 12be9a613..350b5c6f5 100644 --- a/mdk/arm_startup_nrf52810.s +++ b/mdk/arm_startup_nrf52810.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52811.s b/mdk/arm_startup_nrf52811.s index 63dd406d6..2d8df8cbe 100644 --- a/mdk/arm_startup_nrf52811.s +++ b/mdk/arm_startup_nrf52811.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52820.s b/mdk/arm_startup_nrf52820.s index a2ca2adfa..0ca014fec 100644 --- a/mdk/arm_startup_nrf52820.s +++ b/mdk/arm_startup_nrf52820.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52833.s b/mdk/arm_startup_nrf52833.s index c2216a344..caabb82f3 100644 --- a/mdk/arm_startup_nrf52833.s +++ b/mdk/arm_startup_nrf52833.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52840.s b/mdk/arm_startup_nrf52840.s index 940f84de9..26a6282e2 100644 --- a/mdk/arm_startup_nrf52840.s +++ b/mdk/arm_startup_nrf52840.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf5340_application.s b/mdk/arm_startup_nrf5340_application.s index e96c154fd..35ceeda08 100644 --- a/mdk/arm_startup_nrf5340_application.s +++ b/mdk/arm_startup_nrf5340_application.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf5340_network.s b/mdk/arm_startup_nrf5340_network.s index d19edce3e..1a6528077 100644 --- a/mdk/arm_startup_nrf5340_network.s +++ b/mdk/arm_startup_nrf5340_network.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf9120.s b/mdk/arm_startup_nrf9120.s new file mode 100644 index 000000000..900883b45 --- /dev/null +++ b/mdk/arm_startup_nrf9120.s @@ -0,0 +1,492 @@ +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + + IF :DEF: __STARTUP_CONFIG +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE + ELIF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 15872 + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT + ELSE +Stack_Align EQU 3 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align +Stack_Mem SPACE Stack_Size +__initial_sp + + IF :DEF: __STARTUP_CONFIG +Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE + ELIF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 15872 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD SecureFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU_IRQHandler + DCD 0 ; Reserved + DCD CLOCK_POWER_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + DCD 0 ; Reserved + DCD GPIOTE0_IRQHandler + DCD SAADC_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RTC0_IRQHandler + DCD RTC1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WDT_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EGU0_IRQHandler + DCD EGU1_IRQHandler + DCD EGU2_IRQHandler + DCD EGU3_IRQHandler + DCD EGU4_IRQHandler + DCD EGU5_IRQHandler + DCD PWM0_IRQHandler + DCD PWM1_IRQHandler + DCD PWM2_IRQHandler + DCD PWM3_IRQHandler + DCD 0 ; Reserved + DCD PDM_IRQHandler + DCD 0 ; Reserved + DCD I2S_IRQHandler + DCD 0 ; Reserved + DCD IPC_IRQHandler + DCD 0 ; Reserved + DCD FPU_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD GPIOTE1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD KMU_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CRYPTOCELL_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SecureFault_Handler\ + PROC + EXPORT SecureFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT SPU_IRQHandler [WEAK] + EXPORT CLOCK_POWER_IRQHandler [WEAK] + EXPORT SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler [WEAK] + EXPORT SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler [WEAK] + EXPORT SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler [WEAK] + EXPORT SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler [WEAK] + EXPORT GPIOTE0_IRQHandler [WEAK] + EXPORT SAADC_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT RTC1_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT EGU0_IRQHandler [WEAK] + EXPORT EGU1_IRQHandler [WEAK] + EXPORT EGU2_IRQHandler [WEAK] + EXPORT EGU3_IRQHandler [WEAK] + EXPORT EGU4_IRQHandler [WEAK] + EXPORT EGU5_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT PDM_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT IPC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT GPIOTE1_IRQHandler [WEAK] + EXPORT KMU_IRQHandler [WEAK] + EXPORT CRYPTOCELL_IRQHandler [WEAK] +SPU_IRQHandler +CLOCK_POWER_IRQHandler +SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +GPIOTE0_IRQHandler +SAADC_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +WDT_IRQHandler +EGU0_IRQHandler +EGU1_IRQHandler +EGU2_IRQHandler +EGU3_IRQHandler +EGU4_IRQHandler +EGU5_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +PDM_IRQHandler +I2S_IRQHandler +IPC_IRQHandler +FPU_IRQHandler +GPIOTE1_IRQHandler +KMU_IRQHandler +CRYPTOCELL_IRQHandler + B . + ENDP + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/mdk/arm_startup_nrf9160.s b/mdk/arm_startup_nrf9160.s index ab461044f..900883b45 100644 --- a/mdk/arm_startup_nrf9160.s +++ b/mdk/arm_startup_nrf9160.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/compiler_abstraction.h b/mdk/compiler_abstraction.h index 0503aa3f6..628faf506 100644 --- a/mdk/compiler_abstraction.h +++ b/mdk/compiler_abstraction.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -70,11 +70,47 @@ POSSIBILITY OF SUCH DAMAGE. #define __UNUSED __attribute__((unused)) #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + + #ifndef __HANDLER + #define __HANDLER(handler) + #endif + #define GET_SP() __current_sp() #ifndef __DEPRECATED #define __DEPRECATED(msg) __attribute__((deprecated(msg))) #endif + + #ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) + #endif + + #ifndef __RESET_HANDLER_ATTRIBUTE + #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN + #endif + + #ifndef __START + #define __START __main + #endif + + #ifndef __VECTOR_TABLE + #define __VECTOR_TABLE __Vectors + #endif + + #ifndef __VECTOR_TABLE_ATTRIBUTE + #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) + #endif + + #ifndef __STACK_ATTRIBUTES + #define __STACK_ATTRIBUTES(align) + #endif + + #ifndef __HEAP_ATTRIBUTES + #define __HEAP_ATTRIBUTES(align) + #endif #ifndef NRF_STATIC_ASSERT #define NRF_STATIC_ASSERT(cond, msg) \ @@ -107,11 +143,47 @@ POSSIBILITY OF SUCH DAMAGE. #define __UNUSED __attribute__((unused)) #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + + #ifndef __HANDLER + #define __HANDLER(handler) __WEAK __attribute__((alias(handler))) + #endif + #define GET_SP() __current_sp() #ifndef __DEPRECATED #define __DEPRECATED(msg) __attribute__((deprecated(msg))) #endif + + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) + #endif + + #ifndef __RESET_HANDLER_ATTRIBUTE + #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN + #endif + + #ifndef __START + #define __START __main + #endif + + #ifndef __VECTOR_TABLE + #define __VECTOR_TABLE __Vectors + #endif + + #ifndef __VECTOR_TABLE_ATTRIBUTE + #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) + #endif + + #ifndef __STACK_ATTRIBUTES + #define __STACK_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".stack"))); + #endif + + #ifndef __HEAP_ATTRIBUTES + #define __HEAP_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".heap"))); + #endif #ifndef NRF_STATIC_ASSERT #ifdef __cplusplus @@ -158,12 +230,48 @@ POSSIBILITY OF SUCH DAMAGE. #ifndef __UNUSED #define __UNUSED #endif + + #ifndef __USED + #define __USED __root + #endif + + #ifndef __HANDLER + #define __HANDLER(handler) __WEAK __attribute__((alias(handler))) + #endif #define GET_SP() __get_SP() #ifndef __DEPRECATED #define __DEPRECATED(msg) __attribute__((deprecated(msg))) #endif + + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) + #endif + + #ifndef __RESET_HANDLER_ATTRIBUTE + #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN + #endif + + #ifndef __START + #define __START __iar_program_start + #endif + + #ifndef __VECTOR_TABLE + #define __VECTOR_TABLE __vector_table + #endif + + #ifndef __VECTOR_TABLE_ATTRIBUTE + #define __VECTOR_TABLE_ATTRIBUTE @".intvec" + #endif + + #ifndef __STACK_ATTRIBUTES + #define __STACK_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".stack"))); + #endif + + #ifndef __HEAP_ATTRIBUTES + #define __HEAP_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".heap"))); + #endif #ifndef NRF_STATIC_ASSERT #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) @@ -178,6 +286,10 @@ POSSIBILITY OF SUCH DAMAGE. #ifndef __INLINE #define __INLINE inline #endif + + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) @@ -195,11 +307,47 @@ POSSIBILITY OF SUCH DAMAGE. #define __UNUSED __attribute__((unused)) #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + + #ifndef __HANDLER + #define __HANDLER(handler) __WEAK __attribute__((alias(handler))) + #endif + #define GET_SP() gcc_current_sp() #ifndef __DEPRECATED #define __DEPRECATED(msg) __attribute__((deprecated(msg))) #endif + + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) + #endif + + #ifndef __RESET_HANDLER_ATTRIBUTE + #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN __attribute__((section(".startup"))) + #endif + + #ifndef __START + #define __START _start + #endif + + #ifndef __VECTOR_TABLE + #define __VECTOR_TABLE __Vectors + #endif + + #ifndef __VECTOR_TABLE_ATTRIBUTE + #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".isr_vector"))) + #endif + + #ifndef __STACK_ATTRIBUTES + #define __STACK_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".stack"))); + #endif + + #ifndef __HEAP_ATTRIBUTES + #define __HEAP_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".heap"))); + #endif static inline unsigned int gcc_current_sp(void) { @@ -244,11 +392,47 @@ POSSIBILITY OF SUCH DAMAGE. #define __UNUSED __attribute__((unused)) #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + + #ifndef __HANDLER + #define __HANDLER(handler) __WEAK __attribute__((alias(handler))) + #endif + #define GET_SP() __get_MSP() #ifndef __DEPRECATED #define __DEPRECATED(msg) #endif + + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) + #endif + + #ifndef __RESET_HANDLER_ATTRIBUTE + #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN __attribute__((section(".startup"))) + #endif + + #ifndef __START + #define __START _start + #endif + + #ifndef __VECTOR_TABLE + #define __VECTOR_TABLE __Vectors + #endif + + #ifndef __VECTOR_TABLE_ATTRIBUTE + #define __VECTOR_TABLE_ATTRIBUTE + #endif + + #ifndef __STACK_ATTRIBUTES + #define __STACK_ATTRIBUTES(align) + #endif + + #ifndef __HEAP_ATTRIBUTES + #define __HEAP_ATTRIBUTES(align) + #endif #ifndef NRF_STATIC_ASSERT #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) diff --git a/mdk/gcc_startup_nrf51.S b/mdk/gcc_startup_nrf51.S index 142e87e36..a20206bd0 100644 --- a/mdk/gcc_startup_nrf51.S +++ b/mdk/gcc_startup_nrf51.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -154,27 +154,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -190,18 +220,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf52.S b/mdk/gcc_startup_nrf52.S index 161fe6e4e..1b64b4f67 100644 --- a/mdk/gcc_startup_nrf52.S +++ b/mdk/gcc_startup_nrf52.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -220,27 +220,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -256,18 +286,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf52805.S b/mdk/gcc_startup_nrf52805.S index 8d7f307d7..f3714733c 100644 --- a/mdk/gcc_startup_nrf52805.S +++ b/mdk/gcc_startup_nrf52805.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -220,27 +220,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -256,18 +286,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf52810.S b/mdk/gcc_startup_nrf52810.S index 10975ffae..006531d43 100644 --- a/mdk/gcc_startup_nrf52810.S +++ b/mdk/gcc_startup_nrf52810.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -243,27 +243,57 @@ skip: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -279,18 +309,36 @@ skip: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf52811.S b/mdk/gcc_startup_nrf52811.S index 9cbd1aebb..cf4fe8eb1 100644 --- a/mdk/gcc_startup_nrf52811.S +++ b/mdk/gcc_startup_nrf52811.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -220,27 +220,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -256,18 +286,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf52820.S b/mdk/gcc_startup_nrf52820.S index bb596b5a8..d30279c61 100644 --- a/mdk/gcc_startup_nrf52820.S +++ b/mdk/gcc_startup_nrf52820.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -220,27 +220,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -256,18 +286,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf52833.S b/mdk/gcc_startup_nrf52833.S index d0b07eea6..89add34cc 100644 --- a/mdk/gcc_startup_nrf52833.S +++ b/mdk/gcc_startup_nrf52833.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -220,27 +220,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -256,18 +286,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf52840.S b/mdk/gcc_startup_nrf52840.S index 44930cce0..8fa5ea8c8 100644 --- a/mdk/gcc_startup_nrf52840.S +++ b/mdk/gcc_startup_nrf52840.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -220,27 +220,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -256,18 +286,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf5340_application.S b/mdk/gcc_startup_nrf5340_application.S index a63b20f69..d2d93f88c 100644 --- a/mdk/gcc_startup_nrf5340_application.S +++ b/mdk/gcc_startup_nrf5340_application.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -348,27 +348,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -384,18 +414,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf5340_network.S b/mdk/gcc_startup_nrf5340_network.S index d499439ad..88552d28b 100644 --- a/mdk/gcc_startup_nrf5340_network.S +++ b/mdk/gcc_startup_nrf5340_network.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -237,27 +237,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -273,18 +303,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/gcc_startup_nrf9120.S b/mdk/gcc_startup_nrf9120.S new file mode 100644 index 000000000..cd2edf204 --- /dev/null +++ b/mdk/gcc_startup_nrf9120.S @@ -0,0 +1,583 @@ +/* + +Copyright (c) 2009-2023 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + + .syntax unified + .arch armv8-m.main + +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + + .section .stack +#if defined(__STARTUP_CONFIG) + .align __STARTUP_CONFIG_STACK_ALIGNEMENT + .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE +#elif defined(__STACK_SIZE) + .align 3 + .equ Stack_Size, __STACK_SIZE +#else + .align 3 + .equ Stack_Size, 15872 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#if defined(__STARTUP_CONFIG) + .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE +#elif defined(__HEAP_SIZE) + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 15872 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector, "ax" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long SecureFault_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SVC_Handler + .long DebugMon_Handler + .long 0 /*Reserved */ + .long PendSV_Handler + .long SysTick_Handler + + /* External Interrupts */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SPU_IRQHandler + .long 0 /*Reserved */ + .long CLOCK_POWER_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + .long SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + .long SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + .long 0 /*Reserved */ + .long GPIOTE0_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long RTC0_IRQHandler + .long RTC1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long WDT_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long EGU0_IRQHandler + .long EGU1_IRQHandler + .long EGU2_IRQHandler + .long EGU3_IRQHandler + .long EGU4_IRQHandler + .long EGU5_IRQHandler + .long PWM0_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long PWM3_IRQHandler + .long 0 /*Reserved */ + .long PDM_IRQHandler + .long 0 /*Reserved */ + .long I2S_IRQHandler + .long 0 /*Reserved */ + .long IPC_IRQHandler + .long 0 /*Reserved */ + .long FPU_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long GPIOTE1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long KMU_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long CRYPTOCELL_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifndef __STARTUP_SKIP_ETEXT + +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: + + +#endif + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + bl clear_region + + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: + movs r0, 0 + + subs r2, r2, r1 + ble .L_clear_region_done + +.L_clear_region: + subs r2, r2, #4 + str r0, [r1, r2] + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: + +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + bl SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler,.-Reset_Handler + + .section ".text" + + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + b . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SecureFault_Handler + .type SecureFault_Handler, %function +SecureFault_Handler: + b . + .size SecureFault_Handler, . - SecureFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ SPU_IRQHandler + IRQ CLOCK_POWER_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + IRQ SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + IRQ SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + IRQ GPIOTE0_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ RTC1_IRQHandler + IRQ WDT_IRQHandler + IRQ EGU0_IRQHandler + IRQ EGU1_IRQHandler + IRQ EGU2_IRQHandler + IRQ EGU3_IRQHandler + IRQ EGU4_IRQHandler + IRQ EGU5_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM2_IRQHandler + IRQ PWM3_IRQHandler + IRQ PDM_IRQHandler + IRQ I2S_IRQHandler + IRQ IPC_IRQHandler + IRQ FPU_IRQHandler + IRQ GPIOTE1_IRQHandler + IRQ KMU_IRQHandler + IRQ CRYPTOCELL_IRQHandler + + .end diff --git a/mdk/gcc_startup_nrf9160.S b/mdk/gcc_startup_nrf9160.S index 6e8953163..cd2edf204 100644 --- a/mdk/gcc_startup_nrf9160.S +++ b/mdk/gcc_startup_nrf9160.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -348,27 +348,57 @@ Reset_Handler: /* Loop to copy data from read only memory to RAM. * The ranges of copy from/to are specified by following symbols: * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. * * All addresses must be aligned to 4 bytes boundary. */ #ifndef __STARTUP_SKIP_ETEXT - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - subs r3, r3, r2 - ble .L_loop1_done +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: -.L_loop1: - subs r3, r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 -.L_loop1_done: #endif /* This part of work usually is done in C library startup code. Otherwise, @@ -384,18 +414,36 @@ Reset_Handler: #ifdef __STARTUP_CLEAR_BSS ldr r1, =__bss_start__ ldr r2, =__bss_end__ + bl clear_region + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: movs r0, 0 subs r2, r2, r1 - ble .L_loop3_done + ble .L_clear_region_done -.L_loop3: +.L_clear_region: subs r2, r2, #4 str r0, [r1, r2] - bgt .L_loop3 + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: -.L_loop3_done: #endif /* __STARTUP_CLEAR_BSS */ /* Execute SystemInit function. */ diff --git a/mdk/iar_startup_nrf51.s b/mdk/iar_startup_nrf51.s index 0d84a6951..dd04e86b5 100644 --- a/mdk/iar_startup_nrf51.s +++ b/mdk/iar_startup_nrf51.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52.s b/mdk/iar_startup_nrf52.s index 33d66cf4e..8bee2e9bc 100644 --- a/mdk/iar_startup_nrf52.s +++ b/mdk/iar_startup_nrf52.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52805.s b/mdk/iar_startup_nrf52805.s index bdca6303d..5f8f871a1 100644 --- a/mdk/iar_startup_nrf52805.s +++ b/mdk/iar_startup_nrf52805.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52810.s b/mdk/iar_startup_nrf52810.s index 7b0a624af..279f1ffda 100644 --- a/mdk/iar_startup_nrf52810.s +++ b/mdk/iar_startup_nrf52810.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52811.s b/mdk/iar_startup_nrf52811.s index c8f14c8d3..698408155 100644 --- a/mdk/iar_startup_nrf52811.s +++ b/mdk/iar_startup_nrf52811.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52820.s b/mdk/iar_startup_nrf52820.s index 9ef0ed90d..d828908d4 100644 --- a/mdk/iar_startup_nrf52820.s +++ b/mdk/iar_startup_nrf52820.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52833.s b/mdk/iar_startup_nrf52833.s index 8e873fa70..c7198b306 100644 --- a/mdk/iar_startup_nrf52833.s +++ b/mdk/iar_startup_nrf52833.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52840.s b/mdk/iar_startup_nrf52840.s index b91f45d4a..9fccacd5c 100644 --- a/mdk/iar_startup_nrf52840.s +++ b/mdk/iar_startup_nrf52840.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf5340_application.s b/mdk/iar_startup_nrf5340_application.s index dba2a7d93..b0bcf495e 100644 --- a/mdk/iar_startup_nrf5340_application.s +++ b/mdk/iar_startup_nrf5340_application.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf5340_network.s b/mdk/iar_startup_nrf5340_network.s index 581710b50..3410f47d0 100644 --- a/mdk/iar_startup_nrf5340_network.s +++ b/mdk/iar_startup_nrf5340_network.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf9120.s b/mdk/iar_startup_nrf9120.s new file mode 100644 index 000000000..852a2ec52 --- /dev/null +++ b/mdk/iar_startup_nrf9120.s @@ -0,0 +1,559 @@ +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + MODULE ?cstartup + +#if defined(__STARTUP_CONFIG) + + #include "startup_config.h" + + #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT + #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + #endif + + SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT) + DS8 __STARTUP_CONFIG_STACK_SIZE + + SECTION HEAP:DATA:NOROOT(3) + DS8 __STARTUP_CONFIG_HEAP_SIZE + +#else + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + +#endif + + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD SecureFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU_IRQHandler + DCD 0 ; Reserved + DCD CLOCK_POWER_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + DCD 0 ; Reserved + DCD GPIOTE0_IRQHandler + DCD SAADC_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RTC0_IRQHandler + DCD RTC1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WDT_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EGU0_IRQHandler + DCD EGU1_IRQHandler + DCD EGU2_IRQHandler + DCD EGU3_IRQHandler + DCD EGU4_IRQHandler + DCD EGU5_IRQHandler + DCD PWM0_IRQHandler + DCD PWM1_IRQHandler + DCD PWM2_IRQHandler + DCD PWM3_IRQHandler + DCD 0 ; Reserved + DCD PDM_IRQHandler + DCD 0 ; Reserved + DCD I2S_IRQHandler + DCD 0 ; Reserved + DCD IPC_IRQHandler + DCD 0 ; Reserved + DCD FPU_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD GPIOTE1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD KMU_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CRYPTOCELL_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemoryManagement_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemoryManagement_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + ; Dummy interrupt handlers + + PUBWEAK SPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPU_IRQHandler + B . + + PUBWEAK CLOCK_POWER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CLOCK_POWER_IRQHandler + B . + + PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + B . + + PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + B . + + PUBWEAK SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + B . + + PUBWEAK SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + B . + + PUBWEAK GPIOTE0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE0_IRQHandler + B . + + PUBWEAK SAADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAADC_IRQHandler + B . + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B . + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B . + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B . + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B . + + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B . + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_IRQHandler + B . + + PUBWEAK EGU0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU0_IRQHandler + B . + + PUBWEAK EGU1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU1_IRQHandler + B . + + PUBWEAK EGU2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU2_IRQHandler + B . + + PUBWEAK EGU3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU3_IRQHandler + B . + + PUBWEAK EGU4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU4_IRQHandler + B . + + PUBWEAK EGU5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU5_IRQHandler + B . + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_IRQHandler + B . + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_IRQHandler + B . + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_IRQHandler + B . + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_IRQHandler + B . + + PUBWEAK PDM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PDM_IRQHandler + B . + + PUBWEAK I2S_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S_IRQHandler + B . + + PUBWEAK IPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPC_IRQHandler + B . + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B . + + PUBWEAK GPIOTE1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE1_IRQHandler + B . + + PUBWEAK KMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +KMU_IRQHandler + B . + + PUBWEAK CRYPTOCELL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTOCELL_IRQHandler + B . + + END + + diff --git a/mdk/iar_startup_nrf9160.s b/mdk/iar_startup_nrf9160.s index ec4350b0d..852a2ec52 100644 --- a/mdk/iar_startup_nrf9160.s +++ b/mdk/iar_startup_nrf9160.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2022 ARM Limited. All rights reserved. +; Copyright (c) 2009-2023 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/nrf.h b/mdk/nrf.h index bba19a570..a1174ca0e 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -37,8 +37,8 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 51 -#define MDK_MICRO_VERSION 0 +#define MDK_MINOR_VERSION 53 +#define MDK_MICRO_VERSION 1 /* Define coprocessor domains */ @@ -113,7 +113,7 @@ POSSIBILITY OF SUCH DAMAGE. #endif /* Define NRF91_SERIES for common use in nRF91 series devices. */ -#if defined (NRF9160_XXAA) +#if defined (NRF9160_XXAA) || defined (NRF9120_XXAA) #ifndef NRF91_SERIES #define NRF91_SERIES #endif @@ -185,7 +185,18 @@ POSSIBILITY OF SUCH DAMAGE. #elif defined (NRF9160_XXAA) #include "nrf9160.h" #include "nrf9160_bitfields.h" - #include "nrf9160_name_change.h" + #include "nrf91_name_change.h" + + /* Address of locations in RAM that will be used to store a NS-accessible version of FICR */ + #if !defined(NRF_FICR_NS) + #define NRF_FICR_NS_BASE 0x2003E000 + #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE) + #endif + +#elif defined (NRF9120_XXAA) + #include "nrf9120.h" + #include "nrf9120_bitfields.h" + #include "nrf91_name_change.h" /* Address of locations in RAM that will be used to store a NS-accessible version of FICR */ #if !defined(NRF_FICR_NS) diff --git a/mdk/nrf51.h b/mdk/nrf51.h index b2df90f16..6cf49d85d 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:46 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:28 * from File 'nrf51.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:13 */ diff --git a/mdk/nrf51.svd b/mdk/nrf51.svd index c1720c6ac..93a77c984 100644 --- a/mdk/nrf51.svd +++ b/mdk/nrf51.svd @@ -8,7 +8,7 @@ 522 nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 Microcontroller at 16MHz CPU clock -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n diff --git a/mdk/nrf51422_peripherals.h b/mdk/nrf51422_peripherals.h index c391fcbc1..ac8cba5d5 100644 --- a/mdk/nrf51422_peripherals.h +++ b/mdk/nrf51422_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51422_vectors.h b/mdk/nrf51422_vectors.h new file mode 100644 index 000000000..974a5bba1 --- /dev/null +++ b/mdk/nrf51422_vectors.h @@ -0,0 +1,169 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void ADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SVC_Handler, + 0, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UART0_IRQHandler, + SPI0_TWI0_IRQHandler, + SPI1_TWI1_IRQHandler, + 0, + GPIOTE_IRQHandler, + ADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + LPCOMP_IRQHandler, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ + NRF_POWER->RAMON |= 0x00000003ul; + NRF_POWER->RAMON |= 0x00000003ul; +} + +#endif diff --git a/mdk/nrf51422_xxaa.sct b/mdk/nrf51422_xxaa.sct new file mode 100644 index 000000000..d1fe5a6ef --- /dev/null +++ b/mdk/nrf51422_xxaa.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00040000 +{ + FLASH 0x00000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51422_xxaa_memory.h b/mdk/nrf51422_xxaa_memory.h new file mode 100644 index 000000000..b5dcf9c73 --- /dev/null +++ b/mdk/nrf51422_xxaa_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00004000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51422_xxab.sct b/mdk/nrf51422_xxab.sct new file mode 100644 index 000000000..d279e7b95 --- /dev/null +++ b/mdk/nrf51422_xxab.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00020000 +{ + FLASH 0x00000000 0x00020000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51422_xxab_memory.h b/mdk/nrf51422_xxab_memory.h new file mode 100644 index 000000000..961f9e2ad --- /dev/null +++ b/mdk/nrf51422_xxab_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00020000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00004000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51422_xxac.sct b/mdk/nrf51422_xxac.sct new file mode 100644 index 000000000..8d596eb6e --- /dev/null +++ b/mdk/nrf51422_xxac.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00040000 +{ + FLASH 0x00000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51422_xxac_memory.h b/mdk/nrf51422_xxac_memory.h new file mode 100644 index 000000000..e5e828a35 --- /dev/null +++ b/mdk/nrf51422_xxac_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00008000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51801_peripherals.h b/mdk/nrf51801_peripherals.h index 5d06221fa..8f41c2eb2 100644 --- a/mdk/nrf51801_peripherals.h +++ b/mdk/nrf51801_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51801_vectors.h b/mdk/nrf51801_vectors.h new file mode 100644 index 000000000..974a5bba1 --- /dev/null +++ b/mdk/nrf51801_vectors.h @@ -0,0 +1,169 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void ADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SVC_Handler, + 0, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UART0_IRQHandler, + SPI0_TWI0_IRQHandler, + SPI1_TWI1_IRQHandler, + 0, + GPIOTE_IRQHandler, + ADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + LPCOMP_IRQHandler, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ + NRF_POWER->RAMON |= 0x00000003ul; + NRF_POWER->RAMON |= 0x00000003ul; +} + +#endif diff --git a/mdk/nrf51801_xxab.sct b/mdk/nrf51801_xxab.sct new file mode 100644 index 000000000..0982b6ca5 --- /dev/null +++ b/mdk/nrf51801_xxab.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00030000 +{ + FLASH 0x00000000 0x00030000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51801_xxab_memory.h b/mdk/nrf51801_xxab_memory.h new file mode 100644 index 000000000..c6dc8c929 --- /dev/null +++ b/mdk/nrf51801_xxab_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00030000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00004000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51802_peripherals.h b/mdk/nrf51802_peripherals.h index 36d3791f2..5654b182d 100644 --- a/mdk/nrf51802_peripherals.h +++ b/mdk/nrf51802_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51802_vectors.h b/mdk/nrf51802_vectors.h new file mode 100644 index 000000000..974a5bba1 --- /dev/null +++ b/mdk/nrf51802_vectors.h @@ -0,0 +1,169 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void ADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SVC_Handler, + 0, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UART0_IRQHandler, + SPI0_TWI0_IRQHandler, + SPI1_TWI1_IRQHandler, + 0, + GPIOTE_IRQHandler, + ADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + LPCOMP_IRQHandler, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ + NRF_POWER->RAMON |= 0x00000003ul; + NRF_POWER->RAMON |= 0x00000003ul; +} + +#endif diff --git a/mdk/nrf51802_xxaa.sct b/mdk/nrf51802_xxaa.sct new file mode 100644 index 000000000..d1fe5a6ef --- /dev/null +++ b/mdk/nrf51802_xxaa.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00040000 +{ + FLASH 0x00000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51802_xxaa_memory.h b/mdk/nrf51802_xxaa_memory.h new file mode 100644 index 000000000..b5dcf9c73 --- /dev/null +++ b/mdk/nrf51802_xxaa_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00004000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51822_peripherals.h b/mdk/nrf51822_peripherals.h index 1995550c1..b51e6e2c9 100644 --- a/mdk/nrf51822_peripherals.h +++ b/mdk/nrf51822_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51822_vectors.h b/mdk/nrf51822_vectors.h new file mode 100644 index 000000000..974a5bba1 --- /dev/null +++ b/mdk/nrf51822_vectors.h @@ -0,0 +1,169 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void ADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SVC_Handler, + 0, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UART0_IRQHandler, + SPI0_TWI0_IRQHandler, + SPI1_TWI1_IRQHandler, + 0, + GPIOTE_IRQHandler, + ADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + LPCOMP_IRQHandler, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ + NRF_POWER->RAMON |= 0x00000003ul; + NRF_POWER->RAMON |= 0x00000003ul; +} + +#endif diff --git a/mdk/nrf51822_xxaa.sct b/mdk/nrf51822_xxaa.sct new file mode 100644 index 000000000..d1fe5a6ef --- /dev/null +++ b/mdk/nrf51822_xxaa.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00040000 +{ + FLASH 0x00000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51822_xxaa_memory.h b/mdk/nrf51822_xxaa_memory.h new file mode 100644 index 000000000..b5dcf9c73 --- /dev/null +++ b/mdk/nrf51822_xxaa_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00004000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51822_xxab.sct b/mdk/nrf51822_xxab.sct new file mode 100644 index 000000000..d279e7b95 --- /dev/null +++ b/mdk/nrf51822_xxab.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00020000 +{ + FLASH 0x00000000 0x00020000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51822_xxab_memory.h b/mdk/nrf51822_xxab_memory.h new file mode 100644 index 000000000..961f9e2ad --- /dev/null +++ b/mdk/nrf51822_xxab_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00020000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00004000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51822_xxac.sct b/mdk/nrf51822_xxac.sct new file mode 100644 index 000000000..8d596eb6e --- /dev/null +++ b/mdk/nrf51822_xxac.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00040000 +{ + FLASH 0x00000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51822_xxac_memory.h b/mdk/nrf51822_xxac_memory.h new file mode 100644 index 000000000..e5e828a35 --- /dev/null +++ b/mdk/nrf51822_xxac_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00008000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51824_peripherals.h b/mdk/nrf51824_peripherals.h index 3c0136b7d..7603f0eb2 100644 --- a/mdk/nrf51824_peripherals.h +++ b/mdk/nrf51824_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51824_vectors.h b/mdk/nrf51824_vectors.h new file mode 100644 index 000000000..974a5bba1 --- /dev/null +++ b/mdk/nrf51824_vectors.h @@ -0,0 +1,169 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void ADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SVC_Handler, + 0, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UART0_IRQHandler, + SPI0_TWI0_IRQHandler, + SPI1_TWI1_IRQHandler, + 0, + GPIOTE_IRQHandler, + ADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + LPCOMP_IRQHandler, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ + NRF_POWER->RAMON |= 0x00000003ul; + NRF_POWER->RAMON |= 0x00000003ul; +} + +#endif diff --git a/mdk/nrf51824_xxaa.sct b/mdk/nrf51824_xxaa.sct new file mode 100644 index 000000000..d1fe5a6ef --- /dev/null +++ b/mdk/nrf51824_xxaa.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00040000 +{ + FLASH 0x00000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf51824_xxaa_memory.h b/mdk/nrf51824_xxaa_memory.h new file mode 100644 index 000000000..b5dcf9c73 --- /dev/null +++ b/mdk/nrf51824_xxaa_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00000400 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00000400 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00004000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00020000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf51_bitfields.h b/mdk/nrf51_bitfields.h index 2def895d3..cdbc9752c 100644 --- a/mdk/nrf51_bitfields.h +++ b/mdk/nrf51_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51_deprecated.h b/mdk/nrf51_deprecated.h index 8595203a7..fa67b377f 100644 --- a/mdk/nrf51_deprecated.h +++ b/mdk/nrf51_deprecated.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51_erratas.h b/mdk/nrf51_erratas.h index 4ce1e3c82..4b4d443a0 100644 --- a/mdk/nrf51_erratas.h +++ b/mdk/nrf51_erratas.h @@ -3,7 +3,7 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51_peripherals.h b/mdk/nrf51_peripherals.h index 5ed23a176..232ddad1d 100644 --- a/mdk/nrf51_peripherals.h +++ b/mdk/nrf51_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51_to_nrf52.h b/mdk/nrf51_to_nrf52.h index c7967057b..e17b8d725 100644 --- a/mdk/nrf51_to_nrf52.h +++ b/mdk/nrf51_to_nrf52.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51_to_nrf52810.h b/mdk/nrf51_to_nrf52810.h index a356295a5..6240c8465 100644 --- a/mdk/nrf51_to_nrf52810.h +++ b/mdk/nrf51_to_nrf52810.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf51_to_nrf52840.h b/mdk/nrf51_to_nrf52840.h index 87c2f9653..f6033f574 100644 --- a/mdk/nrf51_to_nrf52840.h +++ b/mdk/nrf51_to_nrf52840.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52.h b/mdk/nrf52.h index 2ca8b725b..86c537917 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:56 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:33 * from File 'nrf52.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:13 */ diff --git a/mdk/nrf52.svd b/mdk/nrf52.svd index 66dc81c04..50fdc6874 100644 --- a/mdk/nrf52.svd +++ b/mdk/nrf52.svd @@ -8,7 +8,7 @@ 1 nRF52 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52805.h b/mdk/nrf52805.h index d19291bb9..3f8f1d6b6 100644 --- a/mdk/nrf52805.h +++ b/mdk/nrf52805.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52805.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:52 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:28 * from File 'nrf52805.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ diff --git a/mdk/nrf52805.svd b/mdk/nrf52805.svd index 34133c0eb..778fbaa71 100644 --- a/mdk/nrf52805.svd +++ b/mdk/nrf52805.svd @@ -8,7 +8,7 @@ 1 nRF52805 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n diff --git a/mdk/nrf52805_bitfields.h b/mdk/nrf52805_bitfields.h index 5b08eee79..77daa7c47 100644 --- a/mdk/nrf52805_bitfields.h +++ b/mdk/nrf52805_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52805_peripherals.h b/mdk/nrf52805_peripherals.h index 5d84821f4..c5ea25d4a 100644 --- a/mdk/nrf52805_peripherals.h +++ b/mdk/nrf52805_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52805_vectors.h b/mdk/nrf52805_vectors.h new file mode 100644 index 000000000..a58ddaf62 --- /dev/null +++ b/mdk/nrf52805_vectors.h @@ -0,0 +1,266 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE0_UART0_IRQHandler (void); + __HANDLER("Default_Handler") void TWIM0_TWIS0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_SPI0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + TWIM0_TWIS0_TWI0_IRQHandler, + SPIM0_SPIS0_SPI0_IRQHandler, + 0, + GPIOTE_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + 0, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf52805_xxaa.sct b/mdk/nrf52805_xxaa.sct new file mode 100644 index 000000000..b50eb011c --- /dev/null +++ b/mdk/nrf52805_xxaa.sct @@ -0,0 +1,18 @@ +LOAD 0x00000000 0x00030000 +{ + FLASH 0x00000000 0x00030000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00006000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + CODE_RAM 0x00800000 0x00006000 + { + .ANY (code_ram) ; Code allocated to RAM blocks + } +} \ No newline at end of file diff --git a/mdk/nrf52805_xxaa_memory.h b/mdk/nrf52805_xxaa_memory.h new file mode 100644 index 000000000..d576f043f --- /dev/null +++ b/mdk/nrf52805_xxaa_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00030000 + +/* Device memory CodeRAM: */ +#define NRF_MEMORY_CODERAM_BASE 0x00800000 +#define NRF_MEMORY_CODERAM_SIZE 0x00006000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00006000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00030000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index f437081f3..b15e8b4cb 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:53 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:29 * from File 'nrf52810.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ diff --git a/mdk/nrf52810.svd b/mdk/nrf52810.svd index 64157c531..15393a38f 100644 --- a/mdk/nrf52810.svd +++ b/mdk/nrf52810.svd @@ -8,7 +8,7 @@ 1 nRF52810 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n diff --git a/mdk/nrf52810_bitfields.h b/mdk/nrf52810_bitfields.h index b4be63108..f5434ae93 100644 --- a/mdk/nrf52810_bitfields.h +++ b/mdk/nrf52810_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52810_name_change.h b/mdk/nrf52810_name_change.h index 7afaeb70d..a6eaef1e2 100644 --- a/mdk/nrf52810_name_change.h +++ b/mdk/nrf52810_name_change.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52810_peripherals.h b/mdk/nrf52810_peripherals.h index 32bb64ed9..1d9e63e94 100644 --- a/mdk/nrf52810_peripherals.h +++ b/mdk/nrf52810_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52810_to_nrf52811.h b/mdk/nrf52810_to_nrf52811.h index 03697cf89..6a661fee2 100644 --- a/mdk/nrf52810_to_nrf52811.h +++ b/mdk/nrf52810_to_nrf52811.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52810_vectors.h b/mdk/nrf52810_vectors.h new file mode 100644 index 000000000..873e1f897 --- /dev/null +++ b/mdk/nrf52810_vectors.h @@ -0,0 +1,276 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE0_UART0_IRQHandler (void); + __HANDLER("Default_Handler") void TWIM0_TWIS0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_SPI0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + __HANDLER("Default_Handler") void PWM0_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + TWIM0_TWIS0_TWI0_IRQHandler, + SPIM0_SPIS0_SPI0_IRQHandler, + 0, + GPIOTE_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + COMP_IRQHandler, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + 0, + 0, + PWM0_IRQHandler, + PDM_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ + /* Workaround for Errata 185 RAM: RAM corruption at extreme corners + * found at the Errata document for your device located + * at https://infocenter.nordicsemi.com/index.jsp */ + + if (*(volatile uint32_t *)0x10000130ul == 0xAul && *(volatile uint32_t *)0x10000134ul == 0x0ul){ + *(volatile uint32_t *)0x40000EE4ul = (*(volatile uint32_t *)0x40000EE4ul & ~0x00000070ul) | 0x00000040ul; + } +} + +#endif diff --git a/mdk/nrf52810_xxaa.sct b/mdk/nrf52810_xxaa.sct new file mode 100644 index 000000000..b50eb011c --- /dev/null +++ b/mdk/nrf52810_xxaa.sct @@ -0,0 +1,18 @@ +LOAD 0x00000000 0x00030000 +{ + FLASH 0x00000000 0x00030000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00006000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + CODE_RAM 0x00800000 0x00006000 + { + .ANY (code_ram) ; Code allocated to RAM blocks + } +} \ No newline at end of file diff --git a/mdk/nrf52810_xxaa_memory.h b/mdk/nrf52810_xxaa_memory.h new file mode 100644 index 000000000..d576f043f --- /dev/null +++ b/mdk/nrf52810_xxaa_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00030000 + +/* Device memory CodeRAM: */ +#define NRF_MEMORY_CODERAM_BASE 0x00800000 +#define NRF_MEMORY_CODERAM_SIZE 0x00006000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00006000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00030000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index 5fcfeef2e..56732a95e 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:54 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:31 * from File 'nrf52811.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ diff --git a/mdk/nrf52811.svd b/mdk/nrf52811.svd index 70a3d47b1..0ed08bc06 100644 --- a/mdk/nrf52811.svd +++ b/mdk/nrf52811.svd @@ -8,7 +8,7 @@ 1 nRF52811 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n diff --git a/mdk/nrf52811_bitfields.h b/mdk/nrf52811_bitfields.h index 914673649..b369bb167 100644 --- a/mdk/nrf52811_bitfields.h +++ b/mdk/nrf52811_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52811_peripherals.h b/mdk/nrf52811_peripherals.h index a41cfe73f..b7536c295 100644 --- a/mdk/nrf52811_peripherals.h +++ b/mdk/nrf52811_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52811_vectors.h b/mdk/nrf52811_vectors.h new file mode 100644 index 000000000..ac60cc07c --- /dev/null +++ b/mdk/nrf52811_vectors.h @@ -0,0 +1,269 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE0_UART0_IRQHandler (void); + __HANDLER("Default_Handler") void TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_SPI0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + __HANDLER("Default_Handler") void PWM0_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler, + SPIM0_SPIS0_SPI0_IRQHandler, + 0, + GPIOTE_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + COMP_IRQHandler, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + 0, + 0, + PWM0_IRQHandler, + PDM_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf52811_xxaa.sct b/mdk/nrf52811_xxaa.sct new file mode 100644 index 000000000..b50eb011c --- /dev/null +++ b/mdk/nrf52811_xxaa.sct @@ -0,0 +1,18 @@ +LOAD 0x00000000 0x00030000 +{ + FLASH 0x00000000 0x00030000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00006000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + CODE_RAM 0x00800000 0x00006000 + { + .ANY (code_ram) ; Code allocated to RAM blocks + } +} \ No newline at end of file diff --git a/mdk/nrf52811_xxaa_memory.h b/mdk/nrf52811_xxaa_memory.h new file mode 100644 index 000000000..d576f043f --- /dev/null +++ b/mdk/nrf52811_xxaa_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00030000 + +/* Device memory CodeRAM: */ +#define NRF_MEMORY_CODERAM_BASE 0x00800000 +#define NRF_MEMORY_CODERAM_SIZE 0x00006000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00006000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00030000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf52820.h b/mdk/nrf52820.h index 9bedd926d..06ef0755d 100644 --- a/mdk/nrf52820.h +++ b/mdk/nrf52820.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:55 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:32 * from File 'nrf52820.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ diff --git a/mdk/nrf52820.svd b/mdk/nrf52820.svd index b5aebb1e5..435fbebd5 100644 --- a/mdk/nrf52820.svd +++ b/mdk/nrf52820.svd @@ -8,7 +8,7 @@ 1 nRF52820 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n diff --git a/mdk/nrf52820_bitfields.h b/mdk/nrf52820_bitfields.h index 3080e6e8c..e156e7309 100644 --- a/mdk/nrf52820_bitfields.h +++ b/mdk/nrf52820_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52820_peripherals.h b/mdk/nrf52820_peripherals.h index 31372db4b..a2898a273 100644 --- a/mdk/nrf52820_peripherals.h +++ b/mdk/nrf52820_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52820_vectors.h b/mdk/nrf52820_vectors.h new file mode 100644 index 000000000..24c3927bd --- /dev/null +++ b/mdk/nrf52820_vectors.h @@ -0,0 +1,268 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE0_UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_EGU2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_EGU3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_EGU4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_EGU5_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER3_IRQHandler (void); + __HANDLER("Default_Handler") void USBD_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, + 0, + GPIOTE_IRQHandler, + 0, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + COMP_IRQHandler, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_EGU2_IRQHandler, + SWI3_EGU3_IRQHandler, + SWI4_EGU4_IRQHandler, + SWI5_EGU5_IRQHandler, + TIMER3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + USBD_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf52820_xxaa.sct b/mdk/nrf52820_xxaa.sct new file mode 100644 index 000000000..942164c7d --- /dev/null +++ b/mdk/nrf52820_xxaa.sct @@ -0,0 +1,18 @@ +LOAD 0x00000000 0x00040000 +{ + FLASH 0x00000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + CODE_RAM 0x00800000 0x00008000 + { + .ANY (code_ram) ; Code allocated to RAM blocks + } +} \ No newline at end of file diff --git a/mdk/nrf52820_xxaa_memory.h b/mdk/nrf52820_xxaa_memory.h new file mode 100644 index 000000000..6de546ab8 --- /dev/null +++ b/mdk/nrf52820_xxaa_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory CodeRAM: */ +#define NRF_MEMORY_CODERAM_BASE 0x00800000 +#define NRF_MEMORY_CODERAM_SIZE 0x00008000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00008000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00030000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf52832_peripherals.h b/mdk/nrf52832_peripherals.h index 7796e5e60..727988785 100644 --- a/mdk/nrf52832_peripherals.h +++ b/mdk/nrf52832_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52832_vectors.h b/mdk/nrf52832_vectors.h new file mode 100644 index 000000000..e28b02382 --- /dev/null +++ b/mdk/nrf52832_vectors.h @@ -0,0 +1,279 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE0_UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void NFCT_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_EGU2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_EGU3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_EGU4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_EGU5_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER3_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER4_IRQHandler (void); + __HANDLER("Default_Handler") void PWM0_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void MWU_IRQHandler (void); + __HANDLER("Default_Handler") void PWM1_IRQHandler (void); + __HANDLER("Default_Handler") void PWM2_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM2_SPIS2_SPI2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC2_IRQHandler (void); + __HANDLER("Default_Handler") void I2S_IRQHandler (void); + __HANDLER("Default_Handler") void FPU_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, + NFCT_IRQHandler, + GPIOTE_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + COMP_LPCOMP_IRQHandler, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_EGU2_IRQHandler, + SWI3_EGU3_IRQHandler, + SWI4_EGU4_IRQHandler, + SWI5_EGU5_IRQHandler, + TIMER3_IRQHandler, + TIMER4_IRQHandler, + PWM0_IRQHandler, + PDM_IRQHandler, + 0, + 0, + MWU_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + SPIM2_SPIS2_SPI2_IRQHandler, + RTC2_IRQHandler, + I2S_IRQHandler, + FPU_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf52832_xxaa.sct b/mdk/nrf52832_xxaa.sct new file mode 100644 index 000000000..ae7222980 --- /dev/null +++ b/mdk/nrf52832_xxaa.sct @@ -0,0 +1,18 @@ +LOAD 0x00000000 0x00080000 +{ + FLASH 0x00000000 0x00080000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00010000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + CODE_RAM 0x00800000 0x00010000 + { + .ANY (code_ram) ; Code allocated to RAM blocks + } +} \ No newline at end of file diff --git a/mdk/nrf52832_xxaa_memory.h b/mdk/nrf52832_xxaa_memory.h new file mode 100644 index 000000000..0a7e499cc --- /dev/null +++ b/mdk/nrf52832_xxaa_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 4096 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 4096 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00080000 + +/* Device memory CodeRAM: */ +#define NRF_MEMORY_CODERAM_BASE 0x00800000 +#define NRF_MEMORY_CODERAM_SIZE 0x00010000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00010000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00030000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf52832_xxab.sct b/mdk/nrf52832_xxab.sct new file mode 100644 index 000000000..942164c7d --- /dev/null +++ b/mdk/nrf52832_xxab.sct @@ -0,0 +1,18 @@ +LOAD 0x00000000 0x00040000 +{ + FLASH 0x00000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + CODE_RAM 0x00800000 0x00008000 + { + .ANY (code_ram) ; Code allocated to RAM blocks + } +} \ No newline at end of file diff --git a/mdk/nrf52832_xxab_memory.h b/mdk/nrf52832_xxab_memory.h new file mode 100644 index 000000000..6de546ab8 --- /dev/null +++ b/mdk/nrf52832_xxab_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory CodeRAM: */ +#define NRF_MEMORY_CODERAM_BASE 0x00800000 +#define NRF_MEMORY_CODERAM_SIZE 0x00008000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00008000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00030000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf52833.h b/mdk/nrf52833.h index ea03f8b78..f9c0bcf63 100644 --- a/mdk/nrf52833.h +++ b/mdk/nrf52833.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52833.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:57 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:35 * from File 'nrf52833.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ diff --git a/mdk/nrf52833.svd b/mdk/nrf52833.svd index 79ddf77b8..71e92af16 100644 --- a/mdk/nrf52833.svd +++ b/mdk/nrf52833.svd @@ -8,7 +8,7 @@ 1 nRF52833 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n diff --git a/mdk/nrf52833_bitfields.h b/mdk/nrf52833_bitfields.h index f07c6c3c6..707a35980 100644 --- a/mdk/nrf52833_bitfields.h +++ b/mdk/nrf52833_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52833_peripherals.h b/mdk/nrf52833_peripherals.h index 65baee1af..e7afce421 100644 --- a/mdk/nrf52833_peripherals.h +++ b/mdk/nrf52833_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52833_to_nrf52820.h b/mdk/nrf52833_to_nrf52820.h index 07b302345..f6776a650 100644 --- a/mdk/nrf52833_to_nrf52820.h +++ b/mdk/nrf52833_to_nrf52820.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52833_vectors.h b/mdk/nrf52833_vectors.h new file mode 100644 index 000000000..e736995e0 --- /dev/null +++ b/mdk/nrf52833_vectors.h @@ -0,0 +1,283 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE0_UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void NFCT_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_EGU2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_EGU3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_EGU4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_EGU5_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER3_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER4_IRQHandler (void); + __HANDLER("Default_Handler") void PWM0_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void MWU_IRQHandler (void); + __HANDLER("Default_Handler") void PWM1_IRQHandler (void); + __HANDLER("Default_Handler") void PWM2_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM2_SPIS2_SPI2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC2_IRQHandler (void); + __HANDLER("Default_Handler") void I2S_IRQHandler (void); + __HANDLER("Default_Handler") void FPU_IRQHandler (void); + __HANDLER("Default_Handler") void USBD_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE1_IRQHandler (void); + __HANDLER("Default_Handler") void PWM3_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM3_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, + NFCT_IRQHandler, + GPIOTE_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + COMP_LPCOMP_IRQHandler, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_EGU2_IRQHandler, + SWI3_EGU3_IRQHandler, + SWI4_EGU4_IRQHandler, + SWI5_EGU5_IRQHandler, + TIMER3_IRQHandler, + TIMER4_IRQHandler, + PWM0_IRQHandler, + PDM_IRQHandler, + 0, + 0, + MWU_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + SPIM2_SPIS2_SPI2_IRQHandler, + RTC2_IRQHandler, + I2S_IRQHandler, + FPU_IRQHandler, + USBD_IRQHandler, + UARTE1_IRQHandler, + 0, + 0, + 0, + 0, + PWM3_IRQHandler, + 0, + SPIM3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf52833_xxaa.sct b/mdk/nrf52833_xxaa.sct new file mode 100644 index 000000000..d43b43988 --- /dev/null +++ b/mdk/nrf52833_xxaa.sct @@ -0,0 +1,18 @@ +LOAD 0x00000000 0x00080000 +{ + FLASH 0x00000000 0x00080000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x00020000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + CODE_RAM 0x00800000 0x00020000 + { + .ANY (code_ram) ; Code allocated to RAM blocks + } +} \ No newline at end of file diff --git a/mdk/nrf52833_xxaa_memory.h b/mdk/nrf52833_xxaa_memory.h new file mode 100644 index 000000000..c0c566e21 --- /dev/null +++ b/mdk/nrf52833_xxaa_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 8192 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 8192 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00080000 + +/* Device memory CodeRAM: */ +#define NRF_MEMORY_CODERAM_BASE 0x00800000 +#define NRF_MEMORY_CODERAM_SIZE 0x00020000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00020000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00030000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index 48d1e7c14..ca458c0a1 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:59 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:37 * from File 'nrf52840.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ diff --git a/mdk/nrf52840.svd b/mdk/nrf52840.svd index 97a115337..5efe566b3 100644 --- a/mdk/nrf52840.svd +++ b/mdk/nrf52840.svd @@ -8,7 +8,7 @@ 1 nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n diff --git a/mdk/nrf52840_bitfields.h b/mdk/nrf52840_bitfields.h index 2ddc736b1..fec204b40 100644 --- a/mdk/nrf52840_bitfields.h +++ b/mdk/nrf52840_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52840_peripherals.h b/mdk/nrf52840_peripherals.h index 7f42ddfc9..e56e7bc1a 100644 --- a/mdk/nrf52840_peripherals.h +++ b/mdk/nrf52840_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52840_vectors.h b/mdk/nrf52840_vectors.h new file mode 100644 index 000000000..608b97a38 --- /dev/null +++ b/mdk/nrf52840_vectors.h @@ -0,0 +1,285 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void POWER_CLOCK_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE0_UART0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void); + __HANDLER("Default_Handler") void NFCT_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void CCM_AAR_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_EGU2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_EGU3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_EGU4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_EGU5_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER3_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER4_IRQHandler (void); + __HANDLER("Default_Handler") void PWM0_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void MWU_IRQHandler (void); + __HANDLER("Default_Handler") void PWM1_IRQHandler (void); + __HANDLER("Default_Handler") void PWM2_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM2_SPIS2_SPI2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC2_IRQHandler (void); + __HANDLER("Default_Handler") void I2S_IRQHandler (void); + __HANDLER("Default_Handler") void FPU_IRQHandler (void); + __HANDLER("Default_Handler") void USBD_IRQHandler (void); + __HANDLER("Default_Handler") void UARTE1_IRQHandler (void); + __HANDLER("Default_Handler") void QSPI_IRQHandler (void); + __HANDLER("Default_Handler") void CRYPTOCELL_IRQHandler (void); + __HANDLER("Default_Handler") void PWM3_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM3_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, + NFCT_IRQHandler, + GPIOTE_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + COMP_LPCOMP_IRQHandler, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_EGU2_IRQHandler, + SWI3_EGU3_IRQHandler, + SWI4_EGU4_IRQHandler, + SWI5_EGU5_IRQHandler, + TIMER3_IRQHandler, + TIMER4_IRQHandler, + PWM0_IRQHandler, + PDM_IRQHandler, + 0, + 0, + MWU_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + SPIM2_SPIS2_SPI2_IRQHandler, + RTC2_IRQHandler, + I2S_IRQHandler, + FPU_IRQHandler, + USBD_IRQHandler, + UARTE1_IRQHandler, + QSPI_IRQHandler, + CRYPTOCELL_IRQHandler, + 0, + 0, + PWM3_IRQHandler, + 0, + SPIM3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf52840_xxaa.sct b/mdk/nrf52840_xxaa.sct new file mode 100644 index 000000000..dd6431241 --- /dev/null +++ b/mdk/nrf52840_xxaa.sct @@ -0,0 +1,21 @@ +LOAD 0x00000000 0x00100000 +{ + FLASH 0x00000000 0x00100000 + { + + .ANY (+RO) + .ANY (+XO) + } + EXT_FLASH 0x12000000 0x08000000 + { + .ANY (ext_flash) ; Data or code allocated to external memory + } + RAM 0x20000000 0x00040000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + CODE_RAM 0x00800000 0x00040000 + { + .ANY (code_ram) ; Code allocated to RAM blocks + } +} \ No newline at end of file diff --git a/mdk/nrf52840_xxaa_memory.h b/mdk/nrf52840_xxaa_memory.h new file mode 100644 index 000000000..bd05895cd --- /dev/null +++ b/mdk/nrf52840_xxaa_memory.h @@ -0,0 +1,81 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 16384 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 16384 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00100000 + +/* Device memory ExtFlash: */ +#define NRF_MEMORY_EXTFLASH_BASE 0x12000000 +#define NRF_MEMORY_EXTFLASH_SIZE 0x08000000 + +/* Device memory CodeRAM: */ +#define NRF_MEMORY_CODERAM_BASE 0x00800000 +#define NRF_MEMORY_CODERAM_SIZE 0x00040000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x10000000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x10001000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00040000 + +/* Device memory PeripheralsAPB: */ +#define NRF_MEMORY_PERIPHERALSAPB_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPB_SIZE 0x00030000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00001000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf52_bitfields.h b/mdk/nrf52_bitfields.h index 56d7eede4..33fc6cecd 100644 --- a/mdk/nrf52_bitfields.h +++ b/mdk/nrf52_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52_erratas.h b/mdk/nrf52_erratas.h index e809468db..7347c320f 100644 --- a/mdk/nrf52_erratas.h +++ b/mdk/nrf52_erratas.h @@ -3,7 +3,7 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -232,6 +232,8 @@ static bool nrf52_configuration_257(void) __UNUSED; static bool nrf52_errata_258(void) __UNUSED; static bool nrf52_errata_259(void) __UNUSED; static bool nrf52_errata_262(void) __UNUSED; +static bool nrf52_errata_263(void) __UNUSED; +static bool nrf52_errata_265(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ @@ -13742,11 +13744,11 @@ static bool nrf52_errata_259(void) } /* ========= Errata 262 ========= */ -#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) #define NRF52_ERRATA_262_PRESENT 1 #else #define NRF52_ERRATA_262_PRESENT 0 @@ -13776,9 +13778,9 @@ static bool nrf52_errata_262(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } - #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif @@ -13819,13 +13821,87 @@ static bool nrf52_errata_262(void) } } #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 263 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_ERRATA_263_PRESENT 1 +#else + #define NRF52_ERRATA_263_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_263_ENABLE_WORKAROUND + #define NRF52_ERRATA_263_ENABLE_WORKAROUND NRF52_ERRATA_263_PRESENT +#endif + +static bool nrf52_errata_263(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) if (var1 == 0x0D) { switch(var2) { case 0x00ul: - return false; + return true; case 0x01ul: return true; default: @@ -13847,6 +13923,66 @@ static bool nrf52_errata_262(void) } } #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 265 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + #define NRF52_ERRATA_265_PRESENT 1 +#else + #define NRF52_ERRATA_265_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_265_ENABLE_WORKAROUND + #define NRF52_ERRATA_265_ENABLE_WORKAROUND NRF52_ERRATA_265_PRESENT +#endif + +static bool nrf52_errata_265(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif return false; #endif } diff --git a/mdk/nrf52_name_change.h b/mdk/nrf52_name_change.h index ca158bc3f..a2253df99 100644 --- a/mdk/nrf52_name_change.h +++ b/mdk/nrf52_name_change.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52_to_nrf52810.h b/mdk/nrf52_to_nrf52810.h index a91286aa7..b82955f0a 100644 --- a/mdk/nrf52_to_nrf52810.h +++ b/mdk/nrf52_to_nrf52810.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52_to_nrf52833.h b/mdk/nrf52_to_nrf52833.h index b6e740e18..8efadc60b 100644 --- a/mdk/nrf52_to_nrf52833.h +++ b/mdk/nrf52_to_nrf52833.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf52_to_nrf52840.h b/mdk/nrf52_to_nrf52840.h index 5346f498b..e26e601bf 100644 --- a/mdk/nrf52_to_nrf52840.h +++ b/mdk/nrf52_to_nrf52840.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf5340_application.h b/mdk/nrf5340_application.h index ffb4b5a83..4fc1af1e6 100644 --- a/mdk/nrf5340_application.h +++ b/mdk/nrf5340_application.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf5340_application.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:00 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:39 * from File 'nrf5340_application.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ @@ -226,7 +226,7 @@ typedef struct { * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) */ typedef struct { - __IM uint32_t* ADDR; /*!< (@ 0x00000000) Description cluster: Address of the PAR register + __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address of the PAR register which will be written */ __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ diff --git a/mdk/nrf5340_application.svd b/mdk/nrf5340_application.svd index 7e1192d05..0712fbf90 100644 --- a/mdk/nrf5340_application.svd +++ b/mdk/nrf5340_application.svd @@ -8,7 +8,7 @@ 1 nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -560,7 +560,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x000 read-only 0xFFFFFFFF - uint32_t * + uint32_t Address diff --git a/mdk/nrf5340_application_bitfields.h b/mdk/nrf5340_application_bitfields.h index 5202e3c0d..f201651b5 100644 --- a/mdk/nrf5340_application_bitfields.h +++ b/mdk/nrf5340_application_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf5340_application_name_change.h b/mdk/nrf5340_application_name_change.h index 641bd4619..431407253 100644 --- a/mdk/nrf5340_application_name_change.h +++ b/mdk/nrf5340_application_name_change.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf5340_application_peripherals.h b/mdk/nrf5340_application_peripherals.h index 158d48246..0522aebbc 100644 --- a/mdk/nrf5340_application_peripherals.h +++ b/mdk/nrf5340_application_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf5340_application_vectors.h b/mdk/nrf5340_application_vectors.h new file mode 100644 index 000000000..20199262f --- /dev/null +++ b/mdk/nrf5340_application_vectors.h @@ -0,0 +1,416 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SecureFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void FPU_IRQHandler (void); + __HANDLER("Default_Handler") void CACHE_IRQHandler (void); + __HANDLER("Default_Handler") void SPU_IRQHandler (void); + __HANDLER("Default_Handler") void CLOCK_POWER_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL0_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL1_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM4_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL2_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL3_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE0_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void WDT0_IRQHandler (void); + __HANDLER("Default_Handler") void WDT1_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void EGU2_IRQHandler (void); + __HANDLER("Default_Handler") void EGU3_IRQHandler (void); + __HANDLER("Default_Handler") void EGU4_IRQHandler (void); + __HANDLER("Default_Handler") void EGU5_IRQHandler (void); + __HANDLER("Default_Handler") void PWM0_IRQHandler (void); + __HANDLER("Default_Handler") void PWM1_IRQHandler (void); + __HANDLER("Default_Handler") void PWM2_IRQHandler (void); + __HANDLER("Default_Handler") void PWM3_IRQHandler (void); + __HANDLER("Default_Handler") void PDM0_IRQHandler (void); + __HANDLER("Default_Handler") void I2S0_IRQHandler (void); + __HANDLER("Default_Handler") void IPC_IRQHandler (void); + __HANDLER("Default_Handler") void QSPI_IRQHandler (void); + __HANDLER("Default_Handler") void NFCT_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE1_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC0_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC1_IRQHandler (void); + __HANDLER("Default_Handler") void USBD_IRQHandler (void); + __HANDLER("Default_Handler") void USBREGULATOR_IRQHandler (void); + __HANDLER("Default_Handler") void KMU_IRQHandler (void); + __HANDLER("Default_Handler") void CRYPTOCELL_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + FPU_IRQHandler, + CACHE_IRQHandler, + 0, + SPU_IRQHandler, + 0, + CLOCK_POWER_IRQHandler, + 0, + 0, + SERIAL0_IRQHandler, + SERIAL1_IRQHandler, + SPIM4_IRQHandler, + SERIAL2_IRQHandler, + SERIAL3_IRQHandler, + GPIOTE0_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + 0, + 0, + RTC0_IRQHandler, + RTC1_IRQHandler, + 0, + 0, + WDT0_IRQHandler, + WDT1_IRQHandler, + COMP_LPCOMP_IRQHandler, + EGU0_IRQHandler, + EGU1_IRQHandler, + EGU2_IRQHandler, + EGU3_IRQHandler, + EGU4_IRQHandler, + EGU5_IRQHandler, + PWM0_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + PWM3_IRQHandler, + 0, + PDM0_IRQHandler, + 0, + I2S0_IRQHandler, + 0, + IPC_IRQHandler, + QSPI_IRQHandler, + 0, + NFCT_IRQHandler, + 0, + GPIOTE1_IRQHandler, + 0, + 0, + 0, + QDEC0_IRQHandler, + QDEC1_IRQHandler, + 0, + USBD_IRQHandler, + USBREGULATOR_IRQHandler, + 0, + KMU_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + CRYPTOCELL_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf5340_network.h b/mdk/nrf5340_network.h index 57718fde0..e4bc2dcf9 100644 --- a/mdk/nrf5340_network.h +++ b/mdk/nrf5340_network.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf5340_network.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:09 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:49 * from File 'nrf5340_network.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ @@ -173,7 +173,7 @@ typedef struct { * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) */ typedef struct { - __IM uint32_t* ADDR; /*!< (@ 0x00000000) Description cluster: Address */ + __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ diff --git a/mdk/nrf5340_network.svd b/mdk/nrf5340_network.svd index 06f8e3bd1..6aafef576 100644 --- a/mdk/nrf5340_network.svd +++ b/mdk/nrf5340_network.svd @@ -8,7 +8,7 @@ 1 nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -467,7 +467,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x000 read-only 0xFFFFFFFF - uint32_t * + uint32_t Address diff --git a/mdk/nrf5340_network_bitfields.h b/mdk/nrf5340_network_bitfields.h index b82c3738e..4f8476a7a 100644 --- a/mdk/nrf5340_network_bitfields.h +++ b/mdk/nrf5340_network_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf5340_network_name_change.h b/mdk/nrf5340_network_name_change.h index 31303e43f..4bde57f43 100644 --- a/mdk/nrf5340_network_name_change.h +++ b/mdk/nrf5340_network_name_change.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf5340_network_peripherals.h b/mdk/nrf5340_network_peripherals.h index 18165cb20..329499a51 100644 --- a/mdk/nrf5340_network_peripherals.h +++ b/mdk/nrf5340_network_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf5340_network_vectors.h b/mdk/nrf5340_network_vectors.h new file mode 100644 index 000000000..d4983a4e5 --- /dev/null +++ b/mdk/nrf5340_network_vectors.h @@ -0,0 +1,279 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void CLOCK_POWER_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_IRQHandler (void); + __HANDLER("Default_Handler") void RNG_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void ECB_IRQHandler (void); + __HANDLER("Default_Handler") void AAR_CCM_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void IPC_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL0_IRQHandler (void); + __HANDLER("Default_Handler") void EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + 0, + 0, + 0, + 0, + 0, + CLOCK_POWER_IRQHandler, + 0, + 0, + RADIO_IRQHandler, + RNG_IRQHandler, + GPIOTE_IRQHandler, + WDT_IRQHandler, + TIMER0_IRQHandler, + ECB_IRQHandler, + AAR_CCM_IRQHandler, + 0, + TEMP_IRQHandler, + RTC0_IRQHandler, + IPC_IRQHandler, + SERIAL0_IRQHandler, + EGU0_IRQHandler, + 0, + RTC1_IRQHandler, + 0, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf5340_xxaa_application.sct b/mdk/nrf5340_xxaa_application.sct new file mode 100644 index 000000000..4ceac4112 --- /dev/null +++ b/mdk/nrf5340_xxaa_application.sct @@ -0,0 +1,23 @@ +LOAD 0x00000000 0x00100000 +{ + FLASH 0x00000000 0x00100000 + { + + .ANY (+RO) + .ANY (+XO) + } + EXT_FLASH 0x10000000 0x08000000 + { + .ANY (ext_flash) ; Data or code allocated to external memory + } + RAM0 0x20000000 0x00040000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM1 0x20040000 0x0003F000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf5340_xxaa_application_memory.h b/mdk/nrf5340_xxaa_application_memory.h new file mode 100644 index 000000000..bf3b3002d --- /dev/null +++ b/mdk/nrf5340_xxaa_application_memory.h @@ -0,0 +1,85 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 16384 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 16384 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00100000 + +/* Device memory ExtFlash: */ +#define NRF_MEMORY_EXTFLASH_BASE 0x10000000 +#define NRF_MEMORY_EXTFLASH_SIZE 0x08000000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x00FF0000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x00FF8000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM0: */ +#define NRF_MEMORY_RAM0_BASE 0x20000000 +#define NRF_MEMORY_RAM0_SIZE 0x00040000 + +/* Device memory RAM1: */ +#define NRF_MEMORY_RAM1_BASE 0x20040000 +#define NRF_MEMORY_RAM1_SIZE 0x0003F000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf5340_xxaa_network.sct b/mdk/nrf5340_xxaa_network.sct new file mode 100644 index 000000000..59d987eea --- /dev/null +++ b/mdk/nrf5340_xxaa_network.sct @@ -0,0 +1,28 @@ +LOAD 0x01000000 0x00040000 +{ + FLASH 0x01000000 0x00040000 + { + + .ANY (+RO) + .ANY (+XO) + } + EXT_FLASH 0x10000000 0x08000000 + { + .ANY (ext_flash) ; Data or code allocated to external memory + } + RAM0 0x21000000 0x00010000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM1 0x20000000 0x00040000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM2 0x20040000 0x00040000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf5340_xxaa_network_memory.h b/mdk/nrf5340_xxaa_network_memory.h new file mode 100644 index 000000000..78acd4d2e --- /dev/null +++ b/mdk/nrf5340_xxaa_network_memory.h @@ -0,0 +1,89 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 4096 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 4096 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x01000000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x01FF0000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x01FF8000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x21000000 +#define NRF_MEMORY_RAM_SIZE 0x00010000 + +/* Device memory ExtFlash: */ +#define NRF_MEMORY_EXTFLASH_BASE 0x10000000 +#define NRF_MEMORY_EXTFLASH_SIZE 0x08000000 + +/* Device memory APP_RAM0: */ +#define NRF_MEMORY_APP_RAM0_BASE 0x20000000 +#define NRF_MEMORY_APP_RAM0_SIZE 0x00040000 + +/* Device memory APP_RAM1: */ +#define NRF_MEMORY_APP_RAM1_BASE 0x20040000 +#define NRF_MEMORY_APP_RAM1_SIZE 0x00040000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x41000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x51000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x51840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE1000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf53_erratas.h b/mdk/nrf53_erratas.h index e910757ff..e8803dbc1 100644 --- a/mdk/nrf53_erratas.h +++ b/mdk/nrf53_erratas.h @@ -3,7 +3,7 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -142,6 +142,9 @@ static bool nrf53_errata_140(void) __UNUSED; static bool nrf53_errata_152(void) __UNUSED; static bool nrf53_errata_153(void) __UNUSED; static bool nrf53_errata_154(void) __UNUSED; +static bool nrf53_errata_158(void) __UNUSED; +static bool nrf53_errata_160(void) __UNUSED; +static bool nrf53_errata_161(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -5745,4 +5748,164 @@ static bool nrf53_errata_154(void) #endif } +/* ========= Errata 158 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_158_PRESENT 1 + #else + #define NRF53_ERRATA_158_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_158_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_158_ENABLE_WORKAROUND + #define NRF53_ERRATA_158_ENABLE_WORKAROUND NRF53_ERRATA_158_PRESENT +#endif + +static bool nrf53_errata_158(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 160 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_160_PRESENT 1 + #else + #define NRF53_ERRATA_160_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_160_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_160_ENABLE_WORKAROUND + #define NRF53_ERRATA_160_ENABLE_WORKAROUND NRF53_ERRATA_160_PRESENT +#endif + +static bool nrf53_errata_160(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 161 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_161_PRESENT 1 + #else + #define NRF53_ERRATA_161_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_161_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_161_ENABLE_WORKAROUND + #define NRF53_ERRATA_161_ENABLE_WORKAROUND NRF53_ERRATA_161_PRESENT +#endif + +static bool nrf53_errata_161(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + #endif /* NRF53_ERRATAS_H */ diff --git a/mdk/nrf9120.h b/mdk/nrf9120.h new file mode 100644 index 000000000..6a62070ae --- /dev/null +++ b/mdk/nrf9120.h @@ -0,0 +1,2335 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf9120.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:51 + * from File 'nrf9120.svd', + * last modified on Tuesday, 04.04.2023 09:57:14 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf9120 + * @{ + */ + + +#ifndef NRF9120_H +#define NRF9120_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== nrf9120 Specific Interrupt Numbers =========================================== */ + SPU_IRQn = 3, /*!< 3 SPU */ + CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */ + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */ + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */ + GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ + SAADC_IRQn = 14, /*!< 14 SAADC */ + TIMER0_IRQn = 15, /*!< 15 TIMER0 */ + TIMER1_IRQn = 16, /*!< 16 TIMER1 */ + TIMER2_IRQn = 17, /*!< 17 TIMER2 */ + RTC0_IRQn = 20, /*!< 20 RTC0 */ + RTC1_IRQn = 21, /*!< 21 RTC1 */ + WDT_IRQn = 24, /*!< 24 WDT */ + EGU0_IRQn = 27, /*!< 27 EGU0 */ + EGU1_IRQn = 28, /*!< 28 EGU1 */ + EGU2_IRQn = 29, /*!< 29 EGU2 */ + EGU3_IRQn = 30, /*!< 30 EGU3 */ + EGU4_IRQn = 31, /*!< 31 EGU4 */ + EGU5_IRQn = 32, /*!< 32 EGU5 */ + PWM0_IRQn = 33, /*!< 33 PWM0 */ + PWM1_IRQn = 34, /*!< 34 PWM1 */ + PWM2_IRQn = 35, /*!< 35 PWM2 */ + PWM3_IRQn = 36, /*!< 36 PWM3 */ + PDM_IRQn = 38, /*!< 38 PDM */ + I2S_IRQn = 40, /*!< 40 I2S */ + IPC_IRQn = 42, /*!< 42 IPC */ + FPU_IRQn = 44, /*!< 44 FPU */ + GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */ + KMU_IRQn = 57, /*!< 57 KMU */ + CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ +#define __CM33_REV 0x0004U /*!< CM33 Core Revision */ +#define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __SAUREGION_PRESENT 0 /*!< SAU region present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_nrf9120.h" /*!< nrf9120 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_SIPINFO [SIPINFO] (SIP-specific device info) + */ +typedef struct { + __IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */ + __IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) Description collection: SIP hardware revision, + encoded in ASCII, ex B0A or B1A */ + __IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded + in ASCII, ex SIAA, SIBA or SICA */ +} FICR_SIPINFO_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t RESERVED; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ + __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production + configuration */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ + __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ + __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ +} FICR_INFO_Type; /*!< Size = 44 (0x2c) */ + + +/** + * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) + */ +typedef struct { + __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ + __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ +} FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) + */ +typedef struct { + __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ + __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ + __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ + __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ + __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ + __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ + __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ + __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ +} FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) + */ +typedef struct { + __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where + content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 + ) will be pushed by KMU. Note that this + address must match that of a peripherals + APB mapped write-only key registers, else + the KMU can push this key value into an + address range which the CPU can potentially + read. */ + __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the + key slot. Bits 0-15 and 16-31 can only be + written when equal to 0xFFFF. */ +} UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) + */ +typedef struct { + __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] + of value assigned to KMU key slot. */ +} UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) + */ +typedef struct { + __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ + __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ +} UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ + + +/** + * @brief TAD_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ + __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ + __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ + __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ + __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ +} TAD_PSEL_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated + from the external domain n List capabilities + of the external domain n */ +} SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief SPU_DPPI [DPPI] (Unspecified) + */ +typedef struct { + __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and + non-secure attribute for the DPPI channels. */ + __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification + of the corresponding PERM register */ +} SPU_DPPI_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and + non-secure attribute for pins 0 to 31 of + port n. */ + __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification + of the corresponding PERM register */ +} SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) + */ +typedef struct { + __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region + can contain the non-secure callable (NSC) + region n */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure + callable (NSC) region n */ +} SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPU_RAMNSC [RAMNSC] (Unspecified) + */ +typedef struct { + __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region + can contain the non-secure callable (NSC) + region n */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure + callable (NSC) region n */ +} SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash + region n */ +} SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief SPU_RAMREGION [RAMREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM + region n */ +} SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief SPU_PERIPHID [PERIPHID] (Unspecified) + */ +typedef struct { + __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access + permissions for the peripheral with ID n */ +} SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem) + */ +typedef struct { + __IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */ + __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */ +} POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) + */ +typedef struct { + __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ + __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if + data sent from the debugger to the CPU has + been read. */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ + __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if + the data sent from the CPU to the debugger + has been read. */ +} CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ + + +/** + * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) + */ +typedef struct { + __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE + register from being written until next reset. */ + __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register + and performs an ERASEALL operation. */ +} CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or + above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or + below CH[n].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for + event CH[n].LIMITH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for + event CH[n].LIMITL */ +} SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection + for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection + for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for + CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event + monitoring a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last + START */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ +} DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) + */ +typedef struct { + __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration + for task CHG[n].EN */ + __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration + for task CHG[n].DIS */ +} DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM + of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) + in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM + periods between samples loaded into compare + register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for + PWM channel n */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief I2S_CONFIG [CONFIG] (Unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ +} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + + +/** + * @brief I2S_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ +} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_RXTXD [RXTXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ +} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief APPROTECT_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified) + */ +typedef struct { + __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable SECUREAPPROTECT mechanism */ + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000004) Software force SECUREAPPROTECT mechanism */ +} APPROTECT_SECUREAPPROTECT_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief APPROTECT_APPROTECT [APPROTECT] (Unspecified) + */ +typedef struct { + __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable APPROTECT mechanism */ + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000004) Software force APPROTECT mechanism */ +} APPROTECT_APPROTECT_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief VMC_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear + register */ + __IM uint32_t RESERVED; +} VMC_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR_S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory Information Configuration Registers (FICR_S) + */ + +typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ + __IM uint32_t RESERVED[80]; + __IOM FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000140) SIP-specific device info */ + __IM uint32_t RESERVED1[45]; + __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ + __IM uint32_t RESERVED2[53]; + __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ + __IM uint32_t RESERVED3[64]; + __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ +} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR_S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User information configuration registers User information configuration registers (UICR_S) + */ + +typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */ + __IM uint32_t RESERVED1; + __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ + __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ + __IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE + for Application NVM in POFWARN condition + . */ + __IOM uint32_t PMICCONF; /*!< (@ 0x00000028) Polarity of PMIC polarity configuration signals. */ + __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ + __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: One time programmable + memory */ + __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ +} NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ TAD_S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Trace and debug control (TAD_S) + */ + +typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ + __OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */ + __OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */ + __IM uint32_t RESERVED[318]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ + __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ + __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface + Reset behavior is the same as debug components */ +} NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ + + + +/* =========================================================================================================================== */ +/* ================ SPU_S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System protection unit (SPU_S) + */ + +typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the + RAM memory space */ + __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the + flash memory space */ + __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one + or several peripherals */ + __IM uint32_t RESERVED1[29]; + __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ + __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ + __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ + __IM uint32_t RESERVED2[93]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ + __IM uint32_t RESERVED4[15]; + __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ + __IM uint32_t RESERVED5[15]; + __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ + __IM uint32_t RESERVED6[14]; + __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */ + __IM uint32_t RESERVED7[14]; + __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ + __IM uint32_t RESERVED8[12]; + __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED9[44]; + __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */ + __IM uint32_t RESERVED10[32]; + __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */ + __IM uint32_t RESERVED11[32]; + __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */ +} NRF_SPU_Type; /*!< Size = 2316 (0x90c) */ + + + +/* =========================================================================================================================== */ +/* ================ REGULATORS_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Voltage regulators control 0 (REGULATORS_NS) + */ + +typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ + __IM uint32_t RESERVED[320]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */ + __IM uint32_t RESERVED2[24]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */ +} NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock management 0 (CLOCK_NS) + */ + +typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ + __IM uint32_t RESERVED[28]; + __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ + __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ + __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ + __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED2[30]; + __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ + __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ + __IM uint32_t RESERVED3[94]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED4[62]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested + by triggering HFCLKSTART task and if it + has been started (STATE) */ + __IM uint32_t RESERVED5; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been + requested (SRC) when triggering LFCLKSTART + task and if the source has been started + (STATE) */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART + task has been triggered */ + __IM uint32_t RESERVED6[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts + starts a clock source selected with this + register. */ +} NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control 0 (POWER_NS) + */ + +typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ + __IM uint32_t RESERVED[28]; + __OM uint32_t TASKS_PWMREQSTART; /*!< (@ 0x00000070) Request forcing PWM mode in external DC/DC voltage + regulator. (Drives FPWM_DCDC pin high or + low depending on a setting in UICR). */ + __OM uint32_t TASKS_PWMREQSTOP; /*!< (@ 0x00000074) Stop requesting forcing PWM mode in external + DC/DC voltage regulator */ + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t SUBSCRIBE_PWMREQSTART; /*!< (@ 0x000000F0) Subscribe configuration for task PWMREQSTART */ + __IOM uint32_t SUBSCRIBE_PWMREQSTOP; /*!< (@ 0x000000F4) Subscribe configuration for task PWMREQSTOP */ + __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ + __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IM uint32_t RESERVED4[27]; + __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ + __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ + __IM uint32_t RESERVED6[89]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED8[15]; + __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */ + __IM uint32_t RESERVED9[54]; + __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention + register */ + __IM uint32_t RESERVED10[59]; + __IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */ +} NRF_POWER_Type; /*!< Size = 1560 (0x618) */ + + + +/* =========================================================================================================================== */ +/* ================ CTRL_AP_PERI_S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control access port (CTRL_AP_PERI_S) + */ + +typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */ + __IM uint32_t RESERVED[256]; + __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ + __IM uint32_t RESERVED1[30]; + __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ +} NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) + */ + +typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[27]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED3; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED4[24]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED7; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED8[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED9[13]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED10[2]; + __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ + __IM uint32_t RESERVED11; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ + __IM uint32_t RESERVED12; + __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ + __IM uint32_t RESERVED13[10]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ + __IM uint32_t RESERVED14[12]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED15[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED16[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED17; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED18[4]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED19[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED20[26]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in + case an over-read of the TXD buffer. */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS0_NS) + */ + +typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ + __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ + __IM uint32_t RESERVED2[22]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED5[22]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ + __IM uint32_t RESERVED7[5]; + __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ + __IM uint32_t RESERVED8[21]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED11[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED12[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED13; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED14[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED15; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED16[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) + */ + +typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ + __IM uint32_t RESERVED4; + __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED6; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED7[24]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED8[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED9[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED10[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED11[8]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED12[7]; + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ + __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ + __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ + __IM uint32_t RESERVED14[2]; + __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ + __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED16[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED17[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED18[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED19; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED20[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED21[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED22[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) + */ + +typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED4; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ + __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ + __IM uint32_t RESERVED6[19]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED7[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED8[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED9[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED10[6]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED11[7]; + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ + __IM uint32_t RESERVED12[9]; + __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ + __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ + __IM uint32_t RESERVED13[4]; + __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ + __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ + __IM uint32_t RESERVED14[5]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED15[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED16[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED17[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED18; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED19[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED20[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED21; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED22[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA 0 (UARTE0_NS) + */ + +typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[20]; + __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ + __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ + __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ + __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ + __IM uint32_t RESERVED2[7]; + __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ + __IM uint32_t RESERVED3[20]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED6[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED7; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED8; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED9[9]; + __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ + __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ + __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ + __IM uint32_t RESERVED10; + __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ + __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ + __IM uint32_t RESERVED12[7]; + __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ + __IM uint32_t RESERVED13; + __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ + __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ + __IM uint32_t RESERVED14; + __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ + __IM uint32_t RESERVED15[9]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED16[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED17[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ + __IM uint32_t RESERVED18[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED19; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED20[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED21[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED22; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED23[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE0_S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events 0 (GPIOTE0_S) + */ + +typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ + __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration + for task OUT[n] */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration + for task SET[n] */ + __IM uint32_t RESERVED3[4]; + __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration + for task CLR[n] */ + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from + pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED4[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration + for event IN[n] */ + __IM uint32_t RESERVED5[23]; + __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ + __IM uint32_t RESERVED6[65]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n], and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog to Digital Converter 0 (SAADC_NS) + */ + +typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in + RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels + are sampled */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[28]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the mode, multiple conversions might + be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ + __IM uint32_t RESERVED2[10]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ + __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ + __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ + __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ + __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ + __IM uint32_t RESERVED3[74]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED5[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ + __IM uint32_t RESERVED6[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED7[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should + not be combined with SCAN. The RESOLUTION + is applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED8[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0_NS) + */ + +typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ + __IM uint32_t RESERVED1[10]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ + __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ + __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration + for task SHUTDOWN */ + __IM uint32_t RESERVED2[11]; + __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration + for task CAPTURE[n] */ + __IM uint32_t RESERVED3[26]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED4[26]; + __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration + for event COMPARE[n] */ + __IM uint32_t RESERVED5[10]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED8; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000514) Description collection: Enable one-shot operation + for Capture/Compare channel n */ + __IM uint32_t RESERVED9[5]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register + n */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time counter 0 (RTC0_NS) + */ + +typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ + __IM uint32_t RESERVED[28]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ + __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ + __IM uint32_t RESERVED2[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED3[12]; + __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ + __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ + __IM uint32_t RESERVED4[14]; + __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration + for event COMPARE[n] */ + __IM uint32_t RESERVED5[77]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED7[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). + Must be written when RTC is stopped. */ + __IM uint32_t RESERVED8[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ DPPIC_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS) + */ + +typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ + __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[20]; + __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ + __IM uint32_t RESERVED1[276]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED2[189]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: + Writes to this register are ignored if either + SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS + is enabled */ +} NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer 0 (WDT_NS) + */ + +typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[31]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IM uint32_t RESERVED1[31]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED2[31]; + __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ + __IM uint32_t RESERVED3[96]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED5[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED6[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event generator unit 0 (EGU0_NS) + */ + +typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering + the corresponding TRIGGERED[n] event */ + __IM uint32_t RESERVED[16]; + __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration + for task TRIGGER[n] */ + __IM uint32_t RESERVED1[16]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated + by triggering the corresponding TRIGGER[n] + task */ + __IM uint32_t RESERVED2[16]; + __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration + for event TRIGGERED[n] */ + __IM uint32_t RESERVED3[80]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse width modulation unit 0 (PWM0_NS) + */ + +typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value + on all enabled channels from sequence n, + and starts playing that sequence at the + rate defined in SEQ[n]REFRESH and/or DECODER.MODE. + Causes PWM generation to start if not running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start if + not running. */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration + for task SEQSTART[n] */ + __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started + on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every + sequence n, when last value from RAM has + been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED3[25]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration + for event SEQSTARTED[n] */ + __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration + for event SEQEND[n] */ + __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ + __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ + __IM uint32_t RESERVED4[24]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IM uint32_t RESERVED7[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS) + */ + +typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED2[29]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ + __IM uint32_t RESERVED3[93]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output + sample rate. Change PDMCLKCTRL accordingly. */ + __IM uint32_t RESERVED6[7]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED7[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-IC Sound 0 (I2S_NS) + */ + +typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. + Triggering this task will cause the STOPPED + event to be generated. */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[31]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started + and RX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started + and TX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __IM uint32_t RESERVED3[27]; + __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ + __IM uint32_t RESERVED5[90]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ + __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ + __IM uint32_t RESERVED7[3]; + __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ + __IM uint32_t RESERVED8; + __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED9[3]; + __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ + __IM uint32_t RESERVED10[3]; + __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ IPC_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Interprocessor communication 0 (IPC_NS) + */ + +typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ + __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC + channel enabled in SEND_CNF[n] */ + __IM uint32_t RESERVED[24]; + __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration + for task SEND[n] */ + __IM uint32_t RESERVED1[24]; + __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one + or more of the enabled IPC channels in RECEIVE_CNF[n] */ + __IM uint32_t RESERVED2[24]; + __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration + for event RECEIVE[n] */ + __IM uint32_t RESERVED3[88]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED4[128]; + __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration + for TASKS_SEND[n] */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration + for EVENTS_RECEIVE[n] */ + __IM uint32_t RESERVED6[24]; + __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */ +} NRF_IPC_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ FPU_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FPU 0 (FPU_NS) + */ + +typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_FPU_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ APPROTECT_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection 0 (APPROTECT_NS) + */ + +typedef struct { /*!< (@ 0x40039000) APPROTECT_NS Structure */ + __IM uint32_t RESERVED[896]; + __IOM APPROTECT_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000E00) Unspecified */ + __IM uint32_t RESERVED1[2]; + __IOM APPROTECT_APPROTECT_Type APPROTECT; /*!< (@ 0x00000E10) Unspecified */ +} NRF_APPROTECT_Type; /*!< Size = 3608 (0xe18) */ + + + +/* =========================================================================================================================== */ +/* ================ KMU_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Key management unit 0 (KMU_NS) + */ + +typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ + __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */ + __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked + for selection */ + __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address + defined, or error during push operation */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[63]; + __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ + __IM uint32_t RESERVED3[60]; + __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed + over secure APB when TASKS_PUSH_KEYSLOT + is started */ +} NRF_KMU_Type; /*!< Size = 1284 (0x504) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non-volatile memory controller 0 (NVMC_NS) + */ + +typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1; + __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ + __IM uint32_t RESERVED2[62]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t RESERVED3; + __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ + __IM uint32_t RESERVED6; + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ + __IM uint32_t RESERVED7[13]; + __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ + __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ +} NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ VMC_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Volatile Memory controller 0 (VMC_NS) + */ + +typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */ + __IM uint32_t RESERVED[384]; + __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ +} NRF_VMC_Type; /*!< Size = 1664 (0x680) */ + + + +/* =========================================================================================================================== */ +/* ================ CC_HOST_RGF_S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF_S) + */ + +typedef struct { /*!< (@ 0x50840000) CC_HOST_RGF_S Structure */ + __IM uint32_t RESERVED[1678]; + __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. + When this register is set, K_PRTL cannot + be used and a zeroed key will be used instead. + The value of this register is saved in the + CRYPTOCELL AO power domain. */ + __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. Reading from this address + returns the K_DR valid status indicating + if K_DR is successfully retained. */ + __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The + value of this register is saved in the CRYPTOCELL + AO power domain. */ + __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL + subsystem */ +} NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ + + + +/* =========================================================================================================================== */ +/* ================ CRYPTOCELL_S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S) + */ + +typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */ + __IM uint32_t RESERVED[320]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ +} NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ + + + +/* =========================================================================================================================== */ +/* ================ P0_NS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 0 (P0_NS) + */ + +typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior + and LDETECT mode (For non-secure pin only) */ + __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior + and LDETECT mode (For secure pin only) */ + __IM uint32_t RESERVED1[117]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 640 (0x280) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_S_BASE 0x00FF0000UL +#define NRF_UICR_S_BASE 0x00FF8000UL +#define NRF_TAD_S_BASE 0xE0080000UL +#define NRF_SPU_S_BASE 0x50003000UL +#define NRF_REGULATORS_NS_BASE 0x40004000UL +#define NRF_REGULATORS_S_BASE 0x50004000UL +#define NRF_CLOCK_NS_BASE 0x40005000UL +#define NRF_POWER_NS_BASE 0x40005000UL +#define NRF_CLOCK_S_BASE 0x50005000UL +#define NRF_POWER_S_BASE 0x50005000UL +#define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL +#define NRF_SPIM0_NS_BASE 0x40008000UL +#define NRF_SPIS0_NS_BASE 0x40008000UL +#define NRF_TWIM0_NS_BASE 0x40008000UL +#define NRF_TWIS0_NS_BASE 0x40008000UL +#define NRF_UARTE0_NS_BASE 0x40008000UL +#define NRF_SPIM0_S_BASE 0x50008000UL +#define NRF_SPIS0_S_BASE 0x50008000UL +#define NRF_TWIM0_S_BASE 0x50008000UL +#define NRF_TWIS0_S_BASE 0x50008000UL +#define NRF_UARTE0_S_BASE 0x50008000UL +#define NRF_SPIM1_NS_BASE 0x40009000UL +#define NRF_SPIS1_NS_BASE 0x40009000UL +#define NRF_TWIM1_NS_BASE 0x40009000UL +#define NRF_TWIS1_NS_BASE 0x40009000UL +#define NRF_UARTE1_NS_BASE 0x40009000UL +#define NRF_SPIM1_S_BASE 0x50009000UL +#define NRF_SPIS1_S_BASE 0x50009000UL +#define NRF_TWIM1_S_BASE 0x50009000UL +#define NRF_TWIS1_S_BASE 0x50009000UL +#define NRF_UARTE1_S_BASE 0x50009000UL +#define NRF_SPIM2_NS_BASE 0x4000A000UL +#define NRF_SPIS2_NS_BASE 0x4000A000UL +#define NRF_TWIM2_NS_BASE 0x4000A000UL +#define NRF_TWIS2_NS_BASE 0x4000A000UL +#define NRF_UARTE2_NS_BASE 0x4000A000UL +#define NRF_SPIM2_S_BASE 0x5000A000UL +#define NRF_SPIS2_S_BASE 0x5000A000UL +#define NRF_TWIM2_S_BASE 0x5000A000UL +#define NRF_TWIS2_S_BASE 0x5000A000UL +#define NRF_UARTE2_S_BASE 0x5000A000UL +#define NRF_SPIM3_NS_BASE 0x4000B000UL +#define NRF_SPIS3_NS_BASE 0x4000B000UL +#define NRF_TWIM3_NS_BASE 0x4000B000UL +#define NRF_TWIS3_NS_BASE 0x4000B000UL +#define NRF_UARTE3_NS_BASE 0x4000B000UL +#define NRF_SPIM3_S_BASE 0x5000B000UL +#define NRF_SPIS3_S_BASE 0x5000B000UL +#define NRF_TWIM3_S_BASE 0x5000B000UL +#define NRF_TWIS3_S_BASE 0x5000B000UL +#define NRF_UARTE3_S_BASE 0x5000B000UL +#define NRF_GPIOTE0_S_BASE 0x5000D000UL +#define NRF_SAADC_NS_BASE 0x4000E000UL +#define NRF_SAADC_S_BASE 0x5000E000UL +#define NRF_TIMER0_NS_BASE 0x4000F000UL +#define NRF_TIMER0_S_BASE 0x5000F000UL +#define NRF_TIMER1_NS_BASE 0x40010000UL +#define NRF_TIMER1_S_BASE 0x50010000UL +#define NRF_TIMER2_NS_BASE 0x40011000UL +#define NRF_TIMER2_S_BASE 0x50011000UL +#define NRF_RTC0_NS_BASE 0x40014000UL +#define NRF_RTC0_S_BASE 0x50014000UL +#define NRF_RTC1_NS_BASE 0x40015000UL +#define NRF_RTC1_S_BASE 0x50015000UL +#define NRF_DPPIC_NS_BASE 0x40017000UL +#define NRF_DPPIC_S_BASE 0x50017000UL +#define NRF_WDT_NS_BASE 0x40018000UL +#define NRF_WDT_S_BASE 0x50018000UL +#define NRF_EGU0_NS_BASE 0x4001B000UL +#define NRF_EGU0_S_BASE 0x5001B000UL +#define NRF_EGU1_NS_BASE 0x4001C000UL +#define NRF_EGU1_S_BASE 0x5001C000UL +#define NRF_EGU2_NS_BASE 0x4001D000UL +#define NRF_EGU2_S_BASE 0x5001D000UL +#define NRF_EGU3_NS_BASE 0x4001E000UL +#define NRF_EGU3_S_BASE 0x5001E000UL +#define NRF_EGU4_NS_BASE 0x4001F000UL +#define NRF_EGU4_S_BASE 0x5001F000UL +#define NRF_EGU5_NS_BASE 0x40020000UL +#define NRF_EGU5_S_BASE 0x50020000UL +#define NRF_PWM0_NS_BASE 0x40021000UL +#define NRF_PWM0_S_BASE 0x50021000UL +#define NRF_PWM1_NS_BASE 0x40022000UL +#define NRF_PWM1_S_BASE 0x50022000UL +#define NRF_PWM2_NS_BASE 0x40023000UL +#define NRF_PWM2_S_BASE 0x50023000UL +#define NRF_PWM3_NS_BASE 0x40024000UL +#define NRF_PWM3_S_BASE 0x50024000UL +#define NRF_PDM_NS_BASE 0x40026000UL +#define NRF_PDM_S_BASE 0x50026000UL +#define NRF_I2S_NS_BASE 0x40028000UL +#define NRF_I2S_S_BASE 0x50028000UL +#define NRF_IPC_NS_BASE 0x4002A000UL +#define NRF_IPC_S_BASE 0x5002A000UL +#define NRF_FPU_NS_BASE 0x4002C000UL +#define NRF_FPU_S_BASE 0x5002C000UL +#define NRF_GPIOTE1_NS_BASE 0x40031000UL +#define NRF_APPROTECT_NS_BASE 0x40039000UL +#define NRF_KMU_NS_BASE 0x40039000UL +#define NRF_NVMC_NS_BASE 0x40039000UL +#define NRF_APPROTECT_S_BASE 0x50039000UL +#define NRF_KMU_S_BASE 0x50039000UL +#define NRF_NVMC_S_BASE 0x50039000UL +#define NRF_VMC_NS_BASE 0x4003A000UL +#define NRF_VMC_S_BASE 0x5003A000UL +#define NRF_CC_HOST_RGF_S_BASE 0x50840000UL +#define NRF_CRYPTOCELL_S_BASE 0x50840000UL +#define NRF_P0_NS_BASE 0x40842500UL +#define NRF_P0_S_BASE 0x50842500UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) +#define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) +#define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) +#define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) +#define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) +#define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) +#define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) +#define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) +#define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) +#define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) +#define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE) +#define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) +#define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) +#define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) +#define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) +#define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) +#define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) +#define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) +#define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) +#define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) +#define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) +#define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) +#define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) +#define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) +#define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) +#define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) +#define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) +#define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) +#define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) +#define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) +#define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) +#define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) +#define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) +#define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) +#define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) +#define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) +#define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) +#define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) +#define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) +#define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) +#define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) +#define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) +#define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) +#define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) +#define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) +#define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) +#define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) +#define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) +#define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) +#define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) +#define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) +#define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) +#define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) +#define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) +#define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) +#define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) +#define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) +#define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) +#define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) +#define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) +#define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) +#define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) +#define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) +#define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) +#define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) +#define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) +#define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) +#define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE) +#define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) +#define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) +#define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) +#define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) +#define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) +#define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) +#define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) +#define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) +#define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) +#define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) +#define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) +#define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) +#define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) +#define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) +#define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) +#define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) +#define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) +#define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) +#define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) +#define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) +#define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) +#define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) +#define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE) +#define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE) +#define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) +#define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) +#define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) +#define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE) +#define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) +#define NRF_APPROTECT_NS ((NRF_APPROTECT_Type*) NRF_APPROTECT_NS_BASE) +#define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) +#define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) +#define NRF_APPROTECT_S ((NRF_APPROTECT_Type*) NRF_APPROTECT_S_BASE) +#define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) +#define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) +#define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) +#define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) +#define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE) +#define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) +#define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) +#define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF9120_H */ + + +/** @} */ /* End of group nrf9120 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/mdk/nrf9120.svd b/mdk/nrf9120.svd new file mode 100644 index 000000000..63f7838ae --- /dev/null +++ b/mdk/nrf9120.svd @@ -0,0 +1,35780 @@ + + + + Nordic Semiconductor + Nordic + nrf9120 + nrf91 + 1 + nrf9120 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller + +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + NRF_ + + CM33 + r0p4 + little + 1 + 1 + 3 + 0 + 69 + 0 + + system_nrf91 + + 240 + + + + FICR_S + Factory Information Configuration Registers + 0x00FF0000 + FICR + + + + 0 + 0x1000 + registers + + FICR + 0x20 + + + SIPINFO + SIP-specific device info + FICR_SIPINFO + read-write + 0x140 + + PARTNO + SIP part number + 0x000 + read-only + 0xFFFFFFFF + + + PARTNO + 0 + 31 + + + 9160 + Device is an nRF9160 sip + 0x00009160 + + + + + + + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 + read-only + 0x000000FF + uint8_t + 0x8 + + + HWREVISION + 0 + 7 + + + + + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 + read-only + 0x000000FF + uint8_t + 0x8 + + + VARIANT + 0 + 7 + + + + + + INFO + Device info + FICR_INFO + read-write + 0x200 + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x004 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + PART + Part code + 0x00C + read-only + 0xFFFFFFFF + + + PART + Part code + 0 + 31 + + + N9160 + nRF9160 + 0x9160 + + + N9120 + nRF9120 + 0x9120 + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x010 + read-only + 0x0FFFFFFF + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + AAA0 + AAA0 + 0x41414130 + + + AAB0 + AAB0 + 0x41414230 + + + AAC0 + AAC0 + 0x41414330 + + + + + + + PACKAGE + Package option + 0x014 + read-only + 0x00002000 + + + PACKAGE + Package option + 0 + 31 + + + CF + CFxx - 236 ball wlCSP + 0x2002 + + + + + + + RAM + RAM variant + 0x018 + read-only + 0x00000100 + + + RAM + RAM variant + 0 + 31 + + + K256 + 256 kByte RAM + 0x100 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x01C + read-only + 0x00000400 + + + FLASH + Flash variant + 0 + 31 + + + K1024 + 1 MByte FLASH + 0x400 + + + + + + + CODEPAGESIZE + Code memory page size + 0x020 + read-only + 0x00001000 + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + K4096 + 4 kByte + 0x1000 + + + + + + + CODESIZE + Code memory size + 0x024 + read-only + 0x00000100 + + + CODESIZE + Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE + 0 + 31 + + + P256 + 256 pages + 256 + + + + + + + DEVICETYPE + Device type + 0x028 + read-only + 0xFFFFFFFF + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x0000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + 256 + 0x008 + TRIMCNF[%s] + Unspecified + FICR_TRIMCNF + read-write + 0x300 + + ADDR + Description cluster: Address + 0x000 + read-only + 0xFFFFFFFF + + + Address + Address + 0 + 31 + + + + + DATA + Description cluster: Data + 0x004 + read-only + 0xFFFFFFFF + + + Data + Data + 0 + 31 + + + + + + TRNG90B + NIST800-90B RNG calibration data + FICR_TRNG90B + read-write + 0xC00 + + BYTES + Amount of bytes for the required entropy bits + 0x000 + read-only + 0xFFFFFFFF + + + BYTES + Amount of bytes for the required entropy bits + 0 + 31 + + + + + RCCUTOFF + Repetition counter cutoff + 0x004 + read-only + 0xFFFFFFFF + + + RCCUTOFF + Repetition counter cutoff + 0 + 31 + + + + + APCUTOFF + Adaptive proportion cutoff + 0x008 + read-only + 0xFFFFFFFF + + + APCUTOFF + Adaptive proportion cutoff + 0 + 31 + + + + + STARTUP + Amount of bytes for the startup tests + 0x00C + read-only + 0xFFFFFFFF + + + STARTUP + Amount of bytes for the startup tests + 0 + 31 + + + + + ROSC1 + Sample count for ring oscillator 1 + 0x010 + read-only + 0xFFFFFFFF + + + ROSC1 + Sample count for ring oscillator 1 + 0 + 31 + + + + + ROSC2 + Sample count for ring oscillator 2 + 0x014 + read-only + 0xFFFFFFFF + + + ROSC2 + Sample count for ring oscillator 2 + 0 + 31 + + + + + ROSC3 + Sample count for ring oscillator 3 + 0x018 + read-only + 0xFFFFFFFF + + + ROSC3 + Sample count for ring oscillator 3 + 0 + 31 + + + + + ROSC4 + Sample count for ring oscillator 4 + 0x01C + read-only + 0xFFFFFFFF + + + ROSC4 + Sample count for ring oscillator 4 + 0 + 31 + + + + + + + + UICR_S + User information configuration registers User information configuration registers + 0x00FF8000 + UICR + + + + 0 + 0x1000 + registers + + UICR + 0x20 + + + APPROTECT + Access port protection + 0x000 + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all CPU registers and + memory mapped addresses + 0 + 31 + + + HwUnprotected + HwUnprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + XOSC32M + Oscillator control + 0x014 + read-write + 0xFFFFFFCF + + + CTRL + Pierce current DAC control signals + 0 + 5 + + + + + HFXOSRC + HFXO clock source selection + 0x01C + read-write + 0xFFFFFFFF + + + HFXOSRC + HFXO clock source selection + 0 + 0 + + + XTAL + 32 MHz crystal oscillator + 1 + + + TCXO + 32 MHz temperature compensated crystal oscillator (TCXO) + 0 + + + + + + + HFXOCNT + HFXO startup counter + 0x020 + read-write + 0xFFFFFFFF + + + HFXOCNT + HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us + 0 + 7 + + + MinDebounceTime + Min debounce time = (0*64 us + 0.5 us) + 0 + + + MaxDebounceTime + Max debounce time = (255*64 us + 0.5 us) + 255 + + + + + + + APPNVMCPOFGUARD + Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . + 0x024 + read-write + 0xFFFFFFFF + + + NVMCPOFGUARDEN + Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition + 0 + 0 + + + Disabled + NVM WRITE and NVM ERASE are not blocked in POFWARN condition + 0 + + + Enabled + NVM WRITE and NVM ERASE are blocked in POFWARN condition + 1 + + + + + + + PMICCONF + Polarity of PMIC polarity configuration signals. + 0x028 + read-write + 0xFFFFFFFF + + + PMICFPWMPOL + Polarity of PMIC_FPWM signal. + 0 + 0 + + + ActiveLow + PMIC_FPWM output signal is active-low + 0 + + + ActiveHigh + PMIC_FPWM output signal is active-high + 1 + + + + + + + SECUREAPPROTECT + Secure access port protection + 0x02C + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all secure CPU registers and secure + memory mapped addresses + 0 + 31 + + + HwUnprotected + HwUnprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + ERASEPROTECT + Erase protection + 0x030 + read-write + 0x00000000 + + + PALL + Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality + 0 + 31 + + + Unprotected + Unprotected + 0xFFFFFFFF + + + Protected + Protected + 0x00000000 + + + + + + + 0xBE + 0x4 + OTP[%s] + Description collection: One time programmable memory + 0x108 + read-write + 0xFFFFFFFF + + + LOWER + Lower half word + 0 + 15 + read-writeonce + + + UPPER + Upper half word + 16 + 31 + read-writeonce + + + + + KEYSLOT + Unspecified + UICR_KEYSLOT + read-write + 0x400 + + 128 + 0x008 + CONFIG[%s] + Unspecified + UICR_KEYSLOT_CONFIG + read-write + 0x000 + + DEST + Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) + will be pushed by KMU. Note that this address must match that of a peripherals + APB mapped write-only key registers, else the KMU can push this key value into + an address range which the CPU can potentially read. + 0x000 + read-write + 0xFFFFFFFF + + + DEST + Secure APB destination address + 0 + 31 + + + + + PERM + Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. + 0x004 + read-write + 0xFFFFFFFF + + + WRITE + Write permission for key slot + 0 + 0 + + + Disabled + Disable write to the key value registers + 0 + + + Enabled + Enable write to the key value registers + 1 + + + + + READ + Read permission for key slot + 1 + 1 + + + Disabled + Disable read from key value registers + 0 + + + Enabled + Enable read from key value registers + 1 + + + + + PUSH + Push permission for key slot + 2 + 2 + + + Disabled + Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled + 0 + + + Enabled + Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! + 1 + + + + + STATE + Revocation state for the key slot + 16 + 16 + + + Revoked + Key value registers can no longer be read or pushed + 0 + + + Active + Key value registers are readable (if enabled) and can be pushed (if enabled) + 1 + + + + + + + + 128 + 0x010 + KEY[%s] + Unspecified + UICR_KEYSLOT_KEY + read-write + 0x400 + + 0x4 + 0x4 + VALUE[%s] + Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. + 0x000 + read-write + 0xFFFFFFFF + + + VALUE + Define bits [31+o*32:0+o*32] of value assigned to KMU key slot + 0 + 31 + + + + + + + + + TAD_S + Trace and debug control + 0xE0080000 + TAD + + + + 0 + 0x1000 + registers + + TAD + 0x20 + + + TASKS_CLOCKSTART + Start all trace and debug clocks. + 0x000 + write-only + + + TASKS_CLOCKSTART + Start all trace and debug clocks. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLOCKSTOP + Stop all trace and debug clocks. + 0x004 + write-only + + + TASKS_CLOCKSTOP + Stop all trace and debug clocks. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + ENABLE + Enable debug domain and aquire selected GPIOs + 0x500 + read-write + + + ENABLE + 0 + 0 + + + DISABLED + Disable debug domain and release selected GPIOs + 0 + + + ENABLED + Enable debug domain and aquire selected GPIOs + 1 + + + + + + + PSEL + Unspecified + TAD_PSEL + read-write + 0x504 + + TRACECLK + Pin configuration for TRACECLK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Traceclk + TRACECLK pin + 21 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA0 + Pin configuration for TRACEDATA[0] + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata0 + TRACEDATA0 pin + 22 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA1 + Pin configuration for TRACEDATA[1] + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata1 + TRACEDATA1 pin + 23 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA2 + Pin configuration for TRACEDATA[2] + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata2 + TRACEDATA2 pin + 24 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA3 + Pin configuration for TRACEDATA[3] + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata3 + TRACEDATA3 pin + 25 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + TRACEPORTSPEED + Clocking options for the Trace Port debug interface Reset behavior is the same as debug components + 0x518 + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. + 0 + 1 + + + 32MHz + Trace Port clock is: 32MHz + 0 + + + 16MHz + Trace Port clock is: 16MHz + 1 + + + 8MHz + Trace Port clock is: 8MHz + 2 + + + 4MHz + Trace Port clock is: 4MHz + 3 + + + + + + + + + SPU_S + System protection unit + 0x50003000 + SPU + + + + 0 + 0x1000 + registers + + + SPU + 3 + + SPU + 0x20 + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0x100 + read-write + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0x104 + read-write + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0x108 + read-write + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_RAMACCERR + Publish configuration for event RAMACCERR + 0x180 + read-write + + + CHIDX + DPPI channel that event RAMACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FLASHACCERR + Publish configuration for event FLASHACCERR + 0x184 + read-write + + + CHIDX + DPPI channel that event FLASHACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PERIPHACCERR + Publish configuration for event PERIPHACCERR + 0x188 + read-write + + + CHIDX + DPPI channel that event PERIPHACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RAMACCERR + Enable or disable interrupt for event RAMACCERR + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FLASHACCERR + Enable or disable interrupt for event FLASHACCERR + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PERIPHACCERR + Enable or disable interrupt for event PERIPHACCERR + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RAMACCERR + Write '1' to enable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FLASHACCERR + Write '1' to enable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PERIPHACCERR + Write '1' to enable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RAMACCERR + Write '1' to disable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FLASHACCERR + Write '1' to disable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PERIPHACCERR + Write '1' to disable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CAP + Show implemented features for the current device + 0x400 + read-only + 0x00000001 + + + TZM + Show ARM TrustZone status + 0 + 0 + + + NotAvailable + ARM TrustZone support not available + 0 + + + Enabled + ARM TrustZone support is available + 1 + + + + + + + 1 + 0x004 + EXTDOMAIN[%s] + Unspecified + SPU_EXTDOMAIN + read-write + 0x440 + + PERM + Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n + 0x000 + read-write + 0x00000000 + + + SECUREMAPPING + Define configuration capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + The bus access from this external domain always have the non-secure attribute set + 0 + + + Secure + The bus access from this external domain always have the secure attribute set + 1 + + + UserSelectable + Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register + 2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + NonSecure + Bus accesses from this domain have the non-secure attribute set + 0 + + + Secure + Bus accesses from this domain have secure attribute set + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 1 + 0x008 + DPPI[%s] + Unspecified + SPU_DPPI + read-write + 0x480 + + PERM + Description cluster: Select between secure and non-secure attribute for the DPPI channels. + 0x000 + read-write + 0x0000FFFF + + + CHANNEL0 + Select secure attribute. + 0 + 0 + + + Secure + Channel0 has its secure attribute set + 1 + + + NonSecure + Channel0 has its non-secure attribute set + 0 + + + + + CHANNEL1 + Select secure attribute. + 1 + 1 + + + Secure + Channel1 has its secure attribute set + 1 + + + NonSecure + Channel1 has its non-secure attribute set + 0 + + + + + CHANNEL2 + Select secure attribute. + 2 + 2 + + + Secure + Channel2 has its secure attribute set + 1 + + + NonSecure + Channel2 has its non-secure attribute set + 0 + + + + + CHANNEL3 + Select secure attribute. + 3 + 3 + + + Secure + Channel3 has its secure attribute set + 1 + + + NonSecure + Channel3 has its non-secure attribute set + 0 + + + + + CHANNEL4 + Select secure attribute. + 4 + 4 + + + Secure + Channel4 has its secure attribute set + 1 + + + NonSecure + Channel4 has its non-secure attribute set + 0 + + + + + CHANNEL5 + Select secure attribute. + 5 + 5 + + + Secure + Channel5 has its secure attribute set + 1 + + + NonSecure + Channel5 has its non-secure attribute set + 0 + + + + + CHANNEL6 + Select secure attribute. + 6 + 6 + + + Secure + Channel6 has its secure attribute set + 1 + + + NonSecure + Channel6 has its non-secure attribute set + 0 + + + + + CHANNEL7 + Select secure attribute. + 7 + 7 + + + Secure + Channel7 has its secure attribute set + 1 + + + NonSecure + Channel7 has its non-secure attribute set + 0 + + + + + CHANNEL8 + Select secure attribute. + 8 + 8 + + + Secure + Channel8 has its secure attribute set + 1 + + + NonSecure + Channel8 has its non-secure attribute set + 0 + + + + + CHANNEL9 + Select secure attribute. + 9 + 9 + + + Secure + Channel9 has its secure attribute set + 1 + + + NonSecure + Channel9 has its non-secure attribute set + 0 + + + + + CHANNEL10 + Select secure attribute. + 10 + 10 + + + Secure + Channel10 has its secure attribute set + 1 + + + NonSecure + Channel10 has its non-secure attribute set + 0 + + + + + CHANNEL11 + Select secure attribute. + 11 + 11 + + + Secure + Channel11 has its secure attribute set + 1 + + + NonSecure + Channel11 has its non-secure attribute set + 0 + + + + + CHANNEL12 + Select secure attribute. + 12 + 12 + + + Secure + Channel12 has its secure attribute set + 1 + + + NonSecure + Channel12 has its non-secure attribute set + 0 + + + + + CHANNEL13 + Select secure attribute. + 13 + 13 + + + Secure + Channel13 has its secure attribute set + 1 + + + NonSecure + Channel13 has its non-secure attribute set + 0 + + + + + CHANNEL14 + Select secure attribute. + 14 + 14 + + + Secure + Channel14 has its secure attribute set + 1 + + + NonSecure + Channel14 has its non-secure attribute set + 0 + + + + + CHANNEL15 + Select secure attribute. + 15 + 15 + + + Secure + Channel15 has its secure attribute set + 1 + + + NonSecure + Channel15 has its non-secure attribute set + 0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + DPPI[n].PERM register can't be changed until next reset + 1 + + + Unlocked + DPPI[n].PERM register content can be changed + 0 + + + + + + + + 1 + 0x008 + GPIOPORT[%s] + Unspecified + SPU_GPIOPORT + read-write + 0x4C0 + + PERM + Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. + 0x000 + read-write + 0xFFFFFFFF + + + PIN0 + Select secure attribute attribute for PIN 0. + 0 + 0 + + + Secure + Pin 0 has its secure attribute set + 1 + + + NonSecure + Pin 0 has its non-secure attribute set + 0 + + + + + PIN1 + Select secure attribute attribute for PIN 1. + 1 + 1 + + + Secure + Pin 1 has its secure attribute set + 1 + + + NonSecure + Pin 1 has its non-secure attribute set + 0 + + + + + PIN2 + Select secure attribute attribute for PIN 2. + 2 + 2 + + + Secure + Pin 2 has its secure attribute set + 1 + + + NonSecure + Pin 2 has its non-secure attribute set + 0 + + + + + PIN3 + Select secure attribute attribute for PIN 3. + 3 + 3 + + + Secure + Pin 3 has its secure attribute set + 1 + + + NonSecure + Pin 3 has its non-secure attribute set + 0 + + + + + PIN4 + Select secure attribute attribute for PIN 4. + 4 + 4 + + + Secure + Pin 4 has its secure attribute set + 1 + + + NonSecure + Pin 4 has its non-secure attribute set + 0 + + + + + PIN5 + Select secure attribute attribute for PIN 5. + 5 + 5 + + + Secure + Pin 5 has its secure attribute set + 1 + + + NonSecure + Pin 5 has its non-secure attribute set + 0 + + + + + PIN6 + Select secure attribute attribute for PIN 6. + 6 + 6 + + + Secure + Pin 6 has its secure attribute set + 1 + + + NonSecure + Pin 6 has its non-secure attribute set + 0 + + + + + PIN7 + Select secure attribute attribute for PIN 7. + 7 + 7 + + + Secure + Pin 7 has its secure attribute set + 1 + + + NonSecure + Pin 7 has its non-secure attribute set + 0 + + + + + PIN8 + Select secure attribute attribute for PIN 8. + 8 + 8 + + + Secure + Pin 8 has its secure attribute set + 1 + + + NonSecure + Pin 8 has its non-secure attribute set + 0 + + + + + PIN9 + Select secure attribute attribute for PIN 9. + 9 + 9 + + + Secure + Pin 9 has its secure attribute set + 1 + + + NonSecure + Pin 9 has its non-secure attribute set + 0 + + + + + PIN10 + Select secure attribute attribute for PIN 10. + 10 + 10 + + + Secure + Pin 10 has its secure attribute set + 1 + + + NonSecure + Pin 10 has its non-secure attribute set + 0 + + + + + PIN11 + Select secure attribute attribute for PIN 11. + 11 + 11 + + + Secure + Pin 11 has its secure attribute set + 1 + + + NonSecure + Pin 11 has its non-secure attribute set + 0 + + + + + PIN12 + Select secure attribute attribute for PIN 12. + 12 + 12 + + + Secure + Pin 12 has its secure attribute set + 1 + + + NonSecure + Pin 12 has its non-secure attribute set + 0 + + + + + PIN13 + Select secure attribute attribute for PIN 13. + 13 + 13 + + + Secure + Pin 13 has its secure attribute set + 1 + + + NonSecure + Pin 13 has its non-secure attribute set + 0 + + + + + PIN14 + Select secure attribute attribute for PIN 14. + 14 + 14 + + + Secure + Pin 14 has its secure attribute set + 1 + + + NonSecure + Pin 14 has its non-secure attribute set + 0 + + + + + PIN15 + Select secure attribute attribute for PIN 15. + 15 + 15 + + + Secure + Pin 15 has its secure attribute set + 1 + + + NonSecure + Pin 15 has its non-secure attribute set + 0 + + + + + PIN16 + Select secure attribute attribute for PIN 16. + 16 + 16 + + + Secure + Pin 16 has its secure attribute set + 1 + + + NonSecure + Pin 16 has its non-secure attribute set + 0 + + + + + PIN17 + Select secure attribute attribute for PIN 17. + 17 + 17 + + + Secure + Pin 17 has its secure attribute set + 1 + + + NonSecure + Pin 17 has its non-secure attribute set + 0 + + + + + PIN18 + Select secure attribute attribute for PIN 18. + 18 + 18 + + + Secure + Pin 18 has its secure attribute set + 1 + + + NonSecure + Pin 18 has its non-secure attribute set + 0 + + + + + PIN19 + Select secure attribute attribute for PIN 19. + 19 + 19 + + + Secure + Pin 19 has its secure attribute set + 1 + + + NonSecure + Pin 19 has its non-secure attribute set + 0 + + + + + PIN20 + Select secure attribute attribute for PIN 20. + 20 + 20 + + + Secure + Pin 20 has its secure attribute set + 1 + + + NonSecure + Pin 20 has its non-secure attribute set + 0 + + + + + PIN21 + Select secure attribute attribute for PIN 21. + 21 + 21 + + + Secure + Pin 21 has its secure attribute set + 1 + + + NonSecure + Pin 21 has its non-secure attribute set + 0 + + + + + PIN22 + Select secure attribute attribute for PIN 22. + 22 + 22 + + + Secure + Pin 22 has its secure attribute set + 1 + + + NonSecure + Pin 22 has its non-secure attribute set + 0 + + + + + PIN23 + Select secure attribute attribute for PIN 23. + 23 + 23 + + + Secure + Pin 23 has its secure attribute set + 1 + + + NonSecure + Pin 23 has its non-secure attribute set + 0 + + + + + PIN24 + Select secure attribute attribute for PIN 24. + 24 + 24 + + + Secure + Pin 24 has its secure attribute set + 1 + + + NonSecure + Pin 24 has its non-secure attribute set + 0 + + + + + PIN25 + Select secure attribute attribute for PIN 25. + 25 + 25 + + + Secure + Pin 25 has its secure attribute set + 1 + + + NonSecure + Pin 25 has its non-secure attribute set + 0 + + + + + PIN26 + Select secure attribute attribute for PIN 26. + 26 + 26 + + + Secure + Pin 26 has its secure attribute set + 1 + + + NonSecure + Pin 26 has its non-secure attribute set + 0 + + + + + PIN27 + Select secure attribute attribute for PIN 27. + 27 + 27 + + + Secure + Pin 27 has its secure attribute set + 1 + + + NonSecure + Pin 27 has its non-secure attribute set + 0 + + + + + PIN28 + Select secure attribute attribute for PIN 28. + 28 + 28 + + + Secure + Pin 28 has its secure attribute set + 1 + + + NonSecure + Pin 28 has its non-secure attribute set + 0 + + + + + PIN29 + Select secure attribute attribute for PIN 29. + 29 + 29 + + + Secure + Pin 29 has its secure attribute set + 1 + + + NonSecure + Pin 29 has its non-secure attribute set + 0 + + + + + PIN30 + Select secure attribute attribute for PIN 30. + 30 + 30 + + + Secure + Pin 30 has its secure attribute set + 1 + + + NonSecure + Pin 30 has its non-secure attribute set + 0 + + + + + PIN31 + Select secure attribute attribute for PIN 31. + 31 + 31 + + + Secure + Pin 31 has its secure attribute set + 1 + + + NonSecure + Pin 31 has its non-secure attribute set + 0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + GPIOPORT[n].PERM register can't be changed until next reset + 1 + + + Unlocked + GPIOPORT[n].PERM register content can be changed + 0 + + + + + + + + 2 + 0x008 + FLASHNSC[%s] + Unspecified + SPU_FLASHNSC + read-write + 0x500 + + REGION + Description cluster: Define which flash region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 4 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0 + + + 32 + The region n is defined as non-secure callable with a 32-byte size + 1 + + + 64 + The region n is defined as non-secure callable with a 64-byte size + 2 + + + 128 + The region n is defined as non-secure callable with a 128-byte size + 3 + + + 256 + The region n is defined as non-secure callable with a 256-byte size + 4 + + + 512 + The region n is defined as non-secure callable with a 512-byte size + 5 + + + 1024 + The region n is defined as non-secure callable with a 1024-byte size + 6 + + + 2048 + The region n is defined as non-secure callable with a 2048-byte size + 7 + + + 4096 + The region n is defined as non-secure callable with a 4096-byte size + 8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 2 + 0x008 + RAMNSC[%s] + Unspecified + SPU_RAMNSC + read-write + 0x540 + + REGION + Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 4 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0 + + + 32 + The region n is defined as non-secure callable with a 32-byte size + 1 + + + 64 + The region n is defined as non-secure callable with a 64-byte size + 2 + + + 128 + The region n is defined as non-secure callable with a 128-byte size + 3 + + + 256 + The region n is defined as non-secure callable with a 256-byte size + 4 + + + 512 + The region n is defined as non-secure callable with a 512-byte size + 5 + + + 1024 + The region n is defined as non-secure callable with a 1024-byte size + 6 + + + 2048 + The region n is defined as non-secure callable with a 2048-byte size + 7 + + + 4096 + The region n is defined as non-secure callable with a 4096-byte size + 8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 32 + 0x004 + FLASHREGION[%s] + Unspecified + SPU_FLASHREGION + read-write + 0x600 + + PERM + Description cluster: Access permissions for flash region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from flash region n + 0 + 0 + + + Enable + Allow instruction fetches from flash region n + 1 + + + Disable + Block instruction fetches from flash region n + 0 + + + + + WRITE + Configure write permission for flash region n + 1 + 1 + + + Enable + Allow write operation to region n + 1 + + + Disable + Block write operation to region n + 0 + + + + + READ + Configure read permissions for flash region n + 2 + 2 + + + Enable + Allow read operation from flash region n + 1 + + + Disable + Block read operation from flash region n + 0 + + + + + SECATTR + Security attribute for flash region n + 4 + 4 + + + Non_Secure + Flash region n security attribute is non-secure + 0 + + + Secure + Flash region n security attribute is secure + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 32 + 0x004 + RAMREGION[%s] + Unspecified + SPU_RAMREGION + read-write + 0x700 + + PERM + Description cluster: Access permissions for RAM region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from RAM region n + 0 + 0 + + + Enable + Allow instruction fetches from RAM region n + 1 + + + Disable + Block instruction fetches from RAM region n + 0 + + + + + WRITE + Configure write permission for RAM region n + 1 + 1 + + + Enable + Allow write operation to RAM region n + 1 + + + Disable + Block write operation to RAM region n + 0 + + + + + READ + Configure read permissions for RAM region n + 2 + 2 + + + Enable + Allow read operation from RAM region n + 1 + + + Disable + Block read operation from RAM region n + 0 + + + + + SECATTR + Security attribute for RAM region n + 4 + 4 + + + Non_Secure + RAM region n security attribute is non-secure + 0 + + + Secure + RAM region n security attribute is secure + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 67 + 0x004 + PERIPHID[%s] + Unspecified + SPU_PERIPHID + read-write + 0x800 + + PERM + Description cluster: List capabilities and access permissions for the peripheral with ID n + 0x000 + read-write + 0x00000012 + + + SECUREMAPPING + Define configuration capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + This peripheral is always accessible as a non-secure peripheral + 0 + + + Secure + This peripheral is always accessible as a secure peripheral + 1 + + + UserSelectable + Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register + 2 + + + Split + This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. + 3 + + + + + DMA + Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself + 2 + 3 + read-only + + + NoDMA + Peripheral has no DMA capability + 0 + + + NoSeparateAttribute + Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral + 1 + + + SeparateAttribute + Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral + 2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + Secure + Peripheral is mapped in secure peripheral address space + 1 + + + NonSecure + If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. + 0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + PRESENT + Indicate if a peripheral is present with ID n + 31 + 31 + read-only + + + NotPresent + Peripheral is not present + 0 + + + IsPresent + Peripheral is present + 1 + + + + + + + + + + REGULATORS_NS + Voltage regulators control 0 + 0x40004000 + REGULATORS + + + + 0 + 0x1000 + registers + + REGULATORS + 0x20 + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enable + Enable System OFF mode + 1 + + + + + + + EXTPOFCON + External power failure warning configuration + 0x514 + read-write + + + POF + Enable or disable external power failure warning + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + DCDCEN + Enable DC/DC mode of the main voltage regulator. + 0x578 + read-write + + + DCDCEN + Enable DC/DC converter + 0 + 0 + + + Disabled + DC/DC mode is disabled + 0 + + + Enabled + DC/DC mode is enabled + 1 + + + + + + + + + REGULATORS_S + Voltage regulators control 1 + 0x50004000 + + + + + CLOCK_NS + Clock management 0 + 0x40005000 + CLOCK + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK source + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK source + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_HFCLKSTART + Subscribe configuration for task HFCLKSTART + 0x080 + read-write + + + CHIDX + DPPI channel that task HFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKSTOP + Subscribe configuration for task HFCLKSTOP + 0x084 + read-write + + + CHIDX + DPPI channel that task HFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTART + Subscribe configuration for task LFCLKSTART + 0x088 + read-write + + + CHIDX + DPPI channel that task LFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTOP + Subscribe configuration for task LFCLKSTOP + 0x08C + read-write + + + CHIDX + DPPI channel that task LFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_HFCLKSTARTED + Publish configuration for event HFCLKSTARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event HFCLKSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LFCLKSTARTED + Publish configuration for event LFCLKSTARTED + 0x184 + read-write + + + CHIDX + DPPI channel that event LFCLKSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + HFCLKSTARTED + Enable or disable interrupt for event HFCLKSTARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LFCLKSTARTED + Enable or disable interrupt for event LFCLKSTARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + HFCLKSTARTED + Read pending status of interrupt for event HFCLKSTARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + LFCLKSTARTED + Read pending status of interrupt for event LFCLKSTARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) + 0x40C + read-only + + + SRC + Active clock source + 0 + 0 + + + HFINT + HFINT - 64 MHz on-chip oscillator + 0 + + + HFXO + HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFXO has not been started or HFCLKSTOP task has been triggered + 0 + + + Running + HFXO has been started (HFCLKSTARTED event has been generated) + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) + 0x418 + read-only + + + SRC + Active clock source + 0 + 1 + + + RFU + Reserved for future use + 0 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + Requested LFCLK source has not been started or LFCLKSTOP task has been triggered + 0 + + + Running + Requested LFCLK source has been started (LFCLKSTARTED event has been generated) + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered + 0x41C + read-only + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + RFU + Reserved for future use + 0 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. + 0x518 + read-write + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + RFU + Reserved for future use (equals selecting LFRC) + 0 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + + + + + + + POWER_NS + Power control 0 + 0x40005000 + CLOCK_NS + POWER + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + POWER + 0x20 + + + TASKS_PWMREQSTART + Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). + 0x70 + write-only + + + TASKS_PWMREQSTART + Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PWMREQSTOP + Stop requesting forcing PWM mode in external DC/DC voltage regulator + 0x74 + write-only + + + TASKS_PWMREQSTOP + Stop requesting forcing PWM mode in external DC/DC voltage regulator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CONSTLAT + Enable constant latency mode. + 0x78 + write-only + + + TASKS_CONSTLAT + Enable constant latency mode. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_PWMREQSTART + Subscribe configuration for task PWMREQSTART + 0xF0 + read-write + + + CHIDX + DPPI channel that task PWMREQSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PWMREQSTOP + Subscribe configuration for task PWMREQSTOP + 0xF4 + read-write + + + CHIDX + DPPI channel that task PWMREQSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CONSTLAT + Subscribe configuration for task CONSTLAT + 0xF8 + read-write + + + CHIDX + DPPI channel that task CONSTLAT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LOWPWR + Subscribe configuration for task LOWPWR + 0xFC + read-write + + + CHIDX + DPPI channel that task LOWPWR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_POFWARN + Publish configuration for event POFWARN + 0x188 + read-write + + + CHIDX + DPPI channel that event POFWARN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPENTER + Publish configuration for event SLEEPENTER + 0x194 + read-write + + + CHIDX + DPPI channel that event SLEEPENTER will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPEXIT + Publish configuration for event SLEEPEXIT + 0x198 + read-write + + + CHIDX + DPPI channel that event SLEEPEXIT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + POFWARN + Enable or disable interrupt for event POFWARN + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPENTER + Enable or disable interrupt for event SLEEPENTER + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPEXIT + Enable or disable interrupt for event SLEEPEXIT + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from global watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode + 4 + 4 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from AIRCR.SYSRESETREQ detected + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 17 + 17 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + CTRLAP + Reset triggered through CTRL-AP + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + POWERSTATUS + Modem domain power status + 0x440 + read-only + + + LTEMODEM + LTE modem domain status + 0 + 0 + + + OFF + LTE modem domain is powered off + 0 + + + ON + LTE modem domain is powered on + 1 + + + + + + + 0x2 + 0x4 + GPREGRET[%s] + Description collection: General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + LTEMODEM + LTE Modem + POWER_LTEMODEM + read-write + 0x610 + + STARTN + Start LTE modem + 0x000 + read-write + 0x00000001 + + + STARTN + Start LTE modem + 0 + 0 + + + Start + Start LTE modem + 0 + + + Hold + Hold LTE modem disabled + 1 + + + + + + + FORCEOFF + Force off LTE modem + 0x004 + read-write + 0x00000000 + + + FORCEOFF + Force off LTE modem + 0 + 0 + + + Release + Release force off + 0 + + + Hold + Hold force off active + 1 + + + + + + + + + + CLOCK_S + Clock management 1 + 0x50005000 + + + + CLOCK_POWER + 5 + + + + POWER_S + Power control 1 + 0x50005000 + CLOCK_S + + + + CLOCK_POWER + 5 + + + + CTRL_AP_PERI_S + Control access port + 0x50006000 + CTRLAPPERI + + + + 0 + 0x1000 + registers + + CTRLAPPERI + 0x20 + + + MAILBOX + Unspecified + CTRLAPPERI_MAILBOX + read-write + 0x400 + + RXDATA + Data sent from the debugger to the CPU. + 0x000 + read-only + 0x00000000 + + + RXDATA + Data received from debugger + 0 + 31 + + + + + RXSTATUS + This register shows a status that indicates if data sent from the debugger to the CPU has been read. + 0x004 + read-only + 0x00000000 + + + RXSTATUS + Status of data in register RXDATA + 0 + 0 + + + NoDataPending + No data pending in register RXDATA + 0 + + + DataPending + Data pending in register RXDATA + 1 + + + + + + + TXDATA + Data sent from the CPU to the debugger. + 0x80 + read-write + 0x00000000 + + + TXDATA + Data sent to debugger + 0 + 31 + + + + + TXSTATUS + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. + 0x84 + read-only + 0x00000000 + + + TXSTATUS + Status of data in register TXDATA + 0 + 0 + + + NoDataPending + No data pending in register TXDATA + 0 + + + DataPending + Data pending in register TXDATA + 1 + + + + + + + + ERASEPROTECT + Unspecified + CTRLAPPERI_ERASEPROTECT + read-write + 0x500 + + LOCK + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeonce + 0x00000000 + + + LOCK + Lock ERASEPROTECT.DISABLE register from being written until next reset + 0 + 0 + + + Unlocked + Register ERASEPROTECT.DISABLE is writeable + 0 + + + Locked + Register ERASEPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the ERASEPROTECT register and performs an ERASEALL operation. + 0x004 + read-write + 0x00000000 + + + KEY + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + 0 + 31 + + + + + + + + SPIM0_NS + Serial Peripheral Interface Master with EasyDMA 0 + 0x40008000 + SPIM + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x090 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x198 + read-write + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + ORC + Over-read character. Character clocked out in case an over-read of the TXD buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out in case an over-read of the TXD buffer. + 0 + 7 + + + + + + + SPIS0_NS + SPI Slave 0 + 0x40008000 + SPIM0_NS + SPIS + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x0A4 + read-write + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x0A8 + read-write + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x1A8 + read-write + + + CHIDX + DPPI channel that event ACQUIRED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWIM0_NS + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIM + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1C8 + read-write + + + CHIDX + DPPI channel that event SUSPENDED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1DC + read-write + + + CHIDX + DPPI channel that event LASTRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1E0 + read-write + + + CHIDX + DPPI channel that event LASTTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIS + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0B0 + read-write + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0B4 + read-write + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1E4 + read-write + + + CHIDX + DPPI channel that event WRITE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1E8 + read-write + + + CHIDX + DPPI channel that event READ will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Indication of which address in {ADDRESS} that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + UARTE0_NS + UART with EasyDMA 0 + 0x40008000 + SPIM0_NS + UARTE + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPRX + Subscribe configuration for task STOPRX + 0x084 + read-write + + + CHIDX + DPPI channel that task STOPRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPTX + Subscribe configuration for task STOPTX + 0x08C + read-write + + + CHIDX + DPPI channel that task STOPTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x0AC + read-write + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + + + CHIDX + DPPI channel that event CTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + + + CHIDX + DPPI channel that event NCTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x188 + read-write + + + CHIDX + DPPI channel that event RXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x19C + read-write + + + CHIDX + DPPI channel that event TXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1C4 + read-write + + + CHIDX + DPPI channel that event RXTO will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1D8 + read-write + + + CHIDX + DPPI channel that event TXSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source This register is read/write one to clear. + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + SPIM0_S + Serial Peripheral Interface Master with EasyDMA 1 + 0x50008000 + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + SPIS0_S + SPI Slave 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + TWIM0_S + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + TWIS0_S + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + UARTE0_S + UART with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + SPIM1_NS + Serial Peripheral Interface Master with EasyDMA 2 + 0x40009000 + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIS1_NS + SPI Slave 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIM1_NS + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIS1_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + UARTE1_NS + UART with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIM1_S + Serial Peripheral Interface Master with EasyDMA 3 + 0x50009000 + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIS1_S + SPI Slave 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIM1_S + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIS1_S + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + UARTE1_S + UART with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIM2_NS + Serial Peripheral Interface Master with EasyDMA 4 + 0x4000A000 + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIS2_NS + SPI Slave 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIM2_NS + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIS2_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + UARTE2_NS + UART with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIM2_S + Serial Peripheral Interface Master with EasyDMA 5 + 0x5000A000 + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIS2_S + SPI Slave 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIM2_S + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIS2_S + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + UARTE2_S + UART with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIM3_NS + Serial Peripheral Interface Master with EasyDMA 6 + 0x4000B000 + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIS3_NS + SPI Slave 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIM3_NS + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIS3_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + UARTE3_NS + UART with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIM3_S + Serial Peripheral Interface Master with EasyDMA 7 + 0x5000B000 + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIS3_S + SPI Slave 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIM3_S + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIS3_S + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + UARTE3_S + UART with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + GPIOTE0_S + GPIO Tasks and Events 0 + 0x5000D000 + GPIOTE + + + + 0 + 0x1000 + registers + + + GPIOTE0 + 13 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event IN[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PORT + Publish configuration for event PORT + 0x1FC + read-write + + + CHIDX + DPPI channel that event PORT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC_NS + Analog to Digital Converter 0 + 0x4000E000 + SAADC + + + + 0 + 0x1000 + registers + + + SAADC + 14 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + + + CHIDX + DPPI channel that event RESULTDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0 + + + Busy + ADC is busy. Single conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDDGPIO + VDD_GPIO + 9 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD_GPIO + VDD_GPIO + 9 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD_GPIO + 2 + + + VDD1_2 + Set input at VDD_GPIO/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD_GPIO + 2 + + + VDD1_2 + Set input at VDD_GPIO/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD_GPIO/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0 + + + 10bit + 10 bit + 1 + + + 12bit + 12 bit + 2 + + + 14bit + 14 bit + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + SAADC_S + Analog to Digital Converter 1 + 0x5000E000 + + + + SAADC + 14 + + + + TIMER0_NS + Timer/Counter 0 + 0x4000F000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER0 + 15 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x6 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x6 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x514 + read-write + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0 + + + Enable + Enable one-shot operation + 1 + + + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER0_S + Timer/Counter 1 + 0x5000F000 + + + + TIMER0 + 15 + + + + TIMER1_NS + Timer/Counter 2 + 0x40010000 + + + + TIMER1 + 16 + + + + TIMER1_S + Timer/Counter 3 + 0x50010000 + + + + TIMER1 + 16 + + + + TIMER2_NS + Timer/Counter 4 + 0x40011000 + + + + TIMER2 + 17 + + + + TIMER2_S + Timer/Counter 5 + 0x50011000 + + + + TIMER2 + 17 + + + + RTC0_NS + Real-time counter 0 + 0x40014000 + RTC + + + + 0 + 0x1000 + registers + + + RTC0 + 20 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x4 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + RTC0_S + Real-time counter 1 + 0x50014000 + + + + RTC0 + 20 + + + + RTC1_NS + Real-time counter 2 + 0x40015000 + + + + RTC1 + 21 + + + + RTC1_S + Real-time counter 3 + 0x50015000 + + + + RTC1 + 21 + + + + DPPIC_NS + Distributed programmable peripheral interconnect controller 0 + 0x40017000 + DPPIC + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + 6 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + + + DPPIC_S + Distributed programmable peripheral interconnect controller 1 + 0x50017000 + + + + + WDT_NS + Watchdog Timer 0 + 0x40018000 + WDT + + + + 0 + 0x1000 + registers + + + WDT + 24 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + + + CHIDX + DPPI channel that event TIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUSWDT + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + WDT_S + Watchdog Timer 1 + 0x50018000 + + + + WDT + 24 + + + + EGU0_NS + Event generator unit 0 + 0x4001B000 + EGU + + + + 0 + 0x1000 + registers + + + EGU0 + 27 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + EGU0_S + Event generator unit 1 + 0x5001B000 + + + + EGU0 + 27 + + + + EGU1_NS + Event generator unit 2 + 0x4001C000 + + + + EGU1 + 28 + + + + EGU1_S + Event generator unit 3 + 0x5001C000 + + + + EGU1 + 28 + + + + EGU2_NS + Event generator unit 4 + 0x4001D000 + + + + EGU2 + 29 + + + + EGU2_S + Event generator unit 5 + 0x5001D000 + + + + EGU2 + 29 + + + + EGU3_NS + Event generator unit 6 + 0x4001E000 + + + + EGU3 + 30 + + + + EGU3_S + Event generator unit 7 + 0x5001E000 + + + + EGU3 + 30 + + + + EGU4_NS + Event generator unit 8 + 0x4001F000 + + + + EGU4 + 31 + + + + EGU4_S + Event generator unit 9 + 0x5001F000 + + + + EGU4 + 31 + + + + EGU5_NS + Event generator unit 10 + 0x40020000 + + + + EGU5 + 32 + + + + EGU5_S + Event generator unit 11 + 0x50020000 + + + + EGU5 + 32 + + + + PWM0_NS + Pulse width modulation unit 0 + 0x40021000 + PWM + + + + 0 + 0x1000 + registers + + + PWM0 + 33 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x2 + 0x4 + SUBSCRIBE_SEQSTART[%s] + Description collection: Subscribe configuration for task SEQSTART[n] + 0x088 + read-write + + + CHIDX + DPPI channel that task SEQSTART[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x090 + read-write + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + + + CHIDX + DPPI channel that event SEQEND[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + + + CHIDX + DPPI channel that event LOOPSDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PWM0_S + Pulse width modulation unit 1 + 0x50021000 + + + + PWM0 + 33 + + + + PWM1_NS + Pulse width modulation unit 2 + 0x40022000 + + + + PWM1 + 34 + + + + PWM1_S + Pulse width modulation unit 3 + 0x50022000 + + + + PWM1 + 34 + + + + PWM2_NS + Pulse width modulation unit 4 + 0x40023000 + + + + PWM2 + 35 + + + + PWM2_S + Pulse width modulation unit 5 + 0x50023000 + + + + PWM2 + 35 + + + + PWM3_NS + Pulse width modulation unit 6 + 0x40024000 + + + + PWM3 + 36 + + + + PWM3_S + Pulse width modulation unit 7 + 0x50024000 + + + + PWM3 + 36 + + + + PDM_NS + Pulse Density Modulation (Digital Microphone) Interface 0 + 0x40026000 + PDM + + + + 0 + 0x1000 + registers + + + PDM + 38 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency configuration. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0 + + + Ratio80 + Ratio of 80 + 1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + PDM_S + Pulse Density Modulation (Digital Microphone) Interface 1 + 0x50026000 + + + + PDM + 38 + + + + I2S_NS + Inter-IC Sound 0 + 0x40028000 + I2S + + + + 0 + 0x1000 + registers + + + I2S + 40 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0x004 + write-only + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + + + CHIDX + DPPI channel that event RXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + + + CHIDX + DPPI channel that event TXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0 + + + 16Bit + 16 bit. + 1 + + + 24Bit + 24 bit. + 2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + I2S_S + Inter-IC Sound 1 + 0x50028000 + + + + I2S + 40 + + + + IPC_NS + Interprocessor communication 0 + 0x4002A000 + IPC + + + + 0 + 0x1000 + registers + + + IPC + 42 + + IPC + 0x20 + + + 0x8 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] + 0x000 + write-only + + + TASKS_SEND + Trigger events on IPC channel enabled in SEND_CNF[n] + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0x100 + read-write + + + EVENTS_RECEIVE + Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + 0x8 + 0x4 + SEND_CNF[%s] + Description collection: Send event configuration for TASKS_SEND[n] + 0x510 + read-write + 0x00000000 + + + CHEN0 + Enable broadcasting on IPC channel 0 + 0 + 0 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN1 + Enable broadcasting on IPC channel 1 + 1 + 1 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN2 + Enable broadcasting on IPC channel 2 + 2 + 2 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN3 + Enable broadcasting on IPC channel 3 + 3 + 3 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN4 + Enable broadcasting on IPC channel 4 + 4 + 4 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN5 + Enable broadcasting on IPC channel 5 + 5 + 5 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN6 + Enable broadcasting on IPC channel 6 + 6 + 6 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN7 + Enable broadcasting on IPC channel 7 + 7 + 7 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + + + 0x8 + 0x4 + RECEIVE_CNF[%s] + Description collection: Receive event configuration for EVENTS_RECEIVE[n] + 0x590 + read-write + 0x00000000 + + + CHEN0 + Enable subscription to IPC channel 0 + 0 + 0 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN1 + Enable subscription to IPC channel 1 + 1 + 1 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN2 + Enable subscription to IPC channel 2 + 2 + 2 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN3 + Enable subscription to IPC channel 3 + 3 + 3 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN4 + Enable subscription to IPC channel 4 + 4 + 4 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN5 + Enable subscription to IPC channel 5 + 5 + 5 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN6 + Enable subscription to IPC channel 6 + 6 + 6 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN7 + Enable subscription to IPC channel 7 + 7 + 7 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + + + 0x4 + 0x4 + GPMEM[%s] + Description collection: General purpose memory + 0x610 + read-write + 0x00000000 + + + GPMEM + General purpose memory + 0 + 31 + + + + + + + IPC_S + Interprocessor communication 1 + 0x5002A000 + + + + IPC + 42 + + + + FPU_NS + FPU 0 + 0x4002C000 + FPU + + + + 0 + 0x1000 + registers + + + FPU + 44 + + FPU + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + FPU_S + FPU 1 + 0x5002C000 + + + + FPU + 44 + + + + GPIOTE1_NS + GPIO Tasks and Events 1 + 0x40031000 + + + + GPIOTE1 + 49 + + + + APPROTECT_NS + Access Port Protection 0 + 0x40039000 + APPROTECT + + + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + SECUREAPPROTECT + Unspecified + APPROTECT_SECUREAPPROTECT + read-write + 0xE00 + + DISABLE + Software disable SECUREAPPROTECT mechanism + 0x000 + read-write + 0x00000001 + + + + DISABLE + Software disable SECUREAPPROTECT mechanism + 0 + 7 + + + SwUnprotected + Software disable SECUREAPPROTECT mechanism + 0x5A + + + + + + + FORCEPROTECT + Software force SECUREAPPROTECT mechanism + 0x004 + read-write + 0x00000001 + + + + FORCEPROTECT + Write 0x1 to force enable SECUREAPPROTECT mechanism, which will remain set until the next reset + 9 + 9 + oneToSet + + write + + Force + Software force enable SECUREAPPROTECT mechanism + 0x1 + + + + + + + + APPROTECT + Unspecified + APPROTECT_APPROTECT + read-write + 0xE10 + + DISABLE + Software disable APPROTECT mechanism + 0x000 + read-write + 0x00000001 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwUnprotected + Software disable APPROTECT mechanism + 0x5A + + + + + + + FORCEPROTECT + Software force APPROTECT mechanism + 0x004 + read-write + 0x00000001 + + + FORCEPROTECT + Write 0x1 to force enable APPROTECT mechanism, which will remain set until the next reset + 9 + 9 + oneToSet + + write + + Force + Software force enable APPROTECT mechanism + 0x1 + + + + + + + + + + KMU_NS + Key management unit 0 + 0x40039000 + APPROTECT_NS + KMU + + + + 0 + 0x1000 + registers + + + KMU + 57 + + KMU + 0x20 + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0x0000 + write-only + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0x100 + read-write + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0x104 + read-write + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0x108 + read-write + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + KEYSLOT_PUSHED + Enable or disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + KEYSLOT_REVOKED + Enable or disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + KEYSLOT_ERROR + Enable or disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + KEYSLOT_PUSHED + Write '1' to enable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + KEYSLOT_REVOKED + Write '1' to enable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + KEYSLOT_ERROR + Write '1' to enable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + KEYSLOT_PUSHED + Write '1' to disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + KEYSLOT_REVOKED + Write '1' to disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + KEYSLOT_ERROR + Write '1' to disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + KEYSLOT_PUSHED + Read pending status of interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + KEYSLOT_REVOKED + Read pending status of interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + KEYSLOT_ERROR + Read pending status of interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + STATUS + Status bits for KMU operation + 0x40C + read-only + 0x00000000 + + + SELECTED + Key slot ID successfully selected by the KMU + 0 + 0 + + + Disabled + No key slot ID selected by KMU + 0 + + + Enabled + Key slot ID successfully selected by KMU + 1 + + + + + BLOCKED + Violation status + 1 + 1 + + + Disabled + No access violation detected + 0 + + + Enabled + Access violation detected and blocked + 1 + + + + + + + SELECTKEYSLOT + Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started + 0x500 + read-write + 0x00000000 + + + ID + Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. + 0 + 7 + + + + + + + NVMC_NS + Non-volatile memory controller 0 + 0x40039000 + APPROTECT_NS + NVMC + + + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 2 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + PEen + Partial erase enabled + 4 + + + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + + + + ERASEALL + Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register + 0x540 + read-write + 0x00000000 + + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-code cache hit counter + 0x548 + read-write + + + + HITS + Number of cache hits Write zero to clear + 0 + 31 + + + + + IMISS + I-code cache miss counter + 0x54C + read-write + + + + MISSES + Number of cache misses Write zero to clear + 0 + 31 + + + + + CONFIGNS + Unspecified + 0x584 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + WRITEUICRNS + Non-secure APPROTECT enable register + 0x588 + write-only + + + SET + Allow non-secure code to set APPROTECT + 0 + 0 + + + Set + Set value + 1 + + + + + KEY + Key to write in order to validate the write operation + 4 + 31 + + + Keyvalid + Key value + 0xAFBE5A7 + + + + + + + + + APPROTECT_S + Access Port Protection 1 + 0x50039000 + + + + + KMU_S + Key management unit 1 + 0x50039000 + APPROTECT_S + + + + KMU + 57 + + + + NVMC_S + Non-volatile memory controller 1 + 0x50039000 + APPROTECT_S + + + + + VMC_NS + Volatile Memory controller 0 + 0x4003A000 + VMC + + + + 0 + 0x1000 + registers + + VMC + 0x20 + + + 8 + 0x010 + RAM[%s] + Unspecified + VMC_RAM + read-write + 0x600 + + POWER + Description cluster: RAMn power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + Off + Off + 1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + Off + Off + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + Off + Off + 1 + + + + + + + + + + VMC_S + Volatile Memory controller 1 + 0x5003A000 + + + + + CC_HOST_RGF_S + CRYPTOCELL HOST_RGF interface + 0x50840000 + CC_HOST_RGF + + + + 0 + 0x2000 + registers + + CC_HOST_RGF + 0x20 + + + HOST_CRYPTOKEY_SEL + AES hardware key select + 0x1A38 + read-write + 0x00000000 + + + HOST_CRYPTOKEY_SEL + Select the source of the HW key that is used by the AES engine + 0 + 1 + + + K_DR + Use device root key K_DR from CRYPTOCELL AO power domain + 0 + + + K_PRTL + Use hard-coded RTL key K_PRTL + 1 + + + Session + Use provided session key + 2 + + + + + + + HOST_IOT_KPRTL_LOCK + This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A4C + read-write + 0x00000000 + + + HOST_IOT_KPRTL_LOCK + This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0 + 0 + + + Disabled + K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL + 0 + + + Enabled + K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. + 1 + + + + + + + HOST_IOT_KDR0 + This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. + 0x1A50 + read-write + 0x00000000 + + + HOST_IOT_KDR0 + Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. + 0 + 31 + + + + + HOST_IOT_KDR1 + This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A54 + write-only + 0x00000000 + + + HOST_IOT_KDR1 + K_DR bits 63:32 + 0 + 31 + + + + + HOST_IOT_KDR2 + This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A58 + write-only + 0x00000000 + + + HOST_IOT_KDR2 + K_DR bits 95:64 + 0 + 31 + + + + + HOST_IOT_KDR3 + This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A5C + write-only + 0x00000000 + + + HOST_IOT_KDR3 + K_DR bits 127:96 + 0 + 31 + + + + + HOST_IOT_LCS + Controls lifecycle state (LCS) for CRYPTOCELL subsystem + 0x1A60 + read-write + 0x00000002 + + + LCS + Lifecycle state value. This field is write-once per reset. + 0 + 2 + + + Debug + CC310 operates in debug mode + 0 + + + Secure + CC310 operates in secure mode + 2 + + + + + LCS_IS_VALID + Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. + 8 + 8 + + + Invalid + Valid LCS not yet retained in the CRYPTOCELL AO power domain + 0 + + + Valid + Valid LCS successfully retained in the CRYPTOCELL AO power domain + 1 + + + + + + + + + CRYPTOCELL_S + ARM TrustZone CryptoCell register interface + 0x50840000 + CC_HOST_RGF_S + CRYPTOCELL + + + + 0 + 0x2000 + registers + + + CRYPTOCELL + 64 + + CRYPTOCELL + 0x20 + + + ENABLE + Enable CRYPTOCELL subsystem + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable the CRYPTOCELL subsystem + 0 + 0 + + + Disabled + CRYPTOCELL subsystem disabled + 0 + + + Enabled + CRYPTOCELL subsystem enabled. + 1 + + + + + + + + + P0_NS + GPIO Port 0 + 0x40842500 + GPIO + + + + 0 + 0x300 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x004 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x008 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x00C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x010 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x014 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x018 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x01C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + + + PIN0 + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) + 0x024 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + DETECTMODE_SEC + Select between default DETECT signal behavior and LDETECT mode (For secure pin only) + 0x028 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x200 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0', standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0', disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + P0_S + GPIO Port 1 + 0x50842500 + + + + + \ No newline at end of file diff --git a/mdk/nrf9120_bitfields.h b/mdk/nrf9120_bitfields.h new file mode 100644 index 000000000..2a1b529f4 --- /dev/null +++ b/mdk/nrf9120_bitfields.h @@ -0,0 +1,11195 @@ +/* + +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF9120_BITS_H +#define __NRF9120_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: APPROTECT */ +/* Description: Access Port Protection 0 */ + +/* Register: APPROTECT_SECUREAPPROTECT_DISABLE */ +/* Description: Software disable SECUREAPPROTECT mechanism */ + +/* Bits 7..0 : Software disable SECUREAPPROTECT mechanism */ +#define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_SwUnprotected (0x5AUL) /*!< Software disable SECUREAPPROTECT mechanism */ + +/* Register: APPROTECT_SECUREAPPROTECT_FORCEPROTECT */ +/* Description: Software force SECUREAPPROTECT mechanism */ + +/* Bit 9 : Write 0x1 to force enable SECUREAPPROTECT mechanism, which will remain set until the next reset */ +#define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable SECUREAPPROTECT mechanism */ + +/* Register: APPROTECT_APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_APPROTECT_DISABLE_DISABLE_SwUnprotected (0x5AUL) /*!< Software disable APPROTECT mechanism */ + +/* Register: APPROTECT_APPROTECT_FORCEPROTECT */ +/* Description: Software force APPROTECT mechanism */ + +/* Bit 9 : Write 0x1 to force enable APPROTECT mechanism, which will remain set until the next reset */ +#define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable APPROTECT mechanism */ + + +/* Peripheral: CC_HOST_RGF */ +/* Description: CRYPTOCELL HOST_RGF interface */ + +/* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */ +/* Description: AES hardware key select */ + +/* Bits 1..0 : Select the source of the HW key that is used by the AES engine */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ + +/* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ +/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ +/* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ + +/* Bits 31..0 : Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */ +#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR1 */ +/* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 63:32 */ +#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR2 */ +/* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 95:64 */ +#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR3 */ +/* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 127:96 */ +#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_LCS */ +/* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ + +/* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */ + +/* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */ + + +/* Peripheral: CLOCK */ +/* Description: Clock management 0 */ + +/* Register: CLOCK_TASKS_HFCLKSTART */ +/* Description: Start HFCLK source */ + +/* Bit 0 : Start HFCLK source */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_HFCLKSTOP */ +/* Description: Stop HFCLK source */ + +/* Bit 0 : Stop HFCLK source */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_LFCLKSTART */ +/* Description: Start LFCLK source */ + +/* Bit 0 : Start LFCLK source */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_LFCLKSTOP */ +/* Description: Stop LFCLK source */ + +/* Bit 0 : Stop LFCLK source */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_SUBSCRIBE_HFCLKSTART */ +/* Description: Subscribe configuration for task HFCLKSTART */ + +/* Bit 31 : */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */ +/* Description: Subscribe configuration for task HFCLKSTOP */ + +/* Bit 31 : */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: CLOCK_SUBSCRIBE_LFCLKSTART */ +/* Description: Subscribe configuration for task LFCLKSTART */ + +/* Bit 31 : */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */ +/* Description: Subscribe configuration for task LFCLKSTOP */ + +/* Bit 31 : */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: CLOCK_EVENTS_HFCLKSTARTED */ +/* Description: HFCLK oscillator started */ + +/* Bit 0 : HFCLK oscillator started */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_LFCLKSTARTED */ +/* Description: LFCLK started */ + +/* Bit 0 : LFCLK started */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_PUBLISH_HFCLKSTARTED */ +/* Description: Publish configuration for event HFCLKSTARTED */ + +/* Bit 31 : */ +#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */ +#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: CLOCK_PUBLISH_LFCLKSTARTED */ +/* Description: Publish configuration for event LFCLKSTARTED */ + +/* Bit 31 : */ +#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */ +#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: CLOCK_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */ +#define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */ +#define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_INTPEND */ +/* Description: Pending interrupts */ + +/* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */ +#define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ +#define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ + +/* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */ +#define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ +#define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */ + +/* Bit 0 : Active clock source */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< HFINT - 64 MHz on-chip oscillator */ +#define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */ + +/* Bits 1..0 : Active clock source */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RFU (0UL) /*!< Reserved for future use */ +#define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RFU (0UL) /*!< Reserved for future use */ +#define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RFU (0UL) /*!< Reserved for future use (equals selecting LFRC) */ +#define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ + + +/* Peripheral: CRYPTOCELL */ +/* Description: ARM TrustZone CryptoCell register interface */ + +/* Register: CRYPTOCELL_ENABLE */ +/* Description: Enable CRYPTOCELL subsystem */ + +/* Bit 0 : Enable or disable the CRYPTOCELL subsystem */ +#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */ + + +/* Peripheral: CTRLAPPERI */ +/* Description: Control access port */ + +/* Register: CTRLAPPERI_MAILBOX_RXDATA */ +/* Description: Data sent from the debugger to the CPU. */ + +/* Bits 31..0 : Data received from debugger */ +#define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */ +#define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */ + +/* Register: CTRLAPPERI_MAILBOX_RXSTATUS */ +/* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */ + +/* Bit 0 : Status of data in register RXDATA */ +#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ +#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */ +#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL) /*!< No data pending in register RXDATA */ +#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */ + +/* Register: CTRLAPPERI_MAILBOX_TXDATA */ +/* Description: Data sent from the CPU to the debugger. */ + +/* Bits 31..0 : Data sent to debugger */ +#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */ +#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */ + +/* Register: CTRLAPPERI_MAILBOX_TXSTATUS */ +/* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */ + +/* Bit 0 : Status of data in register TXDATA */ +#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ +#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */ +#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL) /*!< No data pending in register TXDATA */ +#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */ + +/* Register: CTRLAPPERI_ERASEPROTECT_LOCK */ +/* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */ + +/* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */ +#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ +#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */ +#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */ + +/* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */ +/* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */ + +/* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ +#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ +#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ + + +/* Peripheral: DPPIC */ +/* Description: Distributed programmable peripheral interconnect controller 0 */ + +/* Register: DPPIC_TASKS_CHG_EN */ +/* Description: Description cluster: Enable channel group n */ + +/* Bit 0 : Enable channel group n */ +#define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ +#define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ + +/* Register: DPPIC_TASKS_CHG_DIS */ +/* Description: Description cluster: Disable channel group n */ + +/* Bit 0 : Disable channel group n */ +#define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ +#define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ +#define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ + +/* Register: DPPIC_SUBSCRIBE_CHG_EN */ +/* Description: Description cluster: Subscribe configuration for task CHG[n].EN */ + +/* Bit 31 : */ +#define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */ +#define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */ +#define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */ +#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: DPPIC_SUBSCRIBE_CHG_DIS */ +/* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */ + +/* Bit 31 : */ +#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */ +#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */ +#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */ +#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */ +#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: DPPIC_CHEN */ +/* Description: Channel enable register */ + +/* Bit 15 : Enable or disable channel 15 */ +#define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: DPPIC_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: DPPIC_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */ + +/* Register: DPPIC_CHG */ +/* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */ + +/* Bit 15 : Include or exclude channel 15 */ +#define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define DPPIC_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define DPPIC_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define DPPIC_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define DPPIC_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define DPPIC_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define DPPIC_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define DPPIC_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define DPPIC_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define DPPIC_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define DPPIC_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define DPPIC_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define DPPIC_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define DPPIC_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define DPPIC_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define DPPIC_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH0_Included (1UL) /*!< Include */ + + +/* Peripheral: EGU */ +/* Description: Event generator unit 0 */ + +/* Register: EGU_TASKS_TRIGGER */ +/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ + +/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ + +/* Register: EGU_SUBSCRIBE_TRIGGER */ +/* Description: Description collection: Subscribe configuration for task TRIGGER[n] */ + +/* Bit 31 : */ +#define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ +#define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ +#define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */ +#define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */ +#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: EGU_EVENTS_TRIGGERED */ +/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ + +/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ + +/* Register: EGU_PUBLISH_TRIGGERED */ +/* Description: Description collection: Publish configuration for event TRIGGERED[n] */ + +/* Bit 31 : */ +#define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ +#define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ +#define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */ +#define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */ +#define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration Registers */ + +/* Register: FICR_SIPINFO_PARTNO */ +/* Description: SIP part number */ + +/* Bits 31..0 : */ +#define FICR_SIPINFO_PARTNO_PARTNO_Pos (0UL) /*!< Position of PARTNO field. */ +#define FICR_SIPINFO_PARTNO_PARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PARTNO_PARTNO_Pos) /*!< Bit mask of PARTNO field. */ +#define FICR_SIPINFO_PARTNO_PARTNO_9160 (0x00009160UL) /*!< Device is an nRF9160 sip */ + +/* Register: FICR_SIPINFO_HWREVISION */ +/* Description: Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A */ + +/* Bits 7..0 : */ +#define FICR_SIPINFO_HWREVISION_HWREVISION_Pos (0UL) /*!< Position of HWREVISION field. */ +#define FICR_SIPINFO_HWREVISION_HWREVISION_Msk (0xFFUL << FICR_SIPINFO_HWREVISION_HWREVISION_Pos) /*!< Bit mask of HWREVISION field. */ + +/* Register: FICR_SIPINFO_VARIANT */ +/* Description: Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA */ + +/* Bits 7..0 : */ +#define FICR_SIPINFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_SIPINFO_VARIANT_VARIANT_Msk (0xFFUL << FICR_SIPINFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ + +/* Register: FICR_INFO_DEVICEID */ +/* Description: Description collection: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N9120 (0x9120UL) /*!< nRF9120 */ +#define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part Variant, Hardware version and Production configuration */ + +/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ +#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_CF (0x2002UL) /*!< CFxx - 236 ball wlCSP */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ + +/* Register: FICR_INFO_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ +#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL) /*!< 4 kByte */ + +/* Register: FICR_INFO_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */ +#define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ +#define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL) /*!< 256 pages */ + +/* Register: FICR_INFO_DEVICETYPE */ +/* Description: Device type */ + +/* Bits 31..0 : Device type */ +#define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */ +#define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */ +#define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL) /*!< Device is an physical DIE */ +#define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */ + +/* Register: FICR_TRIMCNF_ADDR */ +/* Description: Description cluster: Address */ + +/* Bits 31..0 : Address */ +#define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */ +#define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */ + +/* Register: FICR_TRIMCNF_DATA */ +/* Description: Description cluster: Data */ + +/* Bits 31..0 : Data */ +#define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */ +#define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */ + +/* Register: FICR_TRNG90B_BYTES */ +/* Description: Amount of bytes for the required entropy bits */ + +/* Bits 31..0 : Amount of bytes for the required entropy bits */ +#define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */ +#define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */ + +/* Register: FICR_TRNG90B_RCCUTOFF */ +/* Description: Repetition counter cutoff */ + +/* Bits 31..0 : Repetition counter cutoff */ +#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */ +#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */ + +/* Register: FICR_TRNG90B_APCUTOFF */ +/* Description: Adaptive proportion cutoff */ + +/* Bits 31..0 : Adaptive proportion cutoff */ +#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */ +#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */ + +/* Register: FICR_TRNG90B_STARTUP */ +/* Description: Amount of bytes for the startup tests */ + +/* Bits 31..0 : Amount of bytes for the startup tests */ +#define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */ +#define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */ + +/* Register: FICR_TRNG90B_ROSC1 */ +/* Description: Sample count for ring oscillator 1 */ + +/* Bits 31..0 : Sample count for ring oscillator 1 */ +#define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */ +#define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */ + +/* Register: FICR_TRNG90B_ROSC2 */ +/* Description: Sample count for ring oscillator 2 */ + +/* Bits 31..0 : Sample count for ring oscillator 2 */ +#define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */ +#define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */ + +/* Register: FICR_TRNG90B_ROSC3 */ +/* Description: Sample count for ring oscillator 3 */ + +/* Bits 31..0 : Sample count for ring oscillator 3 */ +#define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */ +#define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */ + +/* Register: FICR_TRNG90B_ROSC4 */ +/* Description: Sample count for ring oscillator 4 */ + +/* Bits 31..0 : Sample count for ring oscillator 4 */ +#define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */ +#define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events 0 */ + +/* Register: GPIOTE_TASKS_OUT */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_TASKS_SET */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_TASKS_CLR */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_SUBSCRIBE_OUT */ +/* Description: Description collection: Subscribe configuration for task OUT[n] */ + +/* Bit 31 : */ +#define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */ +#define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */ +#define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */ +#define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */ +#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: GPIOTE_SUBSCRIBE_SET */ +/* Description: Description collection: Subscribe configuration for task SET[n] */ + +/* Bit 31 : */ +#define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */ +#define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */ +#define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */ +#define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */ +#define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: GPIOTE_SUBSCRIBE_CLR */ +/* Description: Description collection: Subscribe configuration for task CLR[n] */ + +/* Bit 31 : */ +#define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */ +#define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */ +#define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */ +#define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */ +#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: GPIOTE_EVENTS_IN */ +/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ + +/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ + +/* Register: GPIOTE_EVENTS_PORT */ +/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ + +/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ + +/* Register: GPIOTE_PUBLISH_IN */ +/* Description: Description collection: Publish configuration for event IN[n] */ + +/* Bit 31 : */ +#define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */ +#define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */ +#define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */ +#define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event IN[n] will publish to */ +#define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: GPIOTE_PUBLISH_PORT */ +/* Description: Publish configuration for event PORT */ + +/* Bit 31 : */ +#define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */ +#define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */ +#define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */ +#define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event PORT will publish to */ +#define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to enable interrupt for event PORT */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to disable interrupt for event PORT */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: I2S */ +/* Description: Inter-IC Sound 0 */ + +/* Register: I2S_TASKS_START */ +/* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ + +/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ +#define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: I2S_TASKS_STOP */ +/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ + +/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ +#define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: I2S_SUBSCRIBE_START */ +/* Description: Subscribe configuration for task START */ + +/* Bit 31 : */ +#define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ +#define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ +#define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ +#define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task START will subscribe to */ +#define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: I2S_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: I2S_EVENTS_RXPTRUPD */ +/* Description: The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ + +/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */ + +/* Register: I2S_EVENTS_STOPPED */ +/* Description: I2S transfer stopped. */ + +/* Bit 0 : I2S transfer stopped. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: I2S_EVENTS_TXPTRUPD */ +/* Description: The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ + +/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */ + +/* Register: I2S_PUBLISH_RXPTRUPD */ +/* Description: Publish configuration for event RXPTRUPD */ + +/* Bit 31 : */ +#define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ +#define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ +#define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */ +#define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */ +#define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: I2S_PUBLISH_STOPPED */ +/* Description: Publish configuration for event STOPPED */ + +/* Bit 31 : */ +#define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ +#define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ +#define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ +#define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ +#define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: I2S_PUBLISH_TXPTRUPD */ +/* Description: Publish configuration for event TXPTRUPD */ + +/* Bit 31 : */ +#define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ +#define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ +#define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */ +#define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */ +#define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: I2S_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ +#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event STOPPED */ +#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ +#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ +#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event STOPPED */ +#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ +#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ + +/* Register: I2S_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ +#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event STOPPED */ +#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ +#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Register: I2S_ENABLE */ +/* Description: Enable I2S module. */ + +/* Bit 0 : Enable I2S module. */ +#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_CONFIG_MODE */ +/* Description: I2S mode. */ + +/* Bit 0 : I2S mode. */ +#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ + +/* Register: I2S_CONFIG_RXEN */ +/* Description: Reception (RX) enable. */ + +/* Bit 0 : Reception (RX) enable. */ +#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: I2S_CONFIG_TXEN */ +/* Description: Transmission (TX) enable. */ + +/* Bit 0 : Transmission (TX) enable. */ +#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ + +/* Register: I2S_CONFIG_MCKEN */ +/* Description: Master clock generator enable. */ + +/* Bit 0 : Master clock generator enable. */ +#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + +/* Register: I2S_CONFIG_MCKFREQ */ +/* Description: Master clock generator frequency. */ + +/* Bits 31..0 : Master clock generator frequency. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ + +/* Register: I2S_CONFIG_RATIO */ +/* Description: MCK / LRCK ratio. */ + +/* Bits 3..0 : MCK / LRCK ratio. */ +#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ + +/* Register: I2S_CONFIG_SWIDTH */ +/* Description: Sample width. */ + +/* Bits 1..0 : Sample width. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ + +/* Register: I2S_CONFIG_ALIGN */ +/* Description: Alignment of sample within a frame. */ + +/* Bit 0 : Alignment of sample within a frame. */ +#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ + +/* Register: I2S_CONFIG_FORMAT */ +/* Description: Frame format. */ + +/* Bit 0 : Frame format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ + +/* Register: I2S_CONFIG_CHANNELS */ +/* Description: Enable channels. */ + +/* Bits 1..0 : Enable channels. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ + +/* Register: I2S_RXD_PTR */ +/* Description: Receive buffer RAM start address. */ + +/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ +#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_TXD_PTR */ +/* Description: Transmit buffer RAM start address. */ + +/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ +#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_RXTXD_MAXCNT */ +/* Description: Size of RXD and TXD buffers. */ + +/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: I2S_PSEL_MCK */ +/* Description: Pin select for MCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SCK */ +/* Description: Pin select for SCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_LRCK */ +/* Description: Pin select for LRCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDIN */ +/* Description: Pin select for SDIN signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDOUT */ +/* Description: Pin select for SDOUT signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: IPC */ +/* Description: Interprocessor communication 0 */ + +/* Register: IPC_TASKS_SEND */ +/* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */ + +/* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */ +#define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */ +#define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */ +#define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: IPC_SUBSCRIBE_SEND */ +/* Description: Description collection: Subscribe configuration for task SEND[n] */ + +/* Bit 31 : */ +#define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */ +#define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */ +#define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */ +#define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */ +#define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: IPC_EVENTS_RECEIVE */ +/* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ + +/* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ +#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */ +#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */ +#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */ +#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */ + +/* Register: IPC_PUBLISH_RECEIVE */ +/* Description: Description collection: Publish configuration for event RECEIVE[n] */ + +/* Bit 31 : */ +#define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */ +#define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */ +#define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */ +#define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */ +#define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: IPC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ +#define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ +#define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ +#define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ +#define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ +#define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ +#define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ +#define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ +#define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ +#define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ +#define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ +#define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ +#define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ +#define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ +#define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ +#define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ +#define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ +#define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ +#define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ +#define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ +#define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ +#define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ +#define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ +#define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ +#define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */ + +/* Register: IPC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ +#define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ +#define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ +#define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ +#define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ +#define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ +#define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ +#define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ +#define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ +#define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ +#define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ +#define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ +#define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ +#define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ +#define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ +#define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ +#define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ +#define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ +#define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ +#define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ +#define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ +#define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ +#define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ +#define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ +#define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */ + +/* Register: IPC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ +#define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ +#define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ +#define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ +#define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ +#define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ +#define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ +#define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ +#define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ +#define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ +#define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ +#define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ +#define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ +#define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ +#define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ +#define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ +#define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ +#define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ +#define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ +#define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ +#define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ +#define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ +#define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ +#define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ +#define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */ + +/* Register: IPC_INTPEND */ +/* Description: Pending interrupts */ + +/* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ +#define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ +#define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ +#define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */ + +/* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ +#define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ +#define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ +#define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */ + +/* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ +#define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ +#define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ +#define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */ + +/* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ +#define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ +#define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ +#define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */ + +/* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ +#define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ +#define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ +#define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */ + +/* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ +#define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ +#define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ +#define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */ + +/* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ +#define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ +#define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ +#define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */ + +/* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ +#define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ +#define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ +#define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */ + +/* Register: IPC_SEND_CNF */ +/* Description: Description collection: Send event configuration for TASKS_SEND[n] */ + +/* Bit 7 : Enable broadcasting on IPC channel 7 */ +#define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ +#define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ +#define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */ + +/* Bit 6 : Enable broadcasting on IPC channel 6 */ +#define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ +#define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ +#define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */ + +/* Bit 5 : Enable broadcasting on IPC channel 5 */ +#define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ +#define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ +#define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */ + +/* Bit 4 : Enable broadcasting on IPC channel 4 */ +#define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ +#define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ +#define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */ + +/* Bit 3 : Enable broadcasting on IPC channel 3 */ +#define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ +#define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ +#define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */ + +/* Bit 2 : Enable broadcasting on IPC channel 2 */ +#define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ +#define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ +#define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */ + +/* Bit 1 : Enable broadcasting on IPC channel 1 */ +#define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ +#define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ +#define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */ + +/* Bit 0 : Enable broadcasting on IPC channel 0 */ +#define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ +#define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ +#define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */ + +/* Register: IPC_RECEIVE_CNF */ +/* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */ + +/* Bit 7 : Enable subscription to IPC channel 7 */ +#define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ +#define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ +#define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */ + +/* Bit 6 : Enable subscription to IPC channel 6 */ +#define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ +#define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ +#define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */ + +/* Bit 5 : Enable subscription to IPC channel 5 */ +#define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ +#define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ +#define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */ + +/* Bit 4 : Enable subscription to IPC channel 4 */ +#define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ +#define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ +#define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */ + +/* Bit 3 : Enable subscription to IPC channel 3 */ +#define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ +#define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ +#define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */ + +/* Bit 2 : Enable subscription to IPC channel 2 */ +#define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ +#define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ +#define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */ + +/* Bit 1 : Enable subscription to IPC channel 1 */ +#define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ +#define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ +#define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */ + +/* Bit 0 : Enable subscription to IPC channel 0 */ +#define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ +#define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ +#define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */ + +/* Register: IPC_GPMEM */ +/* Description: Description collection: General purpose memory */ + +/* Bits 31..0 : General purpose memory */ +#define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */ +#define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */ + + +/* Peripheral: KMU */ +/* Description: Key management unit 0 */ + +/* Register: KMU_TASKS_PUSH_KEYSLOT */ +/* Description: Push a key slot over secure APB */ + +/* Bit 0 : Push a key slot over secure APB */ +#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */ +#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */ +#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */ + +/* Register: KMU_EVENTS_KEYSLOT_PUSHED */ +/* Description: Key slot successfully pushed over secure APB */ + +/* Bit 0 : Key slot successfully pushed over secure APB */ +#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */ +#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */ +#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL) /*!< Event not generated */ +#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */ + +/* Register: KMU_EVENTS_KEYSLOT_REVOKED */ +/* Description: Key slot has been revoked and cannot be tasked for selection */ + +/* Bit 0 : Key slot has been revoked and cannot be tasked for selection */ +#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */ +#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */ +#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL) /*!< Event not generated */ +#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL) /*!< Event generated */ + +/* Register: KMU_EVENTS_KEYSLOT_ERROR */ +/* Description: No key slot selected, no destination address defined, or error during push operation */ + +/* Bit 0 : No key slot selected, no destination address defined, or error during push operation */ +#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */ +#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */ +#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: KMU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */ +#define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ +#define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ +#define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL) /*!< Disable */ +#define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */ +#define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ +#define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ +#define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL) /*!< Disable */ +#define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */ +#define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ +#define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ +#define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL) /*!< Disable */ +#define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */ + +/* Register: KMU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */ +#define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ +#define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ +#define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */ +#define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ +#define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ +#define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */ +#define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */ +#define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */ +#define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ +#define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ +#define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */ +#define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */ +#define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */ + +/* Register: KMU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */ +#define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ +#define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ +#define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */ +#define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ +#define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ +#define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */ +#define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */ +#define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */ +#define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ +#define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ +#define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */ +#define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */ +#define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */ + +/* Register: KMU_INTPEND */ +/* Description: Pending interrupts */ + +/* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */ +#define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ +#define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ +#define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL) /*!< Read: Not pending */ +#define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */ + +/* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */ +#define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ +#define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ +#define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL) /*!< Read: Not pending */ +#define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */ + +/* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */ +#define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ +#define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ +#define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL) /*!< Read: Not pending */ +#define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */ + +/* Register: KMU_STATUS */ +/* Description: Status bits for KMU operation */ + +/* Bit 1 : Violation status */ +#define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */ +#define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */ +#define KMU_STATUS_BLOCKED_Disabled (0UL) /*!< No access violation detected */ +#define KMU_STATUS_BLOCKED_Enabled (1UL) /*!< Access violation detected and blocked */ + +/* Bit 0 : Key slot ID successfully selected by the KMU */ +#define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */ +#define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define KMU_STATUS_SELECTED_Disabled (0UL) /*!< No key slot ID selected by KMU */ +#define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */ + +/* Register: KMU_SELECTKEYSLOT */ +/* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */ + +/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */ +#define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */ +#define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */ + + +/* Peripheral: NVMC */ +/* Description: Non-volatile memory controller 0 */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_READYNEXT */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC can accept a new write operation */ +#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ +#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ +#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ +#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ +#define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPAGEPARTIALCFG */ +/* Description: Register for partial erase configuration */ + +/* Bits 6..0 : Duration of the partial erase in milliseconds */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ + +/* Register: NVMC_ICACHECNF */ +/* Description: I-code cache configuration register */ + +/* Bit 8 : Cache profiling enable */ +#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ + +/* Bit 0 : Cache enable */ +#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ + +/* Register: NVMC_IHIT */ +/* Description: I-code cache hit counter */ + +/* Bits 31..0 : Number of cache hits Write zero to clear */ +#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ +#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ + +/* Register: NVMC_IMISS */ +/* Description: I-code cache miss counter */ + +/* Bits 31..0 : Number of cache misses Write zero to clear */ +#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ +#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + +/* Register: NVMC_CONFIGNS */ +/* Description: Unspecified */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */ +#define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_WRITEUICRNS */ +/* Description: Non-secure APPROTECT enable register */ + +/* Bits 31..4 : Key to write in order to validate the write operation */ +#define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */ +#define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */ +#define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */ + +/* Bit 0 : Allow non-secure code to set APPROTECT */ +#define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */ +#define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */ +#define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 0 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */ + +/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ + +/* Register: GPIO_DETECTMODE_SEC */ +/* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */ + +/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ +#define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */ + +/* Register: PDM_TASKS_START */ +/* Description: Starts continuous PDM transfer */ + +/* Bit 0 : Starts continuous PDM transfer */ +#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: PDM_TASKS_STOP */ +/* Description: Stops PDM transfer */ + +/* Bit 0 : Stops PDM transfer */ +#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PDM_SUBSCRIBE_START */ +/* Description: Subscribe configuration for task START */ + +/* Bit 31 : */ +#define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ +#define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ +#define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ +#define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task START will subscribe to */ +#define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PDM_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PDM_EVENTS_STARTED */ +/* Description: PDM transfer has started */ + +/* Bit 0 : PDM transfer has started */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_EVENTS_STOPPED */ +/* Description: PDM transfer has finished */ + +/* Bit 0 : PDM transfer has finished */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_EVENTS_END */ +/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ + +/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ +#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_PUBLISH_STARTED */ +/* Description: Publish configuration for event STARTED */ + +/* Bit 31 : */ +#define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STARTED will publish to */ +#define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PDM_PUBLISH_STOPPED */ +/* Description: Publish configuration for event STOPPED */ + +/* Bit 31 : */ +#define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ +#define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ +#define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ +#define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ +#define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PDM_PUBLISH_END */ +/* Description: Publish configuration for event END */ + +/* Bit 31 : */ +#define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ +#define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ +#define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ +#define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event END will publish to */ +#define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for event END */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event STARTED */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event END */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event END */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency configuration. */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */ +#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ + +/* Register: PDM_RATIO */ +/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ + +/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */ +#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */ +#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control 0 */ + +/* Register: POWER_TASKS_PWMREQSTART */ +/* Description: Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */ + +/* Bit 0 : Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */ +#define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos (0UL) /*!< Position of TASKS_PWMREQSTART field. */ +#define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Msk (0x1UL << POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos) /*!< Bit mask of TASKS_PWMREQSTART field. */ +#define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_TASKS_PWMREQSTOP */ +/* Description: Stop requesting forcing PWM mode in external DC/DC voltage regulator */ + +/* Bit 0 : Stop requesting forcing PWM mode in external DC/DC voltage regulator */ +#define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos (0UL) /*!< Position of TASKS_PWMREQSTOP field. */ +#define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Msk (0x1UL << POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos) /*!< Bit mask of TASKS_PWMREQSTOP field. */ +#define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_TASKS_CONSTLAT */ +/* Description: Enable constant latency mode. */ + +/* Bit 0 : Enable constant latency mode. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_TASKS_LOWPWR */ +/* Description: Enable low power mode (variable latency) */ + +/* Bit 0 : Enable low power mode (variable latency) */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_SUBSCRIBE_PWMREQSTART */ +/* Description: Subscribe configuration for task PWMREQSTART */ + +/* Bit 31 : */ +#define POWER_SUBSCRIBE_PWMREQSTART_EN_Pos (31UL) /*!< Position of EN field. */ +#define POWER_SUBSCRIBE_PWMREQSTART_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTART_EN_Pos) /*!< Bit mask of EN field. */ +#define POWER_SUBSCRIBE_PWMREQSTART_EN_Disabled (0UL) /*!< Disable subscription */ +#define POWER_SUBSCRIBE_PWMREQSTART_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task PWMREQSTART will subscribe to */ +#define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: POWER_SUBSCRIBE_PWMREQSTOP */ +/* Description: Subscribe configuration for task PWMREQSTOP */ + +/* Bit 31 : */ +#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos) /*!< Bit mask of EN field. */ +#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task PWMREQSTOP will subscribe to */ +#define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: POWER_SUBSCRIBE_CONSTLAT */ +/* Description: Subscribe configuration for task CONSTLAT */ + +/* Bit 31 : */ +#define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */ +#define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */ +#define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */ +#define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */ +#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: POWER_SUBSCRIBE_LOWPWR */ +/* Description: Subscribe configuration for task LOWPWR */ + +/* Bit 31 : */ +#define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */ +#define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */ +#define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */ +#define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */ +#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: POWER_EVENTS_POFWARN */ +/* Description: Power failure warning */ + +/* Bit 0 : Power failure warning */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_SLEEPENTER */ +/* Description: CPU entered WFI/WFE sleep */ + +/* Bit 0 : CPU entered WFI/WFE sleep */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_SLEEPEXIT */ +/* Description: CPU exited WFI/WFE sleep */ + +/* Bit 0 : CPU exited WFI/WFE sleep */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_PUBLISH_POFWARN */ +/* Description: Publish configuration for event POFWARN */ + +/* Bit 31 : */ +#define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */ +#define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */ +#define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */ +#define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event POFWARN will publish to */ +#define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: POWER_PUBLISH_SLEEPENTER */ +/* Description: Publish configuration for event SLEEPENTER */ + +/* Bit 31 : */ +#define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */ +#define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */ +#define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */ +#define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */ +#define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: POWER_PUBLISH_SLEEPEXIT */ +/* Description: Publish configuration for event SLEEPEXIT */ + +/* Bit 31 : */ +#define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */ +#define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */ +#define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */ +#define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */ +#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: POWER_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */ +#define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */ +#define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event SLEEPENTER */ +#define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */ +#define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event POFWARN */ +#define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */ +#define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 18 : Reset triggered through CTRL-AP */ +#define POWER_RESETREAS_CTRLAP_Pos (18UL) /*!< Position of CTRLAP field. */ +#define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */ +#define POWER_RESETREAS_CTRLAP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */ + +/* Bit 17 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (17UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset from AIRCR.SYSRESETREQ detected */ +#define POWER_RESETREAS_SREQ_Pos (16UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 4 : Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (4UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from global watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_POWERSTATUS */ +/* Description: Modem domain power status */ + +/* Bit 0 : LTE modem domain status */ +#define POWER_POWERSTATUS_LTEMODEM_Pos (0UL) /*!< Position of LTEMODEM field. */ +#define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos) /*!< Bit mask of LTEMODEM field. */ +#define POWER_POWERSTATUS_LTEMODEM_OFF (0UL) /*!< LTE modem domain is powered off */ +#define POWER_POWERSTATUS_LTEMODEM_ON (1UL) /*!< LTE modem domain is powered on */ + +/* Register: POWER_GPREGRET */ +/* Description: Description collection: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_LTEMODEM_STARTN */ +/* Description: Start LTE modem */ + +/* Bit 0 : Start LTE modem */ +#define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */ +#define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */ +#define POWER_LTEMODEM_STARTN_STARTN_Start (0UL) /*!< Start LTE modem */ +#define POWER_LTEMODEM_STARTN_STARTN_Hold (1UL) /*!< Hold LTE modem disabled */ + +/* Register: POWER_LTEMODEM_FORCEOFF */ +/* Description: Force off LTE modem */ + +/* Bit 0 : Force off LTE modem */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off active */ + + +/* Peripheral: PWM */ +/* Description: Pulse width modulation unit 0 */ + +/* Register: PWM_TASKS_STOP */ +/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ + +/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ +#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_TASKS_SEQSTART */ +/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ + +/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_TASKS_NEXTSTEP */ +/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ + +/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PWM_SUBSCRIBE_SEQSTART */ +/* Description: Description collection: Subscribe configuration for task SEQSTART[n] */ + +/* Bit 31 : */ +#define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */ +#define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */ +#define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */ +#define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */ +#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PWM_SUBSCRIBE_NEXTSTEP */ +/* Description: Subscribe configuration for task NEXTSTEP */ + +/* Bit 31 : */ +#define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */ +#define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */ +#define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */ +#define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */ +#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PWM_EVENTS_STOPPED */ +/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ + +/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_SEQSTARTED */ +/* Description: Description collection: First PWM period started on sequence n */ + +/* Bit 0 : First PWM period started on sequence n */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_SEQEND */ +/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + +/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_PWMPERIODEND */ +/* Description: Emitted at the end of each PWM period */ + +/* Bit 0 : Emitted at the end of each PWM period */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_LOOPSDONE */ +/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + +/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_PUBLISH_STOPPED */ +/* Description: Publish configuration for event STOPPED */ + +/* Bit 31 : */ +#define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ +#define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ +#define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ +#define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PWM_PUBLISH_SEQSTARTED */ +/* Description: Description collection: Publish configuration for event SEQSTARTED[n] */ + +/* Bit 31 : */ +#define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */ +#define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PWM_PUBLISH_SEQEND */ +/* Description: Description collection: Publish configuration for event SEQEND[n] */ + +/* Bit 31 : */ +#define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */ +#define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */ +#define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */ +#define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PWM_PUBLISH_PWMPERIODEND */ +/* Description: Publish configuration for event PWMPERIODEND */ + +/* Bit 31 : */ +#define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */ +#define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */ +#define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */ +#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PWM_PUBLISH_LOOPSDONE */ +/* Description: Publish configuration for event LOOPSDONE */ + +/* Bit 31 : */ +#define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */ +#define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */ +#define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */ +#define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up mode or up-and-down mode for the counter */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Prescaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Number of playbacks of a loop */ + +/* Bits 15..0 : Number of playbacks of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster: Beginning address in RAM of this sequence */ + +/* Bits 31..0 : Beginning address in RAM of this sequence */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster: Number of values (duty cycles) in this sequence */ + +/* Bits 14..0 : Number of values (duty cycles) in this sequence */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ + +/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection: Output pin select for PWM channel n */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: REGULATORS */ +/* Description: Voltage regulators control 0 */ + +/* Register: REGULATORS_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */ + +/* Register: REGULATORS_EXTPOFCON */ +/* Description: External power failure warning configuration */ + +/* Bit 0 : Enable or disable external power failure warning */ +#define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define REGULATORS_EXTPOFCON_POF_Disabled (0UL) /*!< Disable */ +#define REGULATORS_EXTPOFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: REGULATORS_DCDCEN */ +/* Description: Enable DC/DC mode of the main voltage regulator. */ + +/* Bit 0 : Enable DC/DC converter */ +#define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define REGULATORS_DCDCEN_DCDCEN_Disabled (0UL) /*!< DC/DC mode is disabled */ +#define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL) /*!< DC/DC mode is enabled */ + + +/* Peripheral: RTC */ +/* Description: Real-time counter 0 */ + +/* Register: RTC_TASKS_START */ +/* Description: Start RTC counter */ + +/* Bit 0 : Start RTC counter */ +#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_STOP */ +/* Description: Stop RTC counter */ + +/* Bit 0 : Stop RTC counter */ +#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_CLEAR */ +/* Description: Clear RTC counter */ + +/* Bit 0 : Clear RTC counter */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_TRIGOVRFLW */ +/* Description: Set counter to 0xFFFFF0 */ + +/* Bit 0 : Set counter to 0xFFFFF0 */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_SUBSCRIBE_START */ +/* Description: Subscribe configuration for task START */ + +/* Bit 31 : */ +#define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ +#define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ +#define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ +#define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task START will subscribe to */ +#define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: RTC_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: RTC_SUBSCRIBE_CLEAR */ +/* Description: Subscribe configuration for task CLEAR */ + +/* Bit 31 : */ +#define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ +#define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ +#define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ +#define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ +#define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: RTC_SUBSCRIBE_TRIGOVRFLW */ +/* Description: Subscribe configuration for task TRIGOVRFLW */ + +/* Bit 31 : */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: RTC_EVENTS_TICK */ +/* Description: Event on counter increment */ + +/* Bit 0 : Event on counter increment */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_EVENTS_OVRFLW */ +/* Description: Event on counter overflow */ + +/* Bit 0 : Event on counter overflow */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_EVENTS_COMPARE */ +/* Description: Description collection: Compare event on CC[n] match */ + +/* Bit 0 : Compare event on CC[n] match */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_PUBLISH_TICK */ +/* Description: Publish configuration for event TICK */ + +/* Bit 31 : */ +#define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */ +#define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */ +#define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */ +#define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TICK will publish to */ +#define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: RTC_PUBLISH_OVRFLW */ +/* Description: Publish configuration for event OVRFLW */ + +/* Bit 31 : */ +#define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ +#define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */ +#define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */ +#define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event OVRFLW will publish to */ +#define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: RTC_PUBLISH_COMPARE */ +/* Description: Description collection: Publish configuration for event COMPARE[n] */ + +/* Bit 31 : */ +#define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ +#define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ +#define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ +#define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ +#define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event TICK */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event TICK */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable event routing for event OVRFLW */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable event routing for event TICK */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable event routing for event TICK */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable event routing for event TICK */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current counter value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection: Compare register n */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Analog to Digital Converter 0 */ + +/* Register: SAADC_TASKS_START */ +/* Description: Start the ADC and prepare the result buffer in RAM */ + +/* Bit 0 : Start the ADC and prepare the result buffer in RAM */ +#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_SAMPLE */ +/* Description: Take one ADC sample, if scan is enabled all channels are sampled */ + +/* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_STOP */ +/* Description: Stop the ADC and terminate any on-going conversion */ + +/* Bit 0 : Stop the ADC and terminate any on-going conversion */ +#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_CALIBRATEOFFSET */ +/* Description: Starts offset auto-calibration */ + +/* Bit 0 : Starts offset auto-calibration */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_SUBSCRIBE_START */ +/* Description: Subscribe configuration for task START */ + +/* Bit 31 : */ +#define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ +#define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task START will subscribe to */ +#define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_SUBSCRIBE_SAMPLE */ +/* Description: Subscribe configuration for task SAMPLE */ + +/* Bit 31 : */ +#define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */ +#define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */ +#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */ +/* Description: Subscribe configuration for task CALIBRATEOFFSET */ + +/* Bit 31 : */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_EVENTS_STARTED */ +/* Description: The ADC has started */ + +/* Bit 0 : The ADC has started */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_END */ +/* Description: The ADC has filled up the Result buffer */ + +/* Bit 0 : The ADC has filled up the Result buffer */ +#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_DONE */ +/* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ + +/* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_RESULTDONE */ +/* Description: A result is ready to get transferred to RAM. */ + +/* Bit 0 : A result is ready to get transferred to RAM. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CALIBRATEDONE */ +/* Description: Calibration is complete */ + +/* Bit 0 : Calibration is complete */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_STOPPED */ +/* Description: The ADC has stopped */ + +/* Bit 0 : The ADC has stopped */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CH_LIMITH */ +/* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */ + +/* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CH_LIMITL */ +/* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */ + +/* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_PUBLISH_STARTED */ +/* Description: Publish configuration for event STARTED */ + +/* Bit 31 : */ +#define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STARTED will publish to */ +#define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_PUBLISH_END */ +/* Description: Publish configuration for event END */ + +/* Bit 31 : */ +#define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event END will publish to */ +#define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_PUBLISH_DONE */ +/* Description: Publish configuration for event DONE */ + +/* Bit 31 : */ +#define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event DONE will publish to */ +#define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_PUBLISH_RESULTDONE */ +/* Description: Publish configuration for event RESULTDONE */ + +/* Bit 31 : */ +#define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */ +#define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_PUBLISH_CALIBRATEDONE */ +/* Description: Publish configuration for event CALIBRATEDONE */ + +/* Bit 31 : */ +#define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */ +#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_PUBLISH_STOPPED */ +/* Description: Publish configuration for event STOPPED */ + +/* Bit 31 : */ +#define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ +#define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_PUBLISH_CH_LIMITH */ +/* Description: Description cluster: Publish configuration for event CH[n].LIMITH */ + +/* Bit 31 : */ +#define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */ +#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_PUBLISH_CH_LIMITL */ +/* Description: Description cluster: Publish configuration for event CH[n].LIMITL */ + +/* Bit 31 : */ +#define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */ +#define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */ +#define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */ +#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event STOPPED */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event RESULTDONE */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event DONE */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event END */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event STARTED */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event STOPPED */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event DONE */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event END */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event STOPPED */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event DONE */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event END */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Single conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable ADC */ + +/* Bit 0 : Enable or disable ADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster: Input positive pin selection for CH[n] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDDGPIO (9UL) /*!< VDD_GPIO */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster: Input negative pin selection for CH[n] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD_GPIO (9UL) /*!< VDD_GPIO */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster: Input configuration for CH[n] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD_GPIO/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD_GPIO */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD_GPIO */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster: High/low limits for event monitoring a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 14..0 : Maximum number of buffer words to transfer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of buffer words transferred since last START */ + +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_TASKS_START */ +/* Description: Start SPI transaction */ + +/* Bit 0 : Start SPI transaction */ +#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_STOP */ +/* Description: Stop SPI transaction */ + +/* Bit 0 : Stop SPI transaction */ +#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_SUSPEND */ +/* Description: Suspend SPI transaction */ + +/* Bit 0 : Suspend SPI transaction */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_RESUME */ +/* Description: Resume SPI transaction */ + +/* Bit 0 : Resume SPI transaction */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_SUBSCRIBE_START */ +/* Description: Subscribe configuration for task START */ + +/* Bit 31 : */ +#define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ +#define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task START will subscribe to */ +#define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_SUBSCRIBE_SUSPEND */ +/* Description: Subscribe configuration for task SUSPEND */ + +/* Bit 31 : */ +#define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ +#define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ +#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_SUBSCRIBE_RESUME */ +/* Description: Subscribe configuration for task RESUME */ + +/* Bit 31 : */ +#define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ +#define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ +#define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_EVENTS_STOPPED */ +/* Description: SPI transaction has stopped */ + +/* Bit 0 : SPI transaction has stopped */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : End of RXD buffer reached */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_END */ +/* Description: End of RXD buffer and TXD buffer reached */ + +/* Bit 0 : End of RXD buffer and TXD buffer reached */ +#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_ENDTX */ +/* Description: End of TXD buffer reached */ + +/* Bit 0 : End of TXD buffer reached */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_STARTED */ +/* Description: Transaction started */ + +/* Bit 0 : Transaction started */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_PUBLISH_STOPPED */ +/* Description: Publish configuration for event STOPPED */ + +/* Bit 31 : */ +#define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ +#define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_PUBLISH_ENDRX */ +/* Description: Publish configuration for event ENDRX */ + +/* Bit 31 : */ +#define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ENDRX will publish to */ +#define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_PUBLISH_END */ +/* Description: Publish configuration for event END */ + +/* Bit 31 : */ +#define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event END will publish to */ +#define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_PUBLISH_ENDTX */ +/* Description: Publish configuration for event ENDTX */ + +/* Bit 31 : */ +#define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ENDTX will publish to */ +#define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_PUBLISH_STARTED */ +/* Description: Publish configuration for event STARTED */ + +/* Bit 31 : */ +#define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STARTED will publish to */ +#define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 17 : Shortcut between event END and task START */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for event STARTED */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event END */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for event STARTED */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event END */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 12..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 12..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 12..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 12..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. Character clocked out in case an over-read of the TXD buffer. */ + +/* Bits 7..0 : Over-read character. Character clocked out in case an over-read of the TXD buffer. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_TASKS_ACQUIRE */ +/* Description: Acquire SPI semaphore */ + +/* Bit 0 : Acquire SPI semaphore */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIS_TASKS_RELEASE */ +/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ + +/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIS_SUBSCRIBE_ACQUIRE */ +/* Description: Subscribe configuration for task ACQUIRE */ + +/* Bit 31 : */ +#define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */ +#define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */ +#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIS_SUBSCRIBE_RELEASE */ +/* Description: Subscribe configuration for task RELEASE */ + +/* Bit 31 : */ +#define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */ +#define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */ +#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIS_EVENTS_END */ +/* Description: Granted transaction completed */ + +/* Bit 0 : Granted transaction completed */ +#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : End of RXD buffer reached */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_EVENTS_ACQUIRED */ +/* Description: Semaphore acquired */ + +/* Bit 0 : Semaphore acquired */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_PUBLISH_END */ +/* Description: Publish configuration for event END */ + +/* Bit 31 : */ +#define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event END will publish to */ +#define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIS_PUBLISH_ENDRX */ +/* Description: Publish configuration for event ENDRX */ + +/* Bit 31 : */ +#define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ENDRX will publish to */ +#define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIS_PUBLISH_ACQUIRED */ +/* Description: Publish configuration for event ACQUIRED */ + +/* Bit 31 : */ +#define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */ +#define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */ +#define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 2 : Shortcut between event END and task ACQUIRE */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event END */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event END */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 12..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 12..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 12..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 12..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPU */ +/* Description: System protection unit */ + +/* Register: SPU_EVENTS_RAMACCERR */ +/* Description: A security violation has been detected for the RAM memory space */ + +/* Bit 0 : A security violation has been detected for the RAM memory space */ +#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */ +#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */ +#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL) /*!< Event not generated */ +#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL) /*!< Event generated */ + +/* Register: SPU_EVENTS_FLASHACCERR */ +/* Description: A security violation has been detected for the flash memory space */ + +/* Bit 0 : A security violation has been detected for the flash memory space */ +#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */ +#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */ +#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL) /*!< Event not generated */ +#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL) /*!< Event generated */ + +/* Register: SPU_EVENTS_PERIPHACCERR */ +/* Description: A security violation has been detected on one or several peripherals */ + +/* Bit 0 : A security violation has been detected on one or several peripherals */ +#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */ +#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */ +#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL) /*!< Event not generated */ +#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL) /*!< Event generated */ + +/* Register: SPU_PUBLISH_RAMACCERR */ +/* Description: Publish configuration for event RAMACCERR */ + +/* Bit 31 : */ +#define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */ +#define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */ +#define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPU_PUBLISH_FLASHACCERR */ +/* Description: Publish configuration for event FLASHACCERR */ + +/* Bit 31 : */ +#define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */ +#define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */ +#define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPU_PUBLISH_PERIPHACCERR */ +/* Description: Publish configuration for event PERIPHACCERR */ + +/* Bit 31 : */ +#define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */ +#define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */ +#define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */ +#define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */ +#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: SPU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */ +#define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ +#define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ +#define SPU_INTEN_PERIPHACCERR_Disabled (0UL) /*!< Disable */ +#define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event FLASHACCERR */ +#define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ +#define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ +#define SPU_INTEN_FLASHACCERR_Disabled (0UL) /*!< Disable */ +#define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event RAMACCERR */ +#define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ +#define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ +#define SPU_INTEN_RAMACCERR_Disabled (0UL) /*!< Disable */ +#define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */ + +/* Register: SPU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */ +#define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ +#define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ +#define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */ +#define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */ +#define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */ +#define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ +#define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ +#define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */ +#define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */ +#define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */ +#define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ +#define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ +#define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */ +#define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */ +#define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */ + +/* Register: SPU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */ +#define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ +#define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ +#define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */ +#define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */ +#define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */ +#define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ +#define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ +#define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */ +#define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */ +#define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */ +#define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ +#define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ +#define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */ +#define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */ +#define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */ + +/* Register: SPU_CAP */ +/* Description: Show implemented features for the current device */ + +/* Bit 0 : Show ARM TrustZone status */ +#define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */ +#define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */ +#define SPU_CAP_TZM_NotAvailable (0UL) /*!< ARM TrustZone support not available */ +#define SPU_CAP_TZM_Enabled (1UL) /*!< ARM TrustZone support is available */ + +/* Register: SPU_EXTDOMAIN_PERM */ +/* Description: Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n */ + +/* Bit 8 : */ +#define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ +#define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ +#define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ + +/* Bit 4 : Peripheral security mapping */ +#define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ +#define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ +#define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */ +#define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */ + +/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ +#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ +#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ +#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */ +#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL) /*!< The bus access from this external domain always have the secure attribute set */ +#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */ + +/* Register: SPU_DPPI_PERM */ +/* Description: Description cluster: Select between secure and non-secure attribute for the DPPI channels. */ + +/* Bit 15 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */ +#define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */ +#define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */ + +/* Bit 14 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */ +#define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */ +#define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */ + +/* Bit 13 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */ +#define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */ +#define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */ + +/* Bit 12 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */ +#define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */ +#define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */ + +/* Bit 11 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */ +#define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */ +#define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */ + +/* Bit 10 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */ +#define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */ +#define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */ + +/* Bit 9 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */ +#define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */ +#define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */ + +/* Bit 8 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */ +#define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */ +#define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */ + +/* Bit 7 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */ +#define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */ +#define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */ + +/* Bit 6 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */ +#define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */ +#define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */ + +/* Bit 5 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */ +#define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */ +#define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */ + +/* Bit 4 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */ +#define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */ +#define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */ + +/* Bit 3 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */ +#define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */ +#define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */ + +/* Bit 2 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */ +#define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */ +#define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */ + +/* Bit 1 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */ +#define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */ +#define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */ + +/* Bit 0 : Select secure attribute. */ +#define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */ +#define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */ +#define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */ + +/* Register: SPU_DPPI_LOCK */ +/* Description: Description cluster: Prevent further modification of the corresponding PERM register */ + +/* Bit 0 : */ +#define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ +#define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_DPPI_LOCK_LOCK_Unlocked (0UL) /*!< DPPI[n].PERM register content can be changed */ +#define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next reset */ + +/* Register: SPU_GPIOPORT_PERM */ +/* Description: Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. */ + +/* Bit 31 : Select secure attribute attribute for PIN 31. */ +#define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */ + +/* Bit 30 : Select secure attribute attribute for PIN 30. */ +#define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */ + +/* Bit 29 : Select secure attribute attribute for PIN 29. */ +#define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */ + +/* Bit 28 : Select secure attribute attribute for PIN 28. */ +#define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */ + +/* Bit 27 : Select secure attribute attribute for PIN 27. */ +#define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */ + +/* Bit 26 : Select secure attribute attribute for PIN 26. */ +#define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */ + +/* Bit 25 : Select secure attribute attribute for PIN 25. */ +#define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */ + +/* Bit 24 : Select secure attribute attribute for PIN 24. */ +#define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */ + +/* Bit 23 : Select secure attribute attribute for PIN 23. */ +#define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */ + +/* Bit 22 : Select secure attribute attribute for PIN 22. */ +#define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */ + +/* Bit 21 : Select secure attribute attribute for PIN 21. */ +#define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */ + +/* Bit 20 : Select secure attribute attribute for PIN 20. */ +#define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */ + +/* Bit 19 : Select secure attribute attribute for PIN 19. */ +#define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */ + +/* Bit 18 : Select secure attribute attribute for PIN 18. */ +#define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */ + +/* Bit 17 : Select secure attribute attribute for PIN 17. */ +#define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */ + +/* Bit 16 : Select secure attribute attribute for PIN 16. */ +#define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */ + +/* Bit 15 : Select secure attribute attribute for PIN 15. */ +#define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */ + +/* Bit 14 : Select secure attribute attribute for PIN 14. */ +#define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */ + +/* Bit 13 : Select secure attribute attribute for PIN 13. */ +#define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */ + +/* Bit 12 : Select secure attribute attribute for PIN 12. */ +#define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */ + +/* Bit 11 : Select secure attribute attribute for PIN 11. */ +#define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */ + +/* Bit 10 : Select secure attribute attribute for PIN 10. */ +#define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */ + +/* Bit 9 : Select secure attribute attribute for PIN 9. */ +#define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */ + +/* Bit 8 : Select secure attribute attribute for PIN 8. */ +#define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */ + +/* Bit 7 : Select secure attribute attribute for PIN 7. */ +#define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */ + +/* Bit 6 : Select secure attribute attribute for PIN 6. */ +#define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */ + +/* Bit 5 : Select secure attribute attribute for PIN 5. */ +#define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */ + +/* Bit 4 : Select secure attribute attribute for PIN 4. */ +#define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */ + +/* Bit 3 : Select secure attribute attribute for PIN 3. */ +#define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */ + +/* Bit 2 : Select secure attribute attribute for PIN 2. */ +#define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */ + +/* Bit 1 : Select secure attribute attribute for PIN 1. */ +#define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */ + +/* Bit 0 : Select secure attribute attribute for PIN 0. */ +#define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */ + +/* Register: SPU_GPIOPORT_LOCK */ +/* Description: Description cluster: Prevent further modification of the corresponding PERM register */ + +/* Bit 0 : */ +#define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ +#define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL) /*!< GPIOPORT[n].PERM register content can be changed */ +#define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */ + +/* Register: SPU_FLASHNSC_REGION */ +/* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */ + +/* Bit 8 : */ +#define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */ +#define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */ +#define SPU_FLASHNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ + +/* Bits 4..0 : Region number */ +#define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ +#define SPU_FLASHNSC_REGION_REGION_Msk (0x1FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */ + +/* Register: SPU_FLASHNSC_SIZE */ +/* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */ + +/* Bit 8 : */ +#define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */ +#define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */ +#define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ + +/* Bits 3..0 : Size of the non-secure callable (NSC) region n */ +#define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ +#define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ +#define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ + +/* Register: SPU_RAMNSC_REGION */ +/* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */ + +/* Bit 8 : */ +#define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */ +#define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */ +#define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ + +/* Bits 4..0 : Region number */ +#define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ +#define SPU_RAMNSC_REGION_REGION_Msk (0x1FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */ + +/* Register: SPU_RAMNSC_SIZE */ +/* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */ + +/* Bit 8 : */ +#define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */ +#define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */ +#define SPU_RAMNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ + +/* Bits 3..0 : Size of the non-secure callable (NSC) region n */ +#define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ +#define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ +#define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ + +/* Register: SPU_FLASHREGION_PERM */ +/* Description: Description cluster: Access permissions for flash region n */ + +/* Bit 8 : */ +#define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ +#define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ +#define SPU_FLASHREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ + +/* Bit 4 : Security attribute for flash region n */ +#define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ +#define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ +#define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL) /*!< Flash region n security attribute is non-secure */ +#define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL) /*!< Flash region n security attribute is secure */ + +/* Bit 2 : Configure read permissions for flash region n */ +#define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */ +#define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */ +#define SPU_FLASHREGION_PERM_READ_Disable (0UL) /*!< Block read operation from flash region n */ +#define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */ + +/* Bit 1 : Configure write permission for flash region n */ +#define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ +#define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define SPU_FLASHREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to region n */ +#define SPU_FLASHREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to region n */ + +/* Bit 0 : Configure instruction fetch permissions from flash region n */ +#define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */ +#define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ +#define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from flash region n */ +#define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from flash region n */ + +/* Register: SPU_RAMREGION_PERM */ +/* Description: Description cluster: Access permissions for RAM region n */ + +/* Bit 8 : */ +#define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ +#define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ +#define SPU_RAMREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ + +/* Bit 4 : Security attribute for RAM region n */ +#define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ +#define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ +#define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL) /*!< RAM region n security attribute is non-secure */ +#define SPU_RAMREGION_PERM_SECATTR_Secure (1UL) /*!< RAM region n security attribute is secure */ + +/* Bit 2 : Configure read permissions for RAM region n */ +#define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */ +#define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */ +#define SPU_RAMREGION_PERM_READ_Disable (0UL) /*!< Block read operation from RAM region n */ +#define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */ + +/* Bit 1 : Configure write permission for RAM region n */ +#define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ +#define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define SPU_RAMREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to RAM region n */ +#define SPU_RAMREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to RAM region n */ + +/* Bit 0 : Configure instruction fetch permissions from RAM region n */ +#define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */ +#define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ +#define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from RAM region n */ +#define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from RAM region n */ + +/* Register: SPU_PERIPHID_PERM */ +/* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */ + +/* Bit 31 : Indicate if a peripheral is present with ID n */ +#define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */ +#define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ +#define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL) /*!< Peripheral is not present */ +#define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL) /*!< Peripheral is present */ + +/* Bit 8 : */ +#define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ +#define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ +#define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ +#define SPU_PERIPHID_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ + +/* Bit 5 : Security attribution for the DMA transfer */ +#define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */ +#define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */ +#define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */ +#define SPU_PERIPHID_PERM_DMASEC_Secure (1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */ + +/* Bit 4 : Peripheral security mapping */ +#define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ +#define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ +#define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */ +#define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral address space */ + +/* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */ +#define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */ +#define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */ +#define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */ +#define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */ +#define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */ + +/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL) /*!< This peripheral is always accessible as a secure peripheral */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */ + + +/* Peripheral: TAD */ +/* Description: Trace and debug control */ + +/* Register: TAD_TASKS_CLOCKSTART */ +/* Description: Start all trace and debug clocks. */ + +/* Bit 0 : Start all trace and debug clocks. */ +#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */ +#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */ +#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: TAD_TASKS_CLOCKSTOP */ +/* Description: Stop all trace and debug clocks. */ + +/* Bit 0 : Stop all trace and debug clocks. */ +#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */ +#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */ +#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TAD_ENABLE */ +/* Description: Enable debug domain and aquire selected GPIOs */ + +/* Bit 0 : */ +#define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TAD_ENABLE_ENABLE_DISABLED (0UL) /*!< Disable debug domain and release selected GPIOs */ +#define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */ + +/* Register: TAD_PSEL_TRACECLK */ +/* Description: Pin configuration for TRACECLK */ + +/* Bit 31 : Connection */ +#define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL) /*!< Connect */ +#define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACECLK_PIN_Traceclk (21UL) /*!< TRACECLK pin */ + +/* Register: TAD_PSEL_TRACEDATA0 */ +/* Description: Pin configuration for TRACEDATA[0] */ + +/* Bit 31 : Connection */ +#define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL) /*!< Connect */ +#define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (22UL) /*!< TRACEDATA0 pin */ + +/* Register: TAD_PSEL_TRACEDATA1 */ +/* Description: Pin configuration for TRACEDATA[1] */ + +/* Bit 31 : Connection */ +#define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL) /*!< Connect */ +#define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (23UL) /*!< TRACEDATA1 pin */ + +/* Register: TAD_PSEL_TRACEDATA2 */ +/* Description: Pin configuration for TRACEDATA[2] */ + +/* Bit 31 : Connection */ +#define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL) /*!< Connect */ +#define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (24UL) /*!< TRACEDATA2 pin */ + +/* Register: TAD_PSEL_TRACEDATA3 */ +/* Description: Pin configuration for TRACEDATA[3] */ + +/* Bit 31 : Connection */ +#define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL) /*!< Connect */ +#define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (25UL) /*!< TRACEDATA3 pin */ + +/* Register: TAD_TRACEPORTSPEED */ +/* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */ + +/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< Trace Port clock is: 32MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< Trace Port clock is: 16MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< Trace Port clock is: 8MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< Trace Port clock is: 4MHz */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_TASKS_START */ +/* Description: Start Timer */ + +/* Bit 0 : Start Timer */ +#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_STOP */ +/* Description: Stop Timer */ + +/* Bit 0 : Stop Timer */ +#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_COUNT */ +/* Description: Increment Timer (Counter mode only) */ + +/* Bit 0 : Increment Timer (Counter mode only) */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_CLEAR */ +/* Description: Clear time */ + +/* Bit 0 : Clear time */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_SHUTDOWN */ +/* Description: Deprecated register - Shut down timer */ + +/* Bit 0 : Deprecated field - Shut down timer */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_CAPTURE */ +/* Description: Description collection: Capture Timer value to CC[n] register */ + +/* Bit 0 : Capture Timer value to CC[n] register */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_SUBSCRIBE_START */ +/* Description: Subscribe configuration for task START */ + +/* Bit 31 : */ +#define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ +#define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ +#define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task START will subscribe to */ +#define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TIMER_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TIMER_SUBSCRIBE_COUNT */ +/* Description: Subscribe configuration for task COUNT */ + +/* Bit 31 : */ +#define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */ +#define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */ +#define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task COUNT will subscribe to */ +#define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TIMER_SUBSCRIBE_CLEAR */ +/* Description: Subscribe configuration for task CLEAR */ + +/* Bit 31 : */ +#define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ +#define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ +#define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ +#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TIMER_SUBSCRIBE_SHUTDOWN */ +/* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */ + +/* Bit 31 : */ +#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */ +#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */ +#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */ +#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TIMER_SUBSCRIBE_CAPTURE */ +/* Description: Description collection: Subscribe configuration for task CAPTURE[n] */ + +/* Bit 31 : */ +#define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ +#define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ +#define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ +#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TIMER_EVENTS_COMPARE */ +/* Description: Description collection: Compare event on CC[n] match */ + +/* Bit 0 : Compare event on CC[n] match */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ + +/* Register: TIMER_PUBLISH_COMPARE */ +/* Description: Description collection: Publish configuration for event COMPARE[n] */ + +/* Bit 31 : */ +#define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ +#define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ +#define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ +#define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ +#define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_ONESHOTEN */ +/* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */ + +/* Bit 0 : Enable one-shot operation */ +#define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */ +#define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */ +#define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */ +#define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */ + +/* Register: TIMER_CC */ +/* Description: Description collection: Capture/Compare register n */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : Start TWI receive sequence */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : Start TWI transmit sequence */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_STOP */ +/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + +/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_SUBSCRIBE_STARTRX */ +/* Description: Subscribe configuration for task STARTRX */ + +/* Bit 31 : */ +#define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ +#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_SUBSCRIBE_STARTTX */ +/* Description: Subscribe configuration for task STARTTX */ + +/* Bit 31 : */ +#define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ +#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_SUBSCRIBE_SUSPEND */ +/* Description: Subscribe configuration for task SUSPEND */ + +/* Bit 31 : */ +#define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ +#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_SUBSCRIBE_RESUME */ +/* Description: Subscribe configuration for task RESUME */ + +/* Bit 31 : */ +#define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ +#define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_SUSPENDED */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ + +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : Receive sequence started */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : Transmit sequence started */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_LASTRX */ +/* Description: Byte boundary, starting to receive the last byte */ + +/* Bit 0 : Byte boundary, starting to receive the last byte */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_LASTTX */ +/* Description: Byte boundary, starting to transmit the last byte */ + +/* Bit 0 : Byte boundary, starting to transmit the last byte */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_PUBLISH_STOPPED */ +/* Description: Publish configuration for event STOPPED */ + +/* Bit 31 : */ +#define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ +#define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_PUBLISH_ERROR */ +/* Description: Publish configuration for event ERROR */ + +/* Bit 31 : */ +#define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ERROR will publish to */ +#define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_PUBLISH_SUSPENDED */ +/* Description: Publish configuration for event SUSPENDED */ + +/* Bit 31 : */ +#define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */ +#define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_PUBLISH_RXSTARTED */ +/* Description: Publish configuration for event RXSTARTED */ + +/* Bit 31 : */ +#define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ +#define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_PUBLISH_TXSTARTED */ +/* Description: Publish configuration for event TXSTARTED */ + +/* Bit 31 : */ +#define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ +#define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_PUBLISH_LASTRX */ +/* Description: Publish configuration for event LASTRX */ + +/* Bit 31 : */ +#define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event LASTRX will publish to */ +#define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_PUBLISH_LASTTX */ +/* Description: Publish configuration for event LASTTX */ + +/* Bit 31 : */ +#define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event LASTTX will publish to */ +#define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 12 : Shortcut between event LASTRX and task STOP */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between event LASTTX and task STOP */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for event LASTTX */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for event LASTRX */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 12..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 12..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : Stop TWI transaction */ +#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_PREPARERX */ +/* Description: Prepare the TWI slave to respond to a write command */ + +/* Bit 0 : Prepare the TWI slave to respond to a write command */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_PREPARETX */ +/* Description: Prepare the TWI slave to respond to a read command */ + +/* Bit 0 : Prepare the TWI slave to respond to a read command */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_SUBSCRIBE_STOP */ +/* Description: Subscribe configuration for task STOP */ + +/* Bit 31 : */ +#define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ +#define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_SUBSCRIBE_SUSPEND */ +/* Description: Subscribe configuration for task SUSPEND */ + +/* Bit 31 : */ +#define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ +#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_SUBSCRIBE_RESUME */ +/* Description: Subscribe configuration for task RESUME */ + +/* Bit 31 : */ +#define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ +#define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_SUBSCRIBE_PREPARERX */ +/* Description: Subscribe configuration for task PREPARERX */ + +/* Bit 31 : */ +#define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */ +#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_SUBSCRIBE_PREPARETX */ +/* Description: Subscribe configuration for task PREPARETX */ + +/* Bit 31 : */ +#define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */ +#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : Receive sequence started */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : Transmit sequence started */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_WRITE */ +/* Description: Write command received */ + +/* Bit 0 : Write command received */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_READ */ +/* Description: Read command received */ + +/* Bit 0 : Read command received */ +#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_PUBLISH_STOPPED */ +/* Description: Publish configuration for event STOPPED */ + +/* Bit 31 : */ +#define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ +#define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_PUBLISH_ERROR */ +/* Description: Publish configuration for event ERROR */ + +/* Bit 31 : */ +#define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ERROR will publish to */ +#define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_PUBLISH_RXSTARTED */ +/* Description: Publish configuration for event RXSTARTED */ + +/* Bit 31 : */ +#define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ +#define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_PUBLISH_TXSTARTED */ +/* Description: Publish configuration for event TXSTARTED */ + +/* Bit 31 : */ +#define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ +#define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_PUBLISH_WRITE */ +/* Description: Publish configuration for event WRITE */ + +/* Bit 31 : */ +#define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event WRITE will publish to */ +#define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_PUBLISH_READ */ +/* Description: Publish configuration for event READ */ + +/* Bit 31 : */ +#define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */ +#define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */ +#define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event READ will publish to */ +#define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 14 : Shortcut between event READ and task SUSPEND */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for event READ */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for event WRITE */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to enable interrupt for event READ */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for event WRITE */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to disable interrupt for event READ */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for event WRITE */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 12..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 12..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 12..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 12..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection: TWI slave address n */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA 0 */ + +/* Register: UARTE_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : Start UART receiver */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : Stop UART receiver */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : Start UART transmitter */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : Stop UART transmitter */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_FLUSHRX */ +/* Description: Flush RX FIFO into RX buffer */ + +/* Bit 0 : Flush RX FIFO into RX buffer */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_SUBSCRIBE_STARTRX */ +/* Description: Subscribe configuration for task STARTRX */ + +/* Bit 31 : */ +#define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ +#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_SUBSCRIBE_STOPRX */ +/* Description: Subscribe configuration for task STOPRX */ + +/* Bit 31 : */ +#define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */ +#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_SUBSCRIBE_STARTTX */ +/* Description: Subscribe configuration for task STARTTX */ + +/* Bit 31 : */ +#define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ +#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_SUBSCRIBE_STOPTX */ +/* Description: Subscribe configuration for task STOPTX */ + +/* Bit 31 : */ +#define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */ +#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_SUBSCRIBE_FLUSHRX */ +/* Description: Subscribe configuration for task FLUSHRX */ + +/* Bit 31 : */ +#define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */ +#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : CTS is activated (set low). Clear To Send. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXDRDY */ +/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ + +/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ENDRX */ +/* Description: Receive buffer is filled up */ + +/* Bit 0 : Receive buffer is filled up */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : Data sent from TXD */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ENDTX */ +/* Description: Last TX byte transmitted */ + +/* Bit 0 : Last TX byte transmitted */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : Error detected */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : Receiver timeout */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXSTARTED */ +/* Description: UART receiver has started */ + +/* Bit 0 : UART receiver has started */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXSTARTED */ +/* Description: UART transmitter has started */ + +/* Bit 0 : UART transmitter has started */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXSTOPPED */ +/* Description: Transmitter stopped */ + +/* Bit 0 : Transmitter stopped */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_PUBLISH_CTS */ +/* Description: Publish configuration for event CTS */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event CTS will publish to */ +#define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_NCTS */ +/* Description: Publish configuration for event NCTS */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event NCTS will publish to */ +#define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_RXDRDY */ +/* Description: Publish configuration for event RXDRDY */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RXDRDY will publish to */ +#define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_ENDRX */ +/* Description: Publish configuration for event ENDRX */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ENDRX will publish to */ +#define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_TXDRDY */ +/* Description: Publish configuration for event TXDRDY */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TXDRDY will publish to */ +#define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_ENDTX */ +/* Description: Publish configuration for event ENDTX */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ENDTX will publish to */ +#define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_ERROR */ +/* Description: Publish configuration for event ERROR */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event ERROR will publish to */ +#define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_RXTO */ +/* Description: Publish configuration for event RXTO */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RXTO will publish to */ +#define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_RXSTARTED */ +/* Description: Publish configuration for event RXSTARTED */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ +#define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_TXSTARTED */ +/* Description: Publish configuration for event TXSTARTED */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ +#define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_PUBLISH_TXSTOPPED */ +/* Description: Publish configuration for event TXSTOPPED */ + +/* Bit 31 : */ +#define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ +#define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ +#define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */ +#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event RXTO */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event ENDTX */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event TXDRDY */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event ENDRX */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event RXDRDY */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event NCTS */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event CTS */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event CTS */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event CTS */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source This register is read/write one to clear. */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 12..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 12..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 12..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 12..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User information configuration registers User information configuration registers */ + +/* Register: UICR_APPROTECT */ +/* Description: Access port protection */ + +/* Bits 31..0 : Blocks debugger read/write access to all CPU registers and + memory mapped addresses */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ +#define UICR_APPROTECT_PALL_HwUnprotected (0x50FA50FAUL) /*!< HwUnprotected */ + +/* Register: UICR_XOSC32M */ +/* Description: Oscillator control */ + +/* Bits 5..0 : Pierce current DAC control signals */ +#define UICR_XOSC32M_CTRL_Pos (0UL) /*!< Position of CTRL field. */ +#define UICR_XOSC32M_CTRL_Msk (0x3FUL << UICR_XOSC32M_CTRL_Pos) /*!< Bit mask of CTRL field. */ + +/* Register: UICR_HFXOSRC */ +/* Description: HFXO clock source selection */ + +/* Bit 0 : HFXO clock source selection */ +#define UICR_HFXOSRC_HFXOSRC_Pos (0UL) /*!< Position of HFXOSRC field. */ +#define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos) /*!< Bit mask of HFXOSRC field. */ +#define UICR_HFXOSRC_HFXOSRC_TCXO (0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */ +#define UICR_HFXOSRC_HFXOSRC_XTAL (1UL) /*!< 32 MHz crystal oscillator */ + +/* Register: UICR_HFXOCNT */ +/* Description: HFXO startup counter */ + +/* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */ +#define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */ +#define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */ +#define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */ +#define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL) /*!< Max debounce time = (255*64 us + 0.5 us) */ + +/* Register: UICR_APPNVMCPOFGUARD */ +/* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . */ + +/* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */ + +/* Register: UICR_PMICCONF */ +/* Description: Polarity of PMIC polarity configuration signals. */ + +/* Bit 0 : Polarity of PMIC_FPWM signal. */ +#define UICR_PMICCONF_PMICFPWMPOL_Pos (0UL) /*!< Position of PMICFPWMPOL field. */ +#define UICR_PMICCONF_PMICFPWMPOL_Msk (0x1UL << UICR_PMICCONF_PMICFPWMPOL_Pos) /*!< Bit mask of PMICFPWMPOL field. */ +#define UICR_PMICCONF_PMICFPWMPOL_ActiveLow (0UL) /*!< PMIC_FPWM output signal is active-low */ +#define UICR_PMICCONF_PMICFPWMPOL_ActiveHigh (1UL) /*!< PMIC_FPWM output signal is active-high */ + +/* Register: UICR_SECUREAPPROTECT */ +/* Description: Secure access port protection */ + +/* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure + memory mapped addresses */ +#define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ +#define UICR_SECUREAPPROTECT_PALL_HwUnprotected (0x50FA50FAUL) /*!< HwUnprotected */ + +/* Register: UICR_ERASEPROTECT */ +/* Description: Erase protection */ + +/* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality */ +#define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ +#define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */ + +/* Register: UICR_OTP */ +/* Description: Description collection: One time programmable memory */ + +/* Bits 31..16 : Upper half word */ +#define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */ +#define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */ + +/* Bits 15..0 : Lower half word */ +#define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */ +#define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */ + +/* Register: UICR_KEYSLOT_CONFIG_DEST */ +/* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) + will be pushed by KMU. Note that this address must match that of a peripherals + APB mapped write-only key registers, else the KMU can push this key value into + an address range which the CPU can potentially read. */ + +/* Bits 31..0 : Secure APB destination address */ +#define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */ +#define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */ + +/* Register: UICR_KEYSLOT_CONFIG_PERM */ +/* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */ + +/* Bit 16 : Revocation state for the key slot */ +#define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */ +#define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL) /*!< Key value registers can no longer be read or pushed */ +#define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */ + +/* Bit 2 : Push permission for key slot */ +#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */ +#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */ +#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */ +#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */ + +/* Bit 1 : Read permission for key slot */ +#define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */ +#define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */ +#define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */ +#define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */ + +/* Bit 0 : Write permission for key slot */ +#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */ +#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL) /*!< Disable write to the key value registers */ +#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */ + +/* Register: UICR_KEYSLOT_KEY_VALUE */ +/* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */ + +/* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */ +#define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: VMC */ +/* Description: Volatile Memory controller 0 */ + +/* Register: VMC_RAM_POWER */ +/* Description: Description cluster: RAMn power control register */ + +/* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define VMC_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */ +#define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */ + +/* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define VMC_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */ +#define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */ + +/* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define VMC_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define VMC_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define VMC_RAM_POWER_S3POWER_Off (0UL) /*!< Off */ +#define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */ + +/* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define VMC_RAM_POWER_S2POWER_Off (0UL) /*!< Off */ +#define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define VMC_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define VMC_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: VMC_RAM_POWERSET */ +/* Description: Description cluster: RAMn power control set register */ + +/* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */ + +/* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */ + +/* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */ + +/* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: VMC_RAM_POWERCLR */ +/* Description: Description cluster: RAMn power control clear register */ + +/* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */ + +/* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */ + +/* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ +#define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */ + +/* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ +#define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer 0 */ + +/* Register: WDT_TASKS_START */ +/* Description: Start the watchdog */ + +/* Bit 0 : Start the watchdog */ +#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: WDT_SUBSCRIBE_START */ +/* Description: Subscribe configuration for task START */ + +/* Bit 31 : */ +#define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ +#define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ +#define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ +#define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ + +/* Bits 7..0 : DPPI channel that task START will subscribe to */ +#define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: WDT_EVENTS_TIMEOUT */ +/* Description: Watchdog timeout */ + +/* Bit 0 : Watchdog timeout */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ + +/* Register: WDT_PUBLISH_TIMEOUT */ +/* Description: Publish configuration for event TIMEOUT */ + +/* Bit 31 : */ +#define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ +#define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ +#define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */ +#define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */ +#define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */ +#define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */ +#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection: Reload request n */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/mdk/nrf9120_peripherals.h b/mdk/nrf9120_peripherals.h new file mode 100644 index 000000000..c343842b3 --- /dev/null +++ b/mdk/nrf9120_peripherals.h @@ -0,0 +1,232 @@ +/* + +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF9120_PERIPHERALS_H +#define _NRF9120_PERIPHERALS_H + +/* UICR */ +#define UICR_KEYSLOT_COUNT 128 + +/* Clock Peripheral */ +#define CLOCK_PRESENT +#define CLOCK_COUNT 1 + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +/* Non-Volatile Memory Controller */ +#define NVMC_PRESENT +#define NVMC_COUNT 1 + +#define NVMC_FEATURE_CACHE_PRESENT + +/* Memory Protection Unit */ +#define MPU_REGION_NUM 16 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL + +/* Distributed Peripheral to Peripheral Interconnect */ +#define DPPIC_PRESENT +#define DPPIC_COUNT 1 + +#define DPPIC_CH_NUM 16 +#define DPPIC_GROUP_NUM 6 + +/* Event Generator Unit */ +#define EGU_PRESENT +#define EGU_COUNT 6 + +#define EGU0_CH_NUM 16 +#define EGU1_CH_NUM 16 +#define EGU2_CH_NUM 16 +#define EGU3_CH_NUM 16 +#define EGU4_CH_NUM 16 +#define EGU5_CH_NUM 16 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 32 +#define TIMER2_MAX_SIZE 32 + + +#define TIMER0_CC_NUM 6 +#define TIMER1_CC_NUM 6 +#define TIMER2_CC_NUM 6 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 4 +#define RTC1_CC_NUM 4 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Serial Peripheral Interface Master with DMA */ +#define SPIM_PRESENT +#define SPIM_COUNT 4 + +#define SPIM0_MAX_DATARATE 8 +#define SPIM1_MAX_DATARATE 8 +#define SPIM2_MAX_DATARATE 8 +#define SPIM3_MAX_DATARATE 8 + +#define SPIM0_EASYDMA_MAXCNT_SIZE 13 +#define SPIM1_EASYDMA_MAXCNT_SIZE 13 +#define SPIM2_EASYDMA_MAXCNT_SIZE 13 +#define SPIM3_EASYDMA_MAXCNT_SIZE 13 + +/* Serial Peripheral Interface Slave with DMA*/ +#define SPIS_PRESENT +#define SPIS_COUNT 4 + +#define SPIS0_EASYDMA_MAXCNT_SIZE 13 +#define SPIS1_EASYDMA_MAXCNT_SIZE 13 +#define SPIS2_EASYDMA_MAXCNT_SIZE 13 +#define SPIS3_EASYDMA_MAXCNT_SIZE 13 + +/* Two Wire Interface Master with DMA */ +#define TWIM_PRESENT +#define TWIM_COUNT 4 + +#define TWIM0_EASYDMA_MAXCNT_SIZE 13 +#define TWIM1_EASYDMA_MAXCNT_SIZE 13 +#define TWIM2_EASYDMA_MAXCNT_SIZE 13 +#define TWIM3_EASYDMA_MAXCNT_SIZE 13 + +/* Two Wire Interface Slave with DMA */ +#define TWIS_PRESENT +#define TWIS_COUNT 4 + +#define TWIS0_EASYDMA_MAXCNT_SIZE 13 +#define TWIS1_EASYDMA_MAXCNT_SIZE 13 +#define TWIS2_EASYDMA_MAXCNT_SIZE 13 +#define TWIS3_EASYDMA_MAXCNT_SIZE 13 + +/* Universal Asynchronous Receiver-Transmitter with DMA */ +#define UARTE_PRESENT +#define UARTE_COUNT 4 + +#define UARTE0_EASYDMA_MAXCNT_SIZE 13 +#define UARTE1_EASYDMA_MAXCNT_SIZE 13 +#define UARTE2_EASYDMA_MAXCNT_SIZE 13 +#define UARTE3_EASYDMA_MAXCNT_SIZE 13 + +/* Successive Approximation Analog to Digital Converter */ +#define SAADC_PRESENT +#define SAADC_COUNT 1 + +#define SAADC_CH_NUM 8 +#define SAADC_EASYDMA_MAXCNT_SIZE 15 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 2 + +#define GPIOTE_CH_NUM 8 + +#define GPIOTE_FEATURE_SET_PRESENT +#define GPIOTE_FEATURE_CLR_PRESENT + +/* Pulse Width Modulator */ +#define PWM_PRESENT +#define PWM_COUNT 4 + +#define PWM_CH_NUM 4 + +#define PWM_EASYDMA_MAXCNT_SIZE 15 + +/* Pulse Density Modulator */ +#define PDM_PRESENT +#define PDM_COUNT 1 + +#define PDM_EASYDMA_MAXCNT_SIZE 15 + +/* Inter-IC Sound Interface */ +#define I2S_PRESENT +#define I2S_COUNT 1 + +#define I2S_EASYDMA_MAXCNT_SIZE 14 + +/* Inter Processor Communication */ +#define IPC_PRESENT +#define IPC_COUNT 1 + +#define IPC_CH_NUM 8 +#define IPC_CONF_NUM 8 +#define IPC_GPMEM_NUM 4 + +/* FPU */ +#define FPU_PRESENT +#define FPU_COUNT 1 + +/* SPU */ +#define SPU_PRESENT +#define SPU_COUNT 1 + +#define SPU_RAMREGION_SIZE 0x2000ul + +/* CRYPTOCELL */ +#define CRYPTOCELL_PRESENT +#define CRYPTOCELL_COUNT 1 + +/* KMU */ +#define KMU_PRESENT +#define KMU_COUNT 1 + +#define KMU_KEYSLOT_PRESENT + +/* MAGPIO */ +#define MAGPIO_PRESENT +#define MAGPIO_COUNT 1 +#define MAGPIO_PIN_NUM 3 + +/* REGULATORS */ +#define REGULATORS_PRESENT +#define REGULATORS_COUNT 1 + + +#endif // _NRF9120_PERIPHERALS_H diff --git a/mdk/nrf9120_vectors.h b/mdk/nrf9120_vectors.h new file mode 100644 index 000000000..145ba42f0 --- /dev/null +++ b/mdk/nrf9120_vectors.h @@ -0,0 +1,406 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SecureFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void SPU_IRQHandler (void); + __HANDLER("Default_Handler") void CLOCK_POWER_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE0_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void EGU2_IRQHandler (void); + __HANDLER("Default_Handler") void EGU3_IRQHandler (void); + __HANDLER("Default_Handler") void EGU4_IRQHandler (void); + __HANDLER("Default_Handler") void EGU5_IRQHandler (void); + __HANDLER("Default_Handler") void PWM0_IRQHandler (void); + __HANDLER("Default_Handler") void PWM1_IRQHandler (void); + __HANDLER("Default_Handler") void PWM2_IRQHandler (void); + __HANDLER("Default_Handler") void PWM3_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void I2S_IRQHandler (void); + __HANDLER("Default_Handler") void IPC_IRQHandler (void); + __HANDLER("Default_Handler") void FPU_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE1_IRQHandler (void); + __HANDLER("Default_Handler") void KMU_IRQHandler (void); + __HANDLER("Default_Handler") void CRYPTOCELL_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + 0, + 0, + 0, + SPU_IRQHandler, + 0, + CLOCK_POWER_IRQHandler, + 0, + 0, + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler, + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler, + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler, + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler, + 0, + GPIOTE0_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + 0, + 0, + RTC0_IRQHandler, + RTC1_IRQHandler, + 0, + 0, + WDT_IRQHandler, + 0, + 0, + EGU0_IRQHandler, + EGU1_IRQHandler, + EGU2_IRQHandler, + EGU3_IRQHandler, + EGU4_IRQHandler, + EGU5_IRQHandler, + PWM0_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + PWM3_IRQHandler, + 0, + PDM_IRQHandler, + 0, + I2S_IRQHandler, + 0, + IPC_IRQHandler, + 0, + FPU_IRQHandler, + 0, + 0, + 0, + 0, + GPIOTE1_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + KMU_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + CRYPTOCELL_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf9120_xxaa.ld b/mdk/nrf9120_xxaa.ld new file mode 100644 index 000000000..beaba29bc --- /dev/null +++ b/mdk/nrf9120_xxaa.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x3E000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf9120_xxaa.sct b/mdk/nrf9120_xxaa.sct new file mode 100644 index 000000000..d165a8a05 --- /dev/null +++ b/mdk/nrf9120_xxaa.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00100000 +{ + FLASH 0x00000000 0x00100000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x0003E000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf9120_xxaa_memory.h b/mdk/nrf9120_xxaa_memory.h new file mode 100644 index 000000000..f8542eaa0 --- /dev/null +++ b/mdk/nrf9120_xxaa_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 15872 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 15872 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00100000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x00FF0000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x00FF8000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x0003E000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index d37082a6d..0670ad895 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. October 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:10 + * @date 04. April 2023 + * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:56 * from File 'nrf9160.svd', - * last modified on Wednesday, 19.10.2022 09:13:55 + * last modified on Tuesday, 04.04.2023 09:57:14 */ @@ -180,7 +180,10 @@ typedef struct { typedef struct { __IM uint32_t RESERVED; __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ - __IM uint32_t RESERVED1[3]; + __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production + configuration */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ diff --git a/mdk/nrf9160.svd b/mdk/nrf9160.svd index faea2831e..dd96297d1 100644 --- a/mdk/nrf9160.svd +++ b/mdk/nrf9160.svd @@ -8,7 +8,7 @@ 1 nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -162,6 +162,92 @@ POSSIBILITY OF SUCH DAMAGE. + + PART + Part code + 0x00C + read-only + 0xFFFFFFFF + + + PART + Part code + 0 + 31 + + + N9160 + nRF9160 + 0x9160 + + + N9120 + nRF9120 + 0x9120 + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x010 + read-only + 0x0FFFFFFF + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + AAA0 + AAA0 + 0x41414130 + + + AAB0 + AAB0 + 0x41414230 + + + AAC0 + AAC0 + 0x41414330 + + + + + + + PACKAGE + Package option + 0x014 + read-only + 0x00002000 + + + PACKAGE + Package option + 0 + 31 + + + CF + CFxx - 236 ball wlCSP + 0x2002 + + + + + RAM RAM variant @@ -223,6 +309,13 @@ POSSIBILITY OF SUCH DAMAGE. Code memory page size 0 31 + + + K4096 + 4 kByte + 0x1000 + + @@ -235,9 +328,16 @@ POSSIBILITY OF SUCH DAMAGE. CODESIZE - Code memory size in number of pages + Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE 0 31 + + + P256 + 256 pages + 256 + + diff --git a/mdk/nrf9160_bitfields.h b/mdk/nrf9160_bitfields.h index 5dbd7f711..22abc2152 100644 --- a/mdk/nrf9160_bitfields.h +++ b/mdk/nrf9160_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -1315,6 +1315,34 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N9120 (0x9120UL) /*!< nRF9120 */ +#define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part Variant, Hardware version and Production configuration */ + +/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ +#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_CF (0x2002UL) /*!< CFxx - 236 ball wlCSP */ + /* Register: FICR_INFO_RAM */ /* Description: RAM variant */ @@ -1338,13 +1366,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Code memory page size */ #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ +#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL) /*!< 4 kByte */ /* Register: FICR_INFO_CODESIZE */ /* Description: Code memory size */ -/* Bits 31..0 : Code memory size in number of pages */ +/* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */ #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ +#define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL) /*!< 256 pages */ /* Register: FICR_INFO_DEVICETYPE */ /* Description: Device type */ diff --git a/mdk/nrf9160_name_change.h b/mdk/nrf9160_name_change.h index db74658b3..2c24f1bac 100644 --- a/mdk/nrf9160_name_change.h +++ b/mdk/nrf9160_name_change.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -35,45 +35,6 @@ POSSIBILITY OF SUCH DAMAGE. #ifndef NRF9160_NAME_CHANGE_H #define NRF9160_NAME_CHANGE_H -/*lint ++flb "Enter library region */ - -/* This file is given to prevent your SW from not compiling with the updates made to nrf9160.h and - * nrf9160_bitfields.h. The macros defined in this file were available previously. Do not use these - * macros on purpose. Use the ones defined in nrf9160.h and nrf9160_bitfields.h instead. - */ - -/* SAADC enums */ -/* Changes to enum names in SAADC */ -#define SAADC_CH_PSELP_PSELP_VDD SAADC_CH_PSELP_PSELP_VDDGPIO -#define SAADC_CH_PSELP_PSELN_VDD SAADC_CH_PSELP_PSELN_VDDGPIO - -/* CTRLAP PERI Fields */ -#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos -#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk -#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked -#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked - - /* DPPI */ - #define DPPI_PRESENT DPPIC_PRESENT - #define DPPI_COUNT DPPIC_COUNT - #define DPPI_CH_NUM DPPIC_CH_NUM - #define DPPI_GROUP_NUM DPPIC_GROUP_NUM - -/* Serial box enums */ -#define UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 -#define UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 -#define UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 -#define UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 - -/* TAD */ - -#define TAD_CLOCKSTART_START_Pos TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos -#define TAD_CLOCKSTART_START_Msk TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk -#define TAD_CLOCKSTART_START_Start TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger -#define TAD_CLOCKSTOP_STOP_Pos TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos -#define TAD_CLOCKSTOP_STOP_Msk TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk -#define TAD_CLOCKSTOP_STOP_Stop TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger - -/*lint --flb "Leave library region" */ +#include nrf91_name_change.h #endif /* NRF9160_NAME_CHANGE_H */ diff --git a/mdk/nrf9160_peripherals.h b/mdk/nrf9160_peripherals.h index 0a05b3bad..01095e383 100644 --- a/mdk/nrf9160_peripherals.h +++ b/mdk/nrf9160_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -52,6 +52,9 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_FEATURE_CACHE_PRESENT +/* Memory Protection Unit */ +#define MPU_REGION_NUM 16 + /* GPIO */ #define GPIO_PRESENT #define GPIO_COUNT 1 diff --git a/mdk/nrf9160_vectors.h b/mdk/nrf9160_vectors.h new file mode 100644 index 000000000..145ba42f0 --- /dev/null +++ b/mdk/nrf9160_vectors.h @@ -0,0 +1,406 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SecureFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void SPU_IRQHandler (void); + __HANDLER("Default_Handler") void CLOCK_POWER_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE0_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER0_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER2_IRQHandler (void); + __HANDLER("Default_Handler") void RTC0_IRQHandler (void); + __HANDLER("Default_Handler") void RTC1_IRQHandler (void); + __HANDLER("Default_Handler") void WDT_IRQHandler (void); + __HANDLER("Default_Handler") void EGU0_IRQHandler (void); + __HANDLER("Default_Handler") void EGU1_IRQHandler (void); + __HANDLER("Default_Handler") void EGU2_IRQHandler (void); + __HANDLER("Default_Handler") void EGU3_IRQHandler (void); + __HANDLER("Default_Handler") void EGU4_IRQHandler (void); + __HANDLER("Default_Handler") void EGU5_IRQHandler (void); + __HANDLER("Default_Handler") void PWM0_IRQHandler (void); + __HANDLER("Default_Handler") void PWM1_IRQHandler (void); + __HANDLER("Default_Handler") void PWM2_IRQHandler (void); + __HANDLER("Default_Handler") void PWM3_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void I2S_IRQHandler (void); + __HANDLER("Default_Handler") void IPC_IRQHandler (void); + __HANDLER("Default_Handler") void FPU_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE1_IRQHandler (void); + __HANDLER("Default_Handler") void KMU_IRQHandler (void); + __HANDLER("Default_Handler") void CRYPTOCELL_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + 0, + 0, + 0, + SPU_IRQHandler, + 0, + CLOCK_POWER_IRQHandler, + 0, + 0, + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler, + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler, + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler, + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler, + 0, + GPIOTE0_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + 0, + 0, + RTC0_IRQHandler, + RTC1_IRQHandler, + 0, + 0, + WDT_IRQHandler, + 0, + 0, + EGU0_IRQHandler, + EGU1_IRQHandler, + EGU2_IRQHandler, + EGU3_IRQHandler, + EGU4_IRQHandler, + EGU5_IRQHandler, + PWM0_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + PWM3_IRQHandler, + 0, + PDM_IRQHandler, + 0, + I2S_IRQHandler, + 0, + IPC_IRQHandler, + 0, + FPU_IRQHandler, + 0, + 0, + 0, + 0, + GPIOTE1_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + KMU_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + CRYPTOCELL_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf9160_xxaa.sct b/mdk/nrf9160_xxaa.sct new file mode 100644 index 000000000..d165a8a05 --- /dev/null +++ b/mdk/nrf9160_xxaa.sct @@ -0,0 +1,15 @@ +LOAD 0x00000000 0x00100000 +{ + FLASH 0x00000000 0x00100000 + { + + .ANY (+RO) + .ANY (+XO) + } + + RAM 0x20000000 0x0003E000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf9160_xxaa_memory.h b/mdk/nrf9160_xxaa_memory.h new file mode 100644 index 000000000..f8542eaa0 --- /dev/null +++ b/mdk/nrf9160_xxaa_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 15872 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 15872 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x00100000 + +/* Device memory FICR: */ +#define NRF_MEMORY_FICR_BASE 0x00FF0000 +#define NRF_MEMORY_FICR_SIZE 0x00001000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x00FF8000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x0003E000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x40000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x50000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x50840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf91_erratas.h b/mdk/nrf91_erratas.h index 29590ad41..111e2e531 100644 --- a/mdk/nrf91_erratas.h +++ b/mdk/nrf91_erratas.h @@ -3,7 +3,7 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -65,9 +65,12 @@ static bool nrf91_errata_31(void) __UNUSED; static bool nrf91_errata_32(void) __UNUSED; static bool nrf91_errata_33(void) __UNUSED; static bool nrf91_errata_35(void) __UNUSED; +static bool nrf91_errata_36(void) __UNUSED; +static bool nrf91_errata_37(void) __UNUSED; /* ========= Errata 1 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_1_PRESENT 1 #else #define NRF91_ERRATA_1_PRESENT 0 @@ -82,7 +85,8 @@ static bool nrf91_errata_1(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -91,6 +95,21 @@ static bool nrf91_errata_1(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -111,7 +130,8 @@ static bool nrf91_errata_1(void) } /* ========= Errata 2 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_2_PRESENT 1 #else #define NRF91_ERRATA_2_PRESENT 0 @@ -126,7 +146,8 @@ static bool nrf91_errata_2(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -135,6 +156,21 @@ static bool nrf91_errata_2(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -155,7 +191,8 @@ static bool nrf91_errata_2(void) } /* ========= Errata 4 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_4_PRESENT 1 #else #define NRF91_ERRATA_4_PRESENT 0 @@ -170,7 +207,8 @@ static bool nrf91_errata_4(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -179,6 +217,21 @@ static bool nrf91_errata_4(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -199,7 +252,8 @@ static bool nrf91_errata_4(void) } /* ========= Errata 6 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_6_PRESENT 1 #else #define NRF91_ERRATA_6_PRESENT 0 @@ -214,7 +268,8 @@ static bool nrf91_errata_6(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -223,6 +278,21 @@ static bool nrf91_errata_6(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -243,7 +313,8 @@ static bool nrf91_errata_6(void) } /* ========= Errata 7 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_7_PRESENT 1 #else #define NRF91_ERRATA_7_PRESENT 0 @@ -258,7 +329,8 @@ static bool nrf91_errata_7(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -267,6 +339,21 @@ static bool nrf91_errata_7(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -287,7 +374,8 @@ static bool nrf91_errata_7(void) } /* ========= Errata 8 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_8_PRESENT 1 #else #define NRF91_ERRATA_8_PRESENT 0 @@ -302,7 +390,8 @@ static bool nrf91_errata_8(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -311,6 +400,21 @@ static bool nrf91_errata_8(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -331,7 +435,8 @@ static bool nrf91_errata_8(void) } /* ========= Errata 9 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_9_PRESENT 1 #else #define NRF91_ERRATA_9_PRESENT 0 @@ -346,7 +451,8 @@ static bool nrf91_errata_9(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -355,6 +461,21 @@ static bool nrf91_errata_9(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -375,7 +496,8 @@ static bool nrf91_errata_9(void) } /* ========= Errata 10 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_10_PRESENT 1 #else #define NRF91_ERRATA_10_PRESENT 0 @@ -390,7 +512,8 @@ static bool nrf91_errata_10(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -399,6 +522,21 @@ static bool nrf91_errata_10(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -419,7 +557,8 @@ static bool nrf91_errata_10(void) } /* ========= Errata 12 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_12_PRESENT 1 #else #define NRF91_ERRATA_12_PRESENT 0 @@ -434,7 +573,8 @@ static bool nrf91_errata_12(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -443,6 +583,21 @@ static bool nrf91_errata_12(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -463,7 +618,8 @@ static bool nrf91_errata_12(void) } /* ========= Errata 14 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_14_PRESENT 1 #else #define NRF91_ERRATA_14_PRESENT 0 @@ -478,7 +634,8 @@ static bool nrf91_errata_14(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -487,6 +644,21 @@ static bool nrf91_errata_14(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -507,7 +679,8 @@ static bool nrf91_errata_14(void) } /* ========= Errata 15 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_15_PRESENT 1 #else #define NRF91_ERRATA_15_PRESENT 0 @@ -522,7 +695,8 @@ static bool nrf91_errata_15(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -531,6 +705,21 @@ static bool nrf91_errata_15(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -551,7 +740,8 @@ static bool nrf91_errata_15(void) } /* ========= Errata 16 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_16_PRESENT 1 #else #define NRF91_ERRATA_16_PRESENT 0 @@ -566,7 +756,8 @@ static bool nrf91_errata_16(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -575,6 +766,21 @@ static bool nrf91_errata_16(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -595,7 +801,8 @@ static bool nrf91_errata_16(void) } /* ========= Errata 17 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_17_PRESENT 1 #else #define NRF91_ERRATA_17_PRESENT 0 @@ -610,7 +817,8 @@ static bool nrf91_errata_17(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -619,6 +827,21 @@ static bool nrf91_errata_17(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -639,7 +862,8 @@ static bool nrf91_errata_17(void) } /* ========= Errata 20 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_20_PRESENT 1 #else #define NRF91_ERRATA_20_PRESENT 0 @@ -654,7 +878,8 @@ static bool nrf91_errata_20(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -663,6 +888,21 @@ static bool nrf91_errata_20(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -683,7 +923,8 @@ static bool nrf91_errata_20(void) } /* ========= Errata 21 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_21_PRESENT 1 #else #define NRF91_ERRATA_21_PRESENT 0 @@ -698,7 +939,8 @@ static bool nrf91_errata_21(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -707,6 +949,21 @@ static bool nrf91_errata_21(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -727,7 +984,8 @@ static bool nrf91_errata_21(void) } /* ========= Errata 23 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_23_PRESENT 1 #else #define NRF91_ERRATA_23_PRESENT 0 @@ -742,7 +1000,8 @@ static bool nrf91_errata_23(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -751,6 +1010,21 @@ static bool nrf91_errata_23(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -771,7 +1045,8 @@ static bool nrf91_errata_23(void) } /* ========= Errata 24 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_24_PRESENT 1 #else #define NRF91_ERRATA_24_PRESENT 0 @@ -786,7 +1061,8 @@ static bool nrf91_errata_24(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -795,6 +1071,21 @@ static bool nrf91_errata_24(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -815,7 +1106,8 @@ static bool nrf91_errata_24(void) } /* ========= Errata 26 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_26_PRESENT 1 #else #define NRF91_ERRATA_26_PRESENT 0 @@ -830,7 +1122,8 @@ static bool nrf91_errata_26(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -839,6 +1132,21 @@ static bool nrf91_errata_26(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -859,7 +1167,8 @@ static bool nrf91_errata_26(void) } /* ========= Errata 27 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_27_PRESENT 1 #else #define NRF91_ERRATA_27_PRESENT 0 @@ -874,7 +1183,8 @@ static bool nrf91_errata_27(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -883,6 +1193,21 @@ static bool nrf91_errata_27(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -903,7 +1228,8 @@ static bool nrf91_errata_27(void) } /* ========= Errata 28 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_28_PRESENT 1 #else #define NRF91_ERRATA_28_PRESENT 0 @@ -918,7 +1244,8 @@ static bool nrf91_errata_28(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -927,6 +1254,21 @@ static bool nrf91_errata_28(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -947,7 +1289,8 @@ static bool nrf91_errata_28(void) } /* ========= Errata 29 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_29_PRESENT 1 #else #define NRF91_ERRATA_29_PRESENT 0 @@ -962,7 +1305,8 @@ static bool nrf91_errata_29(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -971,6 +1315,21 @@ static bool nrf91_errata_29(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -991,7 +1350,8 @@ static bool nrf91_errata_29(void) } /* ========= Errata 30 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_30_PRESENT 1 #else #define NRF91_ERRATA_30_PRESENT 0 @@ -1006,7 +1366,8 @@ static bool nrf91_errata_30(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -1015,6 +1376,21 @@ static bool nrf91_errata_30(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -1035,7 +1411,8 @@ static bool nrf91_errata_30(void) } /* ========= Errata 31 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_31_PRESENT 1 #else #define NRF91_ERRATA_31_PRESENT 0 @@ -1050,7 +1427,8 @@ static bool nrf91_errata_31(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -1059,6 +1437,21 @@ static bool nrf91_errata_31(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -1079,7 +1472,8 @@ static bool nrf91_errata_31(void) } /* ========= Errata 32 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_32_PRESENT 1 #else #define NRF91_ERRATA_32_PRESENT 0 @@ -1094,7 +1488,8 @@ static bool nrf91_errata_32(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -1103,6 +1498,21 @@ static bool nrf91_errata_32(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -1123,7 +1533,8 @@ static bool nrf91_errata_32(void) } /* ========= Errata 33 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_33_PRESENT 1 #else #define NRF91_ERRATA_33_PRESENT 0 @@ -1138,7 +1549,8 @@ static bool nrf91_errata_33(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -1147,6 +1559,21 @@ static bool nrf91_errata_33(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -1167,7 +1594,8 @@ static bool nrf91_errata_33(void) } /* ========= Errata 35 ========= */ -#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) \ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #define NRF91_ERRATA_35_PRESENT 1 #else #define NRF91_ERRATA_35_PRESENT 0 @@ -1182,7 +1610,8 @@ static bool nrf91_errata_35(void) #ifndef NRF91_SERIES return false; #else - #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120)\ + || defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) #if defined(NRF_TRUSTZONE_NONSECURE) uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); @@ -1191,6 +1620,21 @@ static bool nrf91_errata_35(void) uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); #endif #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) __DSB(); if (var1 == 0x09) @@ -1210,4 +1654,76 @@ static bool nrf91_errata_35(void) #endif } +/* ========= Errata 36 ========= */ +#if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + #if defined(NRF_APPLICATION) + #define NRF91_ERRATA_36_PRESENT 1 + #else + #define NRF91_ERRATA_36_PRESENT 0 + #endif +#else + #define NRF91_ERRATA_36_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_36_ENABLE_WORKAROUND + #define NRF91_ERRATA_36_ENABLE_WORKAROUND 0 +#endif + +static bool nrf91_errata_36(void) +{ + #if defined (DISABLE_WORKAROUND_36) + return false; + #elif !defined(NRF91_SERIES) + return false; + #else + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #endif + #endif + #if defined (NRF9120_XXAA) || defined (DEVELOP_IN_NRF9120) + #if defined (NRF_APPLICATION) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 37 ========= */ +#define NRF91_ERRATA_37_PRESENT 0 + +#ifndef NRF91_ERRATA_37_ENABLE_WORKAROUND + #define NRF91_ERRATA_37_ENABLE_WORKAROUND NRF91_ERRATA_37_PRESENT +#endif + +static bool nrf91_errata_37(void) +{ + #ifndef NRF91_SERIES + return false; + #else + return false; + #endif +} + #endif /* NRF91_ERRATAS_H */ diff --git a/mdk/nrf91_name_change.h b/mdk/nrf91_name_change.h new file mode 100644 index 000000000..eabe14fda --- /dev/null +++ b/mdk/nrf91_name_change.h @@ -0,0 +1,85 @@ +/* + +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF91_NAME_CHANGE_H +#define NRF91_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf91-series + * headerfiles, like nrf9160.h and nrf9160_bitfields.h. The macros defined in this file were available + * previously. Do not use these macros on purpose. Use the ones defined in the respective nrf91-series + * header files. + */ + +/* SAADC enums */ +/* Changes to enum names in SAADC */ +#define SAADC_CH_PSELP_PSELP_VDD SAADC_CH_PSELP_PSELP_VDDGPIO +#define SAADC_CH_PSELP_PSELN_VDD SAADC_CH_PSELP_PSELN_VDDGPIO + +/* CTRLAP PERI Fields */ +#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos +#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk +#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked +#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked + + /* DPPI */ + #define DPPI_PRESENT DPPIC_PRESENT + #define DPPI_COUNT DPPIC_COUNT + #define DPPI_CH_NUM DPPIC_CH_NUM + #define DPPI_GROUP_NUM DPPIC_GROUP_NUM + + +/* The serial box interrupt ISRs were renamed. Adding old names as macros. */ +#define UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn +#define UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +#define UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn +#define UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +#define UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn +#define UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHanlder SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +#define UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn + +/* TAD */ + +#define TAD_CLOCKSTART_START_Pos TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos +#define TAD_CLOCKSTART_START_Msk TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk +#define TAD_CLOCKSTART_START_Start TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger +#define TAD_CLOCKSTOP_STOP_Pos TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos +#define TAD_CLOCKSTOP_STOP_Msk TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk +#define TAD_CLOCKSTOP_STOP_Stop TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger + +/*lint --flb "Leave library region" */ + +#endif /* NRF91_NAME_CHANGE_H */ diff --git a/mdk/nrf_common.ld b/mdk/nrf_common.ld index f2e0fae11..ce03fa479 100644 --- a/mdk/nrf_common.ld +++ b/mdk/nrf_common.ld @@ -23,19 +23,42 @@ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: + * __init_start + * __init_end + * __text_start + * __CTOR_LIST__ + * __CTOR_END__ + * __DTOR_LIST__ + * __DTOR_END__ * __exidx_start * __exidx_end * __etext + * _etext + * etext + * __data_load_start + * __data_start * __data_start__ * __preinit_array_start * __preinit_array_end + * __data_end + * __data_end__ + * __sdata_start + * __sdata_end + * __fast_start + * __fast_end + * __edata + * _edata + * edata * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end - * __data_end__ * __bss_start__ + * __bss_start * __bss_end__ + * __bss_end + * __end + * _end * __end__ * end * __HeapBase @@ -46,109 +69,340 @@ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") */ ENTRY(Reset_Handler) + SECTIONS { + /* Set the location counter to start of FLASH */ + . = ALIGN(ORIGIN(FLASH), 4); + + __vectors_start = .; + .vectors : { + /* Vector table */ + KEEP(*(.isr_vector)) + KEEP(*(.vectors)) + } > FLASH + __vectors_size = SIZEOF(.vectors); + __vectors_end = __vectors_start + __vectors_size; + ASSERT(__vectors_start == __vectors_end || (__vectors_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .vectors is too large to fit in FLASH memory segment") + + + /* .ctors section (global constructor function pointers) */ + . = ALIGN(4); + .ctors : + { + __ctors_start = .; + __CTOR_LIST__ = .; + KEEP (*crtbegin*.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > FLASH + __ctors_size = SIZEOF(.ctors); + __ctors_end = __ctors_start + __ctors_size; + ASSERT(__ctors_start == __ctors_end || (__ctors_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .ctors is too large to fit in FLASH memory segment") + + + /* .detors section (global destructor function pointers) */ + . = ALIGN(4); + .dtors : + { + __dtors_start = .; + __DTOR_LIST__ = .; + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > FLASH + __dtors_size = SIZEOF(.dtors); + __dtors_end = __dtors_start + __dtors_size; + ASSERT(__dtors_start == __dtors_end || (__dtors_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .dtors is too large to fit in FLASH memory segment") + + + /* .rodata section */ + . = ALIGN(4); + .rodata : { + . = ALIGN(4); + __rodata_start = .; + *(.rodata*) + *(.srodata .srodata.*) + } > FLASH + __rodata_size = SIZEOF(.rodata); + __rodata_end = __rodata_start + __rodata_size; + ASSERT(__rodata_start == __rodata_end || (__rodata_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .rodata is too large to fit in FLASH memory segment") + + + . = ALIGN(4); + __text_start = .; .text : { - KEEP(*(.isr_vector)) + /* Reset handler for C startup file */ + KEEP(*(.startup)) + *(.startup*) + + /* text: executable instructions of a program. */ *(.text*) + /* executable instructions that contribute to the process initialization code */ + . = ALIGN(4); KEEP(*(.init)) - KEEP(*(.fini)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) + /* executable instructions that contribute to the process termination code */ + KEEP(*(.fini)) - *(.rodata*) + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + /* DWARF-based unwinding - exception handling. C++ stuff (disable with no-asynchronous-unwind-tables)*/ + . = ALIGN(4); KEEP(*(.eh_frame*)) - } > FLASH - .gnu.sgstubs : - { - . = ALIGN(32); + /* section contains a pointer to the .eh_frame section which is */ + /* accessible to the runtime support code of a C++ application */ + . = ALIGN(4); + *(.eh_frame_hdr) + + /* hash tables */ + . = ALIGN(4); + *(.hash) + *(.gnu.hash) + + . = ALIGN(4); + *(.gnu_extab* .gnu.linkonce.extab.*) + + . = ALIGN(4); + __exidx_start = .; + *(.gnu_exidx* .gnu.linkonce.exidx.*) + . = ALIGN(4); + __exidx_end = .; } > FLASH + __text_size = SIZEOF(.text); + __text_end = __text_start + __text_size; + ASSERT(__text_start == __text_end || (__text_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .text is too large to fit in FLASH memory segment") - - .ARM.extab : + .copy.table : { - *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__data_load_start) + LONG (__data_start) + LONG ((__data_end - __data_start) / 4) + + LONG (__sdata_load_start) + LONG (__sdata_start) + LONG ((__sdata_end - __sdata_start) / 4) + + LONG (__tdata_load_start) + LONG (__tdata_start) + LONG ((__tdata_end - __tdata_start) / 4) + + LONG (__fast_load_start) + LONG (__fast_start) + LONG ((__fast_end - __fast_start) / 4) + + /* Add aditional regions here as needed. */ + + __copy_table_end__ = .; } > FLASH - - .ARM.exidx : + .zero.table : { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; + . = ALIGN(4); + __zero_table_start__ = .; + + LONG (__bss_start) + LONG ((__bss_end - __bss_start) / 4) + + LONG (__sbss_start) + LONG ((__sbss_end - __sbss_start) / 4) + + LONG (__tbss_start) + LONG ((__tbss_end - __tbss_start) / 4) + + /* Add aditional regions here as needed. */ + + __zero_table_end__ = .; } > FLASH + /* End of text */ . = ALIGN(4); - __etext = .; + __etext = .; PROVIDE(etext = .); PROVIDE(_etext = .); - .data : AT (__etext) - { + + /* Define start of all sections that needs to be loaded on boot */ + . = ALIGN(4); + __all_data_load_start = .; + + /* .data section */ + __data_load_start = .; + .data : AT(__data_load_start){ + . = ALIGN(4); + __data_start = .; __data_start__ = .; *(vtable) - *(.data*) + *(.data* .gnu.linkonce.d.*) . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); + KEEP(*(.jcr*)) + } > RAM + __data_size = SIZEOF(.data); + __data_end = __data_start + __data_size; + __data_end__ = __data_end; + __data_load_end = __data_load_start + __data_size; + ASSERT(__data_load_start == __data_load_end || (__data_load_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .data is too large to fit in FLASH memory segment") + ASSERT(__data_start == __data_end || (__data_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .data is too large to fit in RAM memory segment") + + /* .sdata section */ + . = ALIGN(4); + __sdata_load_start = ALIGN(__data_load_end, 4); + .sdata : AT(__sdata_load_start){ . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); + __sdata_start = .; + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + } > RAM + __sdata_size = SIZEOF(.sdata); + __sdata_end = __sdata_start + __sdata_size; + __sdata_load_end = __sdata_load_start + __sdata_size; + ASSERT(__sdata_load_start == __sdata_load_end || (__sdata_load_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .sdata is too large to fit in FLASH memory segment") + ASSERT(__sdata_start == __sdata_end || (__sdata_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .sdata is too large to fit in RAM memory segment") + /* .tdata section */ + . = ALIGN(4); + __tdata_load_start = ALIGN(__sdata_load_end, 4); + .tdata : AT(__tdata_load_start){ . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); + __tdata_start = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + *(.stdata .stdata.*) + } > RAM + __tdata_size = SIZEOF(.tdata); + __tdata_end = __tdata_start + __tdata_size; + __tdata_load_end = __tdata_load_start + __tdata_size; + ASSERT(__tdata_load_start == __tdata_load_end || (__tdata_load_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .tdata is too large to fit in FLASH memory segment") + ASSERT(__tdata_start == __tdata_end || (__tdata_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .tdata is too large to fit in RAM memory segment") - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; + /* .fast section */ + . = ALIGN(4); + __fast_load_start = ALIGN(__tdata_load_end, 4); + .fast : AT(__fast_load_start){ + . = ALIGN(4); + __fast_start = .; + *(.fast .fast.*) + *(.fastcode .fastcode.*) + *(.fastdata .fastdata.*) + *(.ramcode*) } > RAM + __fast_size = SIZEOF(.fast); + __fast_end = __fast_start + __fast_size; + __fast_load_end = __fast_load_start + __fast_size; + ASSERT(__fast_load_start == __fast_load_end || (__fast_load_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .fast is too large to fit in FLASH memory segment") + ASSERT(__fast_start == __fast_end || (__fast_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .fast is too large to fit in RAM memory segment") + + /* end of data in RAM */ + . = ALIGN(4); + _edata = .; PROVIDE (edata = .); PROVIDE (__edata = .); - .bss : + + /* No-init section. */ + . = ALIGN(4); + __noinit_start = .; PROVIDE(__noinit_start__ = .); + .noinit (NOLOAD): { + *(.noinit .noinit.*) + *(.no_init .no_init.*) + *(.noninit .noninit.*) + *(.non_init .non_init.*) . = ALIGN(4); - __bss_start__ = .; - *(.bss*) + } > RAM + __noinit_size = SIZEOF(.noinit); + __noinit_end = __noinit_start + __noinit_size; + __noinit_end__ = __noinit_end; + ASSERT(__noinit_start == __noinit_end || (__noinit_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .noinit is too large to fit in RAM memory segment") + + + /* .bss section */ + . = ALIGN(4); + __bss_start = .; PROVIDE(__bss_start__ = .); + .bss (NOLOAD): + { + *(.bss* .gnu.linkonce.b.*) + *(.dynbss) *(COMMON) . = ALIGN(4); - __bss_end__ = .; } > RAM - + __bss_size = SIZEOF(.bss); + __bss_end = __bss_start + __bss_size; + __bss_end__ = __bss_end; + ASSERT(__bss_start == __bss_end || (__bss_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .bss is too large to fit in RAM memory segment") + + + /* .sbss section */ + . = ALIGN(4); + __sbss_start = .; + .sbss (NOLOAD): + { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + *(.dynsbss) + . = ALIGN(4); + } > RAM + __sbss_size = SIZEOF(.sbss); + __sbss_end = __sbss_start + __sbss_size; + ASSERT(__sbss_start == __sbss_end || (__sbss_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .sbss is too large to fit in RAM memory segment") + + + /* .tbss section */ + . = ALIGN(4); + __tbss_start = .; + .tbss (NOLOAD): + { + . = ALIGN(4); + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + *(.stbss .stbss.*) + . = ALIGN(4); + } > RAM + __tbss_size = SIZEOF(.tbss); + __tbss_end = __tbss_start + __tbss_size; + ASSERT(__tbss_start == __tbss_end || (__tbss_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .tbss is too large to fit in RAM memory segment") + + . = ALIGN(4); + . = SEGMENT_START("ldata-segment", .); + + . = ALIGN(4); + __heap_start = .; .heap (COPY): { __HeapBase = .; - __end__ = .; + __heap_base = .; + __end = .; PROVIDE(end = .); + PROVIDE(_end = .); + PROVIDE(__end__ = .); KEEP(*(.heap*)) __HeapLimit = .; + __heap_limit = .; } > RAM + __heap_end = .; /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign @@ -160,17 +414,19 @@ SECTIONS /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ + __stack_end = ORIGIN(RAM) + LENGTH(RAM); + __StackTop = ORIGIN(RAM) + LENGTH(RAM); __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - + /* Check if text sections + data exceeds FLASH limit */ - DataInitFlashUsed = __bss_start__ - __data_start__; - CodeFlashUsed = __etext - ORIGIN(FLASH); + DataInitFlashUsed = __bss_start - __data_start; + CodeFlashUsed = _etext - ORIGIN(FLASH); TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - } + diff --git a/mdk/nrf_erratas.h b/mdk/nrf_erratas.h index 47a13ee68..f4c547145 100644 --- a/mdk/nrf_erratas.h +++ b/mdk/nrf_erratas.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/nrf_mem.h b/mdk/nrf_mem.h new file mode 100644 index 000000000..cc17da007 --- /dev/null +++ b/mdk/nrf_mem.h @@ -0,0 +1,121 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_MEM_H_ +#define NRF_MEM_H_ + +#if defined(NRF51422_XXAA) + #include "nrf51422_xxaa_memory.h" +#elif defined(NRF51422_XXAB) + #include "nrf51422_xxab_memory.h" +#elif defined(NRF51422_XXAC) + #include "nrf51422_xxac_memory.h" +#elif defined(NRF51801_XXAB) + #include "nrf51801_xxab_memory.h" +#elif defined(NRF51802_XXAA) + #include "nrf51802_xxaa_memory.h" +#elif defined(NRF51822_XXAA) + #include "nrf51822_xxaa_memory.h" +#elif defined(NRF51822_XXAB) + #include "nrf51822_xxab_memory.h" +#elif defined(NRF51822_XXAC) + #include "nrf51822_xxac_memory.h" +#elif defined(NRF51824_XXAA) + #include "nrf51824_xxaa_memory.h" +#elif defined(NRF52805_XXAA) + #include "nrf52805_xxaa_memory.h" +#elif defined(NRF52810_XXAA) + #include "nrf52810_xxaa_memory.h" +#elif defined(NRF52811_XXAA) + #include "nrf52811_xxaa_memory.h" +#elif defined(NRF52820_XXAA) + #include "nrf52820_xxaa_memory.h" +#elif defined(NRF52832_XXAA) + #include "nrf52832_xxaa_memory.h" +#elif defined(NRF52832_XXAB) + #include "nrf52832_xxab_memory.h" +#elif defined(NRF52833_XXAA) + #include "nrf52833_xxaa_memory.h" +#elif defined(NRF52840_XXAA) + #include "nrf52840_xxaa_memory.h" +#elif defined(NRF5340_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf5340_xxaa_application_memory.h" + #endif + #if defined(NRF_NETWORK) + #include "nrf5340_xxaa_network_memory.h" + #endif +#elif defined(NRF9120_XXAA) + #include "nrf9120_xxaa_memory.h" +#elif defined(NRF9160_XXAA) + #include "nrf9160_xxaa_memory.h" +#else + #error "Device must be defined. See nrf_mem.h." +#endif + + +#ifdef __STARTUP_CONFIG + #include "startup_config.h" + #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT + #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + #endif +#endif + +#ifndef __STACK_SIZE + #if defined(__STARTUP_CONFIG_STACK_SIZE) + #define __STACK_SIZE __STARTUP_CONFIG_STACK_SIZE + #else + #define __STACK_SIZE __DEFAULT_STACK_SIZE + #endif +#endif + +#ifndef __STACK_ALIGNMENT + #if defined(__STARTUP_CONFIG_STACK_ALIGNEMENT) + #define __STACK_ALIGNMENT __STARTUP_CONFIG_STACK_ALIGNEMENT + #else + #define __STACK_ALIGNMENT 3 + #endif +#endif + +#ifndef __HEAP_SIZE + #if defined(__STARTUP_CONFIG_HEAP_SIZE) + #define __HEAP_SIZE __STARTUP_CONFIG_HEAP_SIZE + #else + #define __HEAP_SIZE __DEFAULT_HEAP_SIZE + #endif +#endif + +#ifndef __HEAP_ALIGNMENT + #define __HEAP_ALIGNMENT __STACK_ALIGNMENT +#endif + +#endif \ No newline at end of file diff --git a/mdk/nrf_peripherals.h b/mdk/nrf_peripherals.h index e61df002d..750ab015e 100644 --- a/mdk/nrf_peripherals.h +++ b/mdk/nrf_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -60,11 +60,13 @@ POSSIBILITY OF SUCH DAMAGE. #elif defined (NRF5340_XXAA_NETWORK) #include "nrf5340_network_peripherals.h" +#elif defined(NRF9120_XXAA) + #include "nrf9120_peripherals.h" #elif defined(NRF9160_XXAA) #include "nrf9160_peripherals.h" #else - #error "Device must be defined. See nrf.h." + #error "Device must be defined. See nrf_peripherals.h." #endif /*lint --flb "Leave library region" */ diff --git a/mdk/nrf_vectors.h b/mdk/nrf_vectors.h new file mode 100644 index 000000000..7044f14b5 --- /dev/null +++ b/mdk/nrf_vectors.h @@ -0,0 +1,85 @@ +/* +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_VECTORS_H_ +#define NRF_VECTORS_H_ + +#if defined(NRF51422_XXAA) + #include "nrf51422_vectors.h" +#elif defined(NRF51422_XXAB) + #include "nrf51422_vectors.h" +#elif defined(NRF51422_XXAC) + #include "nrf51422_vectors.h" +#elif defined(NRF51801_XXAB) + #include "nrf51801_vectors.h" +#elif defined(NRF51802_XXAA) + #include "nrf51802_vectors.h" +#elif defined(NRF51822_XXAA) + #include "nrf51822_vectors.h" +#elif defined(NRF51822_XXAB) + #include "nrf51822_vectors.h" +#elif defined(NRF51822_XXAC) + #include "nrf51822_vectors.h" +#elif defined(NRF51824_XXAA) + #include "nrf51824_vectors.h" +#elif defined(NRF52805_XXAA) + #include "nrf52805_vectors.h" +#elif defined(NRF52810_XXAA) + #include "nrf52810_vectors.h" +#elif defined(NRF52811_XXAA) + #include "nrf52811_vectors.h" +#elif defined(NRF52820_XXAA) + #include "nrf52820_vectors.h" +#elif defined(NRF52832_XXAA) + #include "nrf52832_vectors.h" +#elif defined(NRF52832_XXAB) + #include "nrf52832_vectors.h" +#elif defined(NRF52833_XXAA) + #include "nrf52833_vectors.h" +#elif defined(NRF52840_XXAA) + #include "nrf52840_vectors.h" +#elif defined(NRF5340_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf5340_application_vectors.h" + #endif + #if defined(NRF_NETWORK) + #include "nrf5340_network_vectors.h" + #endif +#elif defined(NRF9120_XXAA) + #include "nrf9120_vectors.h" +#elif defined(NRF9160_XXAA) + #include "nrf9160_vectors.h" +#else + #error "Device must be defined. See nrf_vectors.h." +#endif + +#endif diff --git a/mdk/ses_startup_nrf9120.s b/mdk/ses_startup_nrf9120.s new file mode 100644 index 000000000..9dd95ad3e --- /dev/null +++ b/mdk/ses_startup_nrf9120.s @@ -0,0 +1,420 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + ************************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + + +/************************************************************************************ + * Macros * + ************************************************************************************/ + +// Directly place a vector (word) in the vector table +.macro VECTOR Name= + .section .vectors, "ax" + .code 16 + .word \Name +.endm + +// Declare an exception handler with a weak definition +.macro EXC_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +.endm + +// Declare an interrupt handler with a weak definition +.macro ISR_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +#endif +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/************************************************************************************ + * Reset Handler Extensions * + ************************************************************************************/ + + .extern Reset_Handler + .global nRFInitialize + .extern afterInitialize + + .thumb_func +nRFInitialize: + bx lr + + +/************************************************************************************ + * Vector Table * + ************************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + +_vectors: + VECTOR __stack_end__ + VECTOR Reset_Handler + EXC_HANDLER NMI_Handler + EXC_HANDLER HardFault_Handler + EXC_HANDLER MemoryManagement_Handler + EXC_HANDLER BusFault_Handler + EXC_HANDLER UsageFault_Handler + EXC_HANDLER SecureFault_Handler + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + EXC_HANDLER SVC_Handler + EXC_HANDLER DebugMon_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER PendSV_Handler + EXC_HANDLER SysTick_Handler + +/* External Interrupts */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SPU_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CLOCK_POWER_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + ISR_HANDLER SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + ISR_HANDLER SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + ISR_HANDLER SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER GPIOTE0_IRQHandler + ISR_HANDLER SAADC_IRQHandler + ISR_HANDLER TIMER0_IRQHandler + ISR_HANDLER TIMER1_IRQHandler + ISR_HANDLER TIMER2_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER RTC0_IRQHandler + ISR_HANDLER RTC1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER WDT_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER EGU0_IRQHandler + ISR_HANDLER EGU1_IRQHandler + ISR_HANDLER EGU2_IRQHandler + ISR_HANDLER EGU3_IRQHandler + ISR_HANDLER EGU4_IRQHandler + ISR_HANDLER EGU5_IRQHandler + ISR_HANDLER PWM0_IRQHandler + ISR_HANDLER PWM1_IRQHandler + ISR_HANDLER PWM2_IRQHandler + ISR_HANDLER PWM3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER PDM_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPC_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER FPU_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER GPIOTE1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER KMU_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CRYPTOCELL_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .thumb_func + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + 1: b 1b // Endless loop diff --git a/mdk/startup_nrf_common.c b/mdk/startup_nrf_common.c new file mode 100644 index 000000000..246d2aa89 --- /dev/null +++ b/mdk/startup_nrf_common.c @@ -0,0 +1,237 @@ +/* +Copyright (c) 2009-2023 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + */ + +#include + +#include +#include + +/*--------------------------------------------------------------------------- + Stack and heap definitions + *---------------------------------------------------------------------------*/ + +#ifndef NRF_SKIP_STACK_DECLARATION + extern uint8_t __STACK[] __STACK_ATTRIBUTES(__STACK_ALIGNMENT); + uint8_t __STACK[__STACK_SIZE] __STACK_ATTRIBUTES(__STACK_ALIGNMENT); + #define __STACK_BASE ((uint32_t)(__STACK + __STACK_SIZE)) + #define __STACK_LIMIT ((uint32_t)(__STACK)) +#endif + +#if !defined(NRF_SKIP_HEAP_DECLARATION) && __HEAP_SIZE > 0 + extern uint8_t __HEAP[] __HEAP_ATTRIBUTES(__HEAP_ALIGNMENT); + uint8_t __HEAP[__HEAP_SIZE] __HEAP_ATTRIBUTES(__HEAP_ALIGNMENT); + #define __HEAP_LIMIT ((uint32_t)(__HEAP + __HEAP_SIZE)) + #define __HEAP_BASE ((uint32_t)(__HEAP)) +#endif + +/*--------------------------------------------------------------------------- + Interrupt vector tables + *---------------------------------------------------------------------------*/ + +#include + +__VECTOR_TABLE_ATTRIBUTE extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + +#include + +/*--------------------------------------------------------------------------- + Memory initializer structs + *---------------------------------------------------------------------------*/ + +#if ! defined (__ARMCC_VERSION) && (defined( __GNUC__ ) || defined( __clang__ )) + +#define DO_GNU_MEM_INIT +/** Source: https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS/Core/Include/cmsis_gcc.h */ +typedef struct __copy_table { + uint32_t const * src; + uint32_t * dest; + uint32_t wlen; +} __copy_table_t; + +typedef struct __zero_table { + uint32_t * dest; + uint32_t wlen; +} __zero_table_t; + +void __STATIC_FORCEINLINE copy_region(const __copy_table_t * table) +{ + for (uint32_t i = 0; i < table->wlen; ++i) + { + table->dest[i] = table->src[i]; + } +} + +void __STATIC_FORCEINLINE zero_region(const __zero_table_t * table) +{ + for (uint32_t i = 0; i < table->wlen; ++i) + { + table->dest[i] = 0; + } +} + +void __STATIC_FORCEINLINE GNUInitializeMemories() +{ + /* Perform C memory initialization */ + #ifndef NRF_SKIP_VARIABLE_INIT + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + copy_region(pTable); + } + #endif + + #ifndef NRF_SKIP_ZERO_INIT + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + zero_region(pTable); + } + #endif + + #ifdef NRF_VECTORS_IN_RAM + /* Copy vector table from code to data region */ + extern const uint32_t __vectors_load_start; + extern uint32_t __vectors_start; + extern uint32_t __vectors_end; + + const __copy_table_t vector_copy = { + &__vectors_load_start, + &__vectors_start, + (&__vectors_end - &__vectors_start) / 4 + }; + + copy_region(&vector_copy); + + SCB->VTOR = &__vectors_start; + #endif +} +#endif + +/*--------------------------------------------------------------------------- + Implement newlib heap monitor + *---------------------------------------------------------------------------*/ +#ifdef NRF_ENABLE_HEAP_LIMIT + + #include + #include + + void * _sbrk (ptrdiff_t incr) + { + extern char __heap_base; /* Defined by the linker. */ + extern char __heap_limit; /* Defined by the linker. */ + static char * heap_top = NULL; + + if (heap_top == NULL) + heap_top = & __heap_base; + + char * prev_heap_top = heap_top; + + if ((heap_top + incr > (char *)GET_SP()) || (heap_top + incr > &__heap_limit)) + { + errno = ENOMEM; + return (void *) -1; + } + + heap_top += incr; + + return (void *) prev_heap_top; + } + +#endif +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + + /* ArmClang stack / heap setup method. */ + void __attribute__((naked)) __user_setup_stackheap() + { + __asm( + " ldr r0, = %0\n" /* __STACK_BASE */ + " mov sp, r0\n" + #if __HEAP_SIZE != 0 + " ldr r0, = %1 \n" /* __HEAP_BASE */ + " ldr r2, = %2 \n" /* __HEAP_LIMIT */ + #else + " mov r0, #0\n" + " mov r2, #0\n" + #endif + " bx lr\n" + :: "i"(__STACK_BASE), "i"(__HEAP_BASE), "i"(__HEAP_LIMIT)); + } +#endif + + +/*--------------------------------------------------------------------------- + Reset Handler called on controller reset + *---------------------------------------------------------------------------*/ +extern __NO_RETURN void __START(void); + + +__RESET_HANDLER_ATTRIBUTE void Reset_Handler(void) +{ +#ifndef NRF_NO_STACK_INIT + __set_PSP((uint32_t)(__STACK_BASE)); + #if __ARM_ARCH >= 8 + __set_MSPLIM((uint32_t)(__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(__STACK_LIMIT)); + #endif +#endif + + NRFPreInit(); + + SystemInit(); /* CMSIS System Initialization */ + +#ifdef DO_GNU_MEM_INIT + GNUInitializeMemories(); +#endif + + /* Configure vector table offset register */ +#ifdef NRF_VTOR_CONFIG + SCB->VTOR = NRF_VTOR_CONFIG; +#endif + + __START(); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*--------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *---------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while (1) + ; +} + +#ifdef INITIALIZE_USER_SECTIONS +void InitializeUserMemorySections() +{ + extern const copy_region_t __start_nrf_sections; + copy_memory_region(&__start_nrf_sections); +} +#endif + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif \ No newline at end of file diff --git a/mdk/system_nrf.h b/mdk/system_nrf.h index b65955fd7..8e16aaf7b 100644 --- a/mdk/system_nrf.h +++ b/mdk/system_nrf.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf51.c b/mdk/system_nrf51.c index 5267b42f4..7abedc0ba 100644 --- a/mdk/system_nrf51.c +++ b/mdk/system_nrf51.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -32,19 +32,19 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. /*lint ++flb "Enter library region" */ -#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ +#define __SYSTEM_CLOCK_DEFAULT (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ #if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; #elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; #elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; #endif void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; } void SystemInit(void) @@ -82,8 +82,6 @@ void SystemInit(void) } *(uint32_t volatile *)0x4006EC14 = 0xC0; } - - SystemCoreClockUpdate(); } /*lint --flb "Leave library region" */ diff --git a/mdk/system_nrf51.h b/mdk/system_nrf51.h index cc75b2344..a4634861f 100644 --- a/mdk/system_nrf51.h +++ b/mdk/system_nrf51.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf52.c b/mdk/system_nrf52.c index fc4d82802..cc482c3f0 100644 --- a/mdk/system_nrf52.c +++ b/mdk/system_nrf52.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -31,37 +31,74 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include "system_nrf52.h" #include "system_nrf52_approtect.h" -#define __SYSTEM_CLOCK_64M (64000000UL) +#define __SYSTEM_CLOCK_DEFAULT (64000000UL) -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; #elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; +#endif + +/* Simplify later device detection macros. Check DEVELOP_IN first, as they take precedence. */ +#if defined (DEVELOP_IN_NRF52805) + #define IS_NRF52805 1 +#elif defined (DEVELOP_IN_NRF52810) + #define IS_NRF52810 1 +#elif defined (DEVELOP_IN_NRF52811) + #define IS_NRF52811 1 +#elif defined (DEVELOP_IN_NRF52820) + #define IS_NRF52820 1 +#elif defined (DEVELOP_IN_NRF52832) + #define IS_NRF52832 1 +#elif defined (DEVELOP_IN_NRF52833) + #define IS_NRF52833 1 +#elif defined (DEVELOP_IN_NRF52840) + #define IS_NRF52840 1 +#elif defined (NRF52805_XXAA) + #define IS_NRF52805 1 +#elif defined (NRF52810_XXAA) + #define IS_NRF52810 1 +#elif defined (NRF52811_XXAA) + #define IS_NRF52811 1 +#elif defined (NRF52820_XXAA) + #define IS_NRF52820 1 +#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) + #define IS_NRF52832 1 +#elif defined (NRF52833_XXAA) + #define IS_NRF52833 1 +#elif defined (NRF52840_XXAA) + #define IS_NRF52840 1 +#else + #error "A supported device macro must be defined." +#endif + +/* Trace configuration */ +#define TRACE_PIN_CONFIG ((GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) \ + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos)) + +#if IS_NRF52832 + #define TRACECLK_PIN_CNF NRF_P0->PIN_CNF[20] + #define TRACEDATA0_PIN_CNF NRF_P0->PIN_CNF[18] + #define TRACEDATA1_PIN_CNF NRF_P0->PIN_CNF[16] + #define TRACEDATA2_PIN_CNF NRF_P0->PIN_CNF[15] + #define TRACEDATA3_PIN_CNF NRF_P0->PIN_CNF[14] +#elif IS_NRF52833 || IS_NRF52840 + #define TRACECLK_PIN_CNF NRF_P0->PIN_CNF[7] + #define TRACEDATA0_PIN_CNF NRF_P1->PIN_CNF[0] + #define TRACEDATA1_PIN_CNF NRF_P0->PIN_CNF[12] + #define TRACEDATA2_PIN_CNF NRF_P0->PIN_CNF[11] + #define TRACEDATA3_PIN_CNF NRF_P1->PIN_CNF[9] +#else + /* No trace supported */ #endif /* Select correct reset pin */ /* Handle DEVELOP_IN-targets first as they take precedence over the later macros */ -#if defined (DEVELOP_IN_NRF52805) \ - || defined (DEVELOP_IN_NRF52810) \ - || defined (DEVELOP_IN_NRF52811) \ - || defined (DEVELOP_IN_NRF52832) +#if IS_NRF52805 || IS_NRF52810 || IS_NRF52811 || IS_NRF52832 #define RESET_PIN 21 -#elif defined (DEVELOP_IN_NRF52820) \ - || defined (DEVELOP_IN_NRF52833) \ - || defined (DEVELOP_IN_NRF52840) - #define RESET_PIN 18 -#elif defined (NRF52805_XXAA) \ - || defined (NRF52810_XXAA) \ - || defined (NRF52811_XXAA) \ - || defined (NRF52832_XXAA) \ - || defined (NRF52832_XXAB) - #define RESET_PIN 21 -#elif defined (NRF52820_XXAA) \ - || defined (NRF52833_XXAA) \ - || defined (NRF52840_XXAA) +#elif IS_NRF52820 || IS_NRF52833 || IS_NRF52840 #define RESET_PIN 18 #else #error "A supported device macro must be defined." @@ -84,7 +121,7 @@ void nvmc_config(uint32_t mode) void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK_64M; + SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; } void SystemInit(void) @@ -94,7 +131,7 @@ void SystemInit(void) #if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + TRACEDATA0_PIN_CNF = TRACE_PIN_CONFIG; #endif /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product @@ -102,11 +139,11 @@ void SystemInit(void) #if defined (ENABLE_TRACE) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + TRACECLK_PIN_CNF = TRACE_PIN_CONFIG; + TRACEDATA0_PIN_CNF = TRACE_PIN_CONFIG; + TRACEDATA1_PIN_CNF = TRACE_PIN_CONFIG; + TRACEDATA2_PIN_CNF = TRACE_PIN_CONFIG; + TRACEDATA3_PIN_CNF = TRACE_PIN_CONFIG; #endif #if NRF52_ERRATA_12_ENABLE_WORKAROUND @@ -324,6 +361,4 @@ void SystemInit(void) NVIC_SystemReset(); } #endif - - SystemCoreClockUpdate(); } diff --git a/mdk/system_nrf52.h b/mdk/system_nrf52.h index 44e7a1eab..c24ae9015 100644 --- a/mdk/system_nrf52.h +++ b/mdk/system_nrf52.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf52805.c b/mdk/system_nrf52805.c index b84c94afb..68d7cc761 100644 --- a/mdk/system_nrf52805.c +++ b/mdk/system_nrf52805.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/system_nrf52805.h b/mdk/system_nrf52805.h index 681eb1067..ee0ee20a8 100644 --- a/mdk/system_nrf52805.h +++ b/mdk/system_nrf52805.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf52810.c b/mdk/system_nrf52810.c index b84c94afb..68d7cc761 100644 --- a/mdk/system_nrf52810.c +++ b/mdk/system_nrf52810.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/system_nrf52810.h b/mdk/system_nrf52810.h index 4daf4b715..1f12996c1 100644 --- a/mdk/system_nrf52810.h +++ b/mdk/system_nrf52810.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf52811.c b/mdk/system_nrf52811.c index b84c94afb..68d7cc761 100644 --- a/mdk/system_nrf52811.c +++ b/mdk/system_nrf52811.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/system_nrf52811.h b/mdk/system_nrf52811.h index 9a638bda3..22a839f3e 100644 --- a/mdk/system_nrf52811.h +++ b/mdk/system_nrf52811.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf52820.c b/mdk/system_nrf52820.c index b84c94afb..68d7cc761 100644 --- a/mdk/system_nrf52820.c +++ b/mdk/system_nrf52820.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/system_nrf52820.h b/mdk/system_nrf52820.h index 7134e0751..6695c1087 100644 --- a/mdk/system_nrf52820.h +++ b/mdk/system_nrf52820.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf52833.c b/mdk/system_nrf52833.c index b84c94afb..68d7cc761 100644 --- a/mdk/system_nrf52833.c +++ b/mdk/system_nrf52833.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/system_nrf52833.h b/mdk/system_nrf52833.h index d7deaa7b5..90388110f 100644 --- a/mdk/system_nrf52833.h +++ b/mdk/system_nrf52833.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf52840.c b/mdk/system_nrf52840.c index b84c94afb..68d7cc761 100644 --- a/mdk/system_nrf52840.c +++ b/mdk/system_nrf52840.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/system_nrf52840.h b/mdk/system_nrf52840.h index adfb90a01..2b4d4fd07 100644 --- a/mdk/system_nrf52840.h +++ b/mdk/system_nrf52840.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf52_approtect.h b/mdk/system_nrf52_approtect.h index c3c2450ef..6b31402c7 100644 --- a/mdk/system_nrf52_approtect.h +++ b/mdk/system_nrf52_approtect.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf53.h b/mdk/system_nrf53.h index 2981a3c12..dea2b9573 100644 --- a/mdk/system_nrf53.h +++ b/mdk/system_nrf53.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf5340_application.c b/mdk/system_nrf5340_application.c index 500449dae..b774c37a0 100644 --- a/mdk/system_nrf5340_application.c +++ b/mdk/system_nrf5340_application.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -37,7 +37,7 @@ void SystemStoreFICRNS(); /* NRF5340 application core uses a variable System Clock Frequency that starts at 64MHz */ #define __SYSTEM_CLOCK_MAX (128000000UL) -#define __SYSTEM_CLOCK_INITIAL ( 64000000UL) +#define __SYSTEM_CLOCK_DEFAULT ( 64000000UL) #define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ @@ -52,12 +52,10 @@ void SystemStoreFICRNS(); #define TRACE_TRACEDATA2_PIN TAD_PSEL_TRACEDATA2_PIN_Tracedata2 #define TRACE_TRACEDATA3_PIN TAD_PSEL_TRACEDATA3_PIN_Tracedata3 -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_INITIAL; +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; #elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_INITIAL; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_INITIAL; + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; #endif void SystemCoreClockUpdate(void) @@ -95,7 +93,7 @@ void SystemInit(void) /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim until one ADDR is not initialized. */ uint32_t index = 0; - for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){ + for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){ #if defined ( __ICCARM__ ) /* IAR will complain about the order of volatile pointer accesses. */ #pragma diag_suppress=Pa082 @@ -171,6 +169,19 @@ void SystemInit(void) } } + if (nrf53_errata_160()) + { + *((volatile uint32_t *)0x5000470C) = 0x7Eul; + *((volatile uint32_t *)0x5000493C) = 0x7Eul; + *((volatile uint32_t *)0x50002118) = 0x7Ful; + *((volatile uint32_t *)0x50039E04) = 0x0ul; + *((volatile uint32_t *)0x50039E08) = 0x0ul; + *((volatile uint32_t *)0x50101110) = 0x0ul; + *((volatile uint32_t *)0x50002124) = 0x0ul; + *((volatile uint32_t *)0x5000212C) = 0x0ul; + *((volatile uint32_t *)0x502012A0) = 0x0ul; + } + #if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM) SystemStoreFICRNS(); #endif @@ -263,8 +274,6 @@ void SystemInit(void) __DSB(); __ISB(); #endif - - SystemCoreClockUpdate(); } /* Workaround to allow NS code to access FICR. Override NRF_FICR_NS to move FICR_NS buffer. */ diff --git a/mdk/system_nrf5340_application.h b/mdk/system_nrf5340_application.h index 62ef1bb3f..8b83c1e48 100644 --- a/mdk/system_nrf5340_application.h +++ b/mdk/system_nrf5340_application.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf5340_network.c b/mdk/system_nrf5340_network.c index 504c88f67..0222b7dd7 100644 --- a/mdk/system_nrf5340_network.c +++ b/mdk/system_nrf5340_network.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -33,19 +33,17 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. /*lint ++flb "Enter library region" */ -#define __SYSTEM_CLOCK (64000000UL) /*!< NRF5340 network core uses a fixed System Clock Frequency of 64MHz */ +#define __SYSTEM_CLOCK_DEFAULT (64000000UL) /*!< NRF5340 network core uses a fixed System Clock Frequency of 64MHz */ -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; #elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; #endif void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; } void SystemInit(void) @@ -53,7 +51,7 @@ void SystemInit(void) /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim until one ADDR is not initialized. */ uint32_t index = 0; - for (index = 0; index < 32ul && NRF_FICR_NS->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){ + for (index = 0; index < 32ul && NRF_FICR_NS->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){ #if defined ( __ICCARM__ ) /* IAR will complain about the order of volatile pointer accesses. */ #pragma diag_suppress=Pa082 @@ -84,10 +82,18 @@ void SystemInit(void) } } + if (nrf53_errata_160()) + { + *((volatile uint32_t *)0x41002118) = 0x7Ful; + *((volatile uint32_t *)0x41080E04) = 0x0ul; + *((volatile uint32_t *)0x41080E08) = 0x0ul; + *((volatile uint32_t *)0x41002124) = 0x0ul; + *((volatile uint32_t *)0x4100212C) = 0x0ul; + *((volatile uint32_t *)0x41101110) = 0x0ul; + } + /* Handle fw-branch APPROTECT setup. */ nrf53_handle_approtect(); - - SystemCoreClockUpdate(); } /*lint --flb "Leave library region" */ diff --git a/mdk/system_nrf5340_network.h b/mdk/system_nrf5340_network.h index 9ec0a0340..8495db9a6 100644 --- a/mdk/system_nrf5340_network.h +++ b/mdk/system_nrf5340_network.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf53_approtect.h b/mdk/system_nrf53_approtect.h index 7b259a07a..53b52840d 100644 --- a/mdk/system_nrf53_approtect.h +++ b/mdk/system_nrf53_approtect.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf91.c b/mdk/system_nrf91.c index 610050005..575c4c8cf 100644 --- a/mdk/system_nrf91.c +++ b/mdk/system_nrf91.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,12 +29,13 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include "nrf_peripherals.h" #include "nrf91_erratas.h" #include "system_nrf91.h" +#include "system_nrf91_approtect.h" /*lint ++flb "Enter library region" */ void SystemStoreFICRNS(); -#define __SYSTEM_CLOCK (64000000UL) /*!< nRF91 Application core uses a fixed System Clock Frequency of 64MHz */ +#define __SYSTEM_CLOCK_DEFAULT (64000000UL) /*!< nRF91 Application core uses a fixed System Clock Frequency of 64MHz */ #define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ @@ -48,30 +49,25 @@ void SystemStoreFICRNS(); #define TRACE_TRACEDATA3_PIN (25) #if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; #elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; #elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#endif - -/* Global values used used in Secure mode SystemInit. */ -#if !defined(NRF_TRUSTZONE_NONSECURE) - /* Global values used by UICR erase fix algorithm. */ - static uint32_t uicr_erased_value; - static uint32_t uicr_new_value; + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; #endif /* Errata are only handled in secure mode since they usually need access to FICR. */ #if !defined(NRF_TRUSTZONE_NONSECURE) - static bool uicr_HFXOSRC_erased(void); - static bool uicr_HFXOCNT_erased(void); + #if !defined(NRF_SKIP_UICR_HFXO_WORKAROUND) + static bool uicr_HFXOSRC_erased(void); + static bool uicr_HFXOCNT_erased(void); + #endif static bool is_empty_word(uint32_t const volatile * word); #endif void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; } void SystemInit(void) @@ -91,7 +87,7 @@ void SystemInit(void) NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos); NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos); } - + /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document for your device located at https://infocenter.nordicsemi.com/index.jsp */ if (nrf91_errata_14()){ @@ -124,7 +120,7 @@ void SystemInit(void) /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim until one ADDR is not initialized. */ - + for (uint32_t index = 0; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){ #if defined ( __ICCARM__ ) #pragma diag_suppress=Pa082 @@ -135,41 +131,45 @@ void SystemInit(void) #endif } - /* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */ - if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) { - __DSB(); - /* Wait for pending NVMC operations to finish */ - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - /* Enable write mode in NVMC */ - NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - if (uicr_HFXOSRC_erased()){ - /* Write default value to UICR->HFXOSRC */ - uicr_erased_value = NRF_UICR_S->HFXOSRC; - uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; - NRF_UICR_S->HFXOSRC = uicr_new_value; - __DSB(); - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + #if !defined(NRF_SKIP_UICR_HFXO_WORKAROUND) + uint32_t uicr_erased_value; + uint32_t uicr_new_value; + /* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */ + if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) { + __DSB(); + /* Wait for pending NVMC operations to finish */ + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + /* Enable write mode in NVMC */ + NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + if (uicr_HFXOSRC_erased()){ + /* Write default value to UICR->HFXOSRC */ + uicr_erased_value = NRF_UICR_S->HFXOSRC; + uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; + NRF_UICR_S->HFXOSRC = uicr_new_value; + __DSB(); + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + } + + if (uicr_HFXOCNT_erased()){ + /* Write default value to UICR->HFXOCNT */ + uicr_erased_value = NRF_UICR_S->HFXOCNT; + uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20; + NRF_UICR_S->HFXOCNT = uicr_new_value; + __DSB(); + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + } + + /* Enable read mode in NVMC */ + NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + /* Reset to apply clock select update */ + NVIC_SystemReset(); } - - if (uicr_HFXOCNT_erased()){ - /* Write default value to UICR->HFXOCNT */ - uicr_erased_value = NRF_UICR_S->HFXOCNT; - uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20; - NRF_UICR_S->HFXOCNT = uicr_new_value; - __DSB(); - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - } - - /* Enable read mode in NVMC */ - NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - /* Reset to apply clock select update */ - NVIC_SystemReset(); - } + #endif /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product Specification to see which ones). */ @@ -203,7 +203,7 @@ void SystemInit(void) NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz; *((volatile uint32_t *)(0xE0053000ul)) = 0x00000001ul; - + *((volatile uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul; *((volatile uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul; *((volatile uint32_t *)(0xE005A004ul)) = 0x00000009ul; @@ -231,41 +231,43 @@ void SystemInit(void) /* Allow Non-Secure code to run FPU instructions. * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ SCB->NSACR |= (3UL << 10); + + nrf91_handle_approtect(); #endif /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit * operations are not used in your code. */ #if (__FPU_USED == 1) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); #endif - - SystemCoreClockUpdate(); } #if !defined(NRF_TRUSTZONE_NONSECURE) - bool uicr_HFXOCNT_erased() - { - if (is_empty_word(&NRF_UICR_S->HFXOCNT)) { - return true; + #if !defined(NRF_SKIP_UICR_HFXO_WORKAROUND) + bool uicr_HFXOCNT_erased() + { + if (is_empty_word(&NRF_UICR_S->HFXOCNT)) { + return true; + } + return false; } - return false; - } - - - bool uicr_HFXOSRC_erased() - { - uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC; - __DSB(); - if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { - return true; + + + bool uicr_HFXOSRC_erased() + { + uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC; + __DSB(); + if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { + return true; + } + return false; } - return false; - } + #endif bool is_empty_word(uint32_t const volatile * word) { diff --git a/mdk/system_nrf91.h b/mdk/system_nrf91.h index e53faa63f..fc6ac0508 100644 --- a/mdk/system_nrf91.h +++ b/mdk/system_nrf91.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf9120.h b/mdk/system_nrf9120.h new file mode 100644 index 000000000..3951be9e5 --- /dev/null +++ b/mdk/system_nrf9120.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2009-2023 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF9120_H +#define SYSTEM_NRF9120_H +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* SYSTEM_NRF9120_H */ diff --git a/mdk/system_nrf9160.c b/mdk/system_nrf9160.c index 9ab88b108..79d4c3232 100644 --- a/mdk/system_nrf9160.c +++ b/mdk/system_nrf9160.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/mdk/system_nrf9160.h b/mdk/system_nrf9160.h index 2e6932f56..ac5620268 100644 --- a/mdk/system_nrf9160.h +++ b/mdk/system_nrf9160.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2009-2023 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,28 +29,26 @@ extern "C" { #include +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); + /** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mdk/system_nrf91_approtect.h b/mdk/system_nrf91_approtect.h new file mode 100644 index 000000000..04813bb25 --- /dev/null +++ b/mdk/system_nrf91_approtect.h @@ -0,0 +1,87 @@ +/* + +Copyright (c) 2009-2023 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF91_APPROTECT_H +#define SYSTEM_NRF91_APPROTECT_H + +#include "nrf.h" +#include "nrf91_erratas.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Function that handles firmware-driven enabling or disabling of APPROTECT on devices where it is supported. + If ENABLE_APPROTECT is defined, the FW will lock the fw branch of the APPROTECT mechanism, + preventing it from being opened. + If ENABLE_APPROTECT_USER_HANDLING is defined, the FW will not write to the fw branch of the APPROTECT mechanism. + This allows later stages of the fw to handle APPROTECT, + for example to implement authenticated debug. + Otherwise, the fw branch state is loaded from UICR. + + The same mechanism is implemented for SECURE APPROTECT, with the macros + ENABLE_SECURE_APPROTECT and ENABLE_SECURE_APPROTECT_USER_HANDLING. */ + +static inline void nrf91_handle_approtect(void) +{ + if (!nrf91_errata_36()) + { + /* Target device does not support firmware-driven approtect. */ + return; + } + #if defined (NRF91_ERRATA_36_PRESENT) && NRF91_ERRATA_36_PRESENT + #if defined (NRF_APPLICATION) + #if defined (ENABLE_APPROTECT) + /* Prevent processor from unlocking APPROTECT soft branch after this point. */ + NRF_APPROTECT_S->APPROTECT.FORCEPROTECT = APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Force; + + #elif defined (ENABLE_APPROTECT_USER_HANDLING) + /* Do nothing, allow user code to handle APPROTECT. Use this if you want to enable authenticated debug. */ + + #else + /* Load APPROTECT soft branch from UICR. + If UICR->APPROTECT is disabled, APPROTECT->APPROTECT will be disabled. */ + NRF_APPROTECT_S->APPROTECT.DISABLE = NRF_UICR_S->APPROTECT; + #endif + + /* Secure APPROTECT is only available for Application core. */ + #if defined (ENABLE_SECURE_APPROTECT) + /* Prevent processor from unlocking SECURE APPROTECT soft branch after this point. */ + NRF_APPROTECT_S->SECUREAPPROTECT.FORCEPROTECT = APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Force; + + #elif defined (ENABLE_SECURE_APPROTECT_USER_HANDLING) + /* Do nothing, allow user code to handle SECURE APPROTECT. Use this if you want to enable authenticated debug. */ + + #else + /* Load SECURE APPROTECT soft branch from UICR. + If UICR->SECUREAPPROTECT is disabled, APPROTECT->SECUREAPPROTECT will be disabled. */ + NRF_APPROTECT_S->SECUREAPPROTECT.DISABLE = NRF_UICR_S->SECUREAPPROTECT; + #endif + #endif + #endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF5_APPROTECT_H */ diff --git a/nrfx.h b/nrfx.h index 4c43d8997..90fd37107 100644 --- a/nrfx.h +++ b/nrfx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_atomic.c b/soc/nrfx_atomic.c index 81bc9cb57..b8a025180 100644 --- a/soc/nrfx_atomic.c +++ b/soc/nrfx_atomic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_atomic.h b/soc/nrfx_atomic.h index 9efb0c43c..e2862c6a0 100644 --- a/soc/nrfx_atomic.h +++ b/soc/nrfx_atomic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_atomic_internal.h b/soc/nrfx_atomic_internal.h index 2db0c5221..5b83a9b8d 100644 --- a/soc/nrfx_atomic_internal.h +++ b/soc/nrfx_atomic_internal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_coredep.h b/soc/nrfx_coredep.h index ee5356973..67675871c 100644 --- a/soc/nrfx_coredep.h +++ b/soc/nrfx_coredep.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -64,7 +64,7 @@ #define NRFX_DELAY_DWT_PRESENT 0 #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ defined(NRF52833_XXAA) || defined(NRF52840_XXAA) || \ - defined(NRF9160_XXAA) + defined(NRF9120_XXAA) || defined(NRF9160_XXAA) #define NRFX_DELAY_CPU_FREQ_MHZ 64 #define NRFX_DELAY_DWT_PRESENT 1 #elif defined(NRF5340_XXAA_APPLICATION) diff --git a/soc/nrfx_irqs.h b/soc/nrfx_irqs.h index 3eae86cc9..580c8e16b 100644 --- a/soc/nrfx_irqs.h +++ b/soc/nrfx_irqs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -50,12 +50,12 @@ #include #elif defined(NRF52840_XXAA) #include -#elif defined(NRF9160_XXAA) - #include #elif defined(NRF5340_XXAA_APPLICATION) #include #elif defined(NRF5340_XXAA_NETWORK) #include +#elif defined(NRF91_SERIES) + #include #else #error "Unknown device." #endif diff --git a/soc/nrfx_irqs_nrf51.h b/soc/nrfx_irqs_nrf51.h index 3561f489b..af445a197 100644 --- a/soc/nrfx_irqs_nrf51.h +++ b/soc/nrfx_irqs_nrf51.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf52805.h b/soc/nrfx_irqs_nrf52805.h index cda5afdce..07aec049e 100644 --- a/soc/nrfx_irqs_nrf52805.h +++ b/soc/nrfx_irqs_nrf52805.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf52810.h b/soc/nrfx_irqs_nrf52810.h index 764345db0..0fff1b9c8 100644 --- a/soc/nrfx_irqs_nrf52810.h +++ b/soc/nrfx_irqs_nrf52810.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf52811.h b/soc/nrfx_irqs_nrf52811.h index 727aaebb7..e62cdab3f 100644 --- a/soc/nrfx_irqs_nrf52811.h +++ b/soc/nrfx_irqs_nrf52811.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf52820.h b/soc/nrfx_irqs_nrf52820.h index ca8060602..e93694a1c 100644 --- a/soc/nrfx_irqs_nrf52820.h +++ b/soc/nrfx_irqs_nrf52820.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf52832.h b/soc/nrfx_irqs_nrf52832.h index dcf67c48f..4672a0df7 100644 --- a/soc/nrfx_irqs_nrf52832.h +++ b/soc/nrfx_irqs_nrf52832.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf52833.h b/soc/nrfx_irqs_nrf52833.h index 806d07067..c798b4e36 100644 --- a/soc/nrfx_irqs_nrf52833.h +++ b/soc/nrfx_irqs_nrf52833.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf52840.h b/soc/nrfx_irqs_nrf52840.h index a64a0ee41..e967ce976 100644 --- a/soc/nrfx_irqs_nrf52840.h +++ b/soc/nrfx_irqs_nrf52840.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf5340_application.h b/soc/nrfx_irqs_nrf5340_application.h index 9e5632ad7..79231b2e1 100644 --- a/soc/nrfx_irqs_nrf5340_application.h +++ b/soc/nrfx_irqs_nrf5340_application.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf5340_network.h b/soc/nrfx_irqs_nrf5340_network.h index abb4191e3..951acb82f 100644 --- a/soc/nrfx_irqs_nrf5340_network.h +++ b/soc/nrfx_irqs_nrf5340_network.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/soc/nrfx_irqs_nrf9160.h b/soc/nrfx_irqs_nrf91.h similarity index 97% rename from soc/nrfx_irqs_nrf9160.h rename to soc/nrfx_irqs_nrf91.h index 27ef83e4f..32442b6dd 100644 --- a/soc/nrfx_irqs_nrf9160.h +++ b/soc/nrfx_irqs_nrf91.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -31,8 +31,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef NRFX_IRQS_NRF9160_H__ -#define NRFX_IRQS_NRF9160_H__ +#ifndef NRFX_IRQS_NRF91_H__ +#define NRFX_IRQS_NRF91_H__ #ifdef __cplusplus extern "C" { @@ -160,4 +160,4 @@ extern "C" { } #endif -#endif // NRFX_IRQS_NRF9160_H__ +#endif // NRFX_IRQS_NRF91_H__ diff --git a/templates/nrfx_config.h b/templates/nrfx_config.h index 12a951219..e46b510c6 100644 --- a/templates/nrfx_config.h +++ b/templates/nrfx_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -55,8 +55,8 @@ #include #elif defined(NRF5340_XXAA_NETWORK) #include -#elif defined(NRF9160_XXAA) - #include +#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) + #include #else #error "Unknown device." #endif diff --git a/templates/nrfx_config_common.h b/templates/nrfx_config_common.h index 09bf58b47..857df4821 100644 --- a/templates/nrfx_config_common.h +++ b/templates/nrfx_config_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Nordic Semiconductor ASA + * Copyright (c) 2022 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -39,7 +39,7 @@ #endif -// NRFX API version 2.9 flag. When the flag is set NRFX API is compatible with the previous NRFX release. +// NRFX API version 2.9 flag. #define NRFX_CONFIG_API_VER_2_9 1 // NRFX API version 2.10 flag. @@ -51,4 +51,7 @@ */ #define NRFX_CONFIG_API_VER_2_10 0 +// NRFX API version 2.11 flag. +#define NRFX_CONFIG_API_VER_2_11 0 + #endif /* NRFX_CONFIG_COMMON_H__ */ diff --git a/templates/nrfx_config_nrf51.h b/templates/nrfx_config_nrf51.h index 1dc346bcf..5b264fa2a 100644 --- a/templates/nrfx_config_nrf51.h +++ b/templates/nrfx_config_nrf51.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf52805.h b/templates/nrfx_config_nrf52805.h index 8ff165ba9..b995d8179 100644 --- a/templates/nrfx_config_nrf52805.h +++ b/templates/nrfx_config_nrf52805.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf52810.h b/templates/nrfx_config_nrf52810.h index 5c3a07e6d..3c8021cfe 100644 --- a/templates/nrfx_config_nrf52810.h +++ b/templates/nrfx_config_nrf52810.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf52811.h b/templates/nrfx_config_nrf52811.h index dbd30fcf1..dce633019 100644 --- a/templates/nrfx_config_nrf52811.h +++ b/templates/nrfx_config_nrf52811.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf52820.h b/templates/nrfx_config_nrf52820.h index d59d33b0d..12c6cbeff 100644 --- a/templates/nrfx_config_nrf52820.h +++ b/templates/nrfx_config_nrf52820.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf52832.h b/templates/nrfx_config_nrf52832.h index 7ce8e037f..953f8a785 100644 --- a/templates/nrfx_config_nrf52832.h +++ b/templates/nrfx_config_nrf52832.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf52833.h b/templates/nrfx_config_nrf52833.h index 237369a94..2615bdce5 100644 --- a/templates/nrfx_config_nrf52833.h +++ b/templates/nrfx_config_nrf52833.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf52840.h b/templates/nrfx_config_nrf52840.h index 90fe54b63..4aed28bb6 100644 --- a/templates/nrfx_config_nrf52840.h +++ b/templates/nrfx_config_nrf52840.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf5340_application.h b/templates/nrfx_config_nrf5340_application.h index 023db993d..a5524c2e1 100644 --- a/templates/nrfx_config_nrf5340_application.h +++ b/templates/nrfx_config_nrf5340_application.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf5340_network.h b/templates/nrfx_config_nrf5340_network.h index 0daac0967..a6b409389 100644 --- a/templates/nrfx_config_nrf5340_network.h +++ b/templates/nrfx_config_nrf5340_network.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_config_nrf9160.h b/templates/nrfx_config_nrf91.h similarity index 99% rename from templates/nrfx_config_nrf9160.h rename to templates/nrfx_config_nrf91.h index 5419fd2e5..ea7d35659 100644 --- a/templates/nrfx_config_nrf9160.h +++ b/templates/nrfx_config_nrf91.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -31,8 +31,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef NRFX_CONFIG_NRF9160_H__ -#define NRFX_CONFIG_NRF9160_H__ +#ifndef NRFX_CONFIG_NRF91_H__ +#define NRFX_CONFIG_NRF91_H__ #ifndef NRFX_CONFIG_H__ #error "This file should not be included directly. Include nrfx_config.h instead." @@ -1654,4 +1654,4 @@ // -#endif // NRFX_CONFIG_NRF9160_H__ +#endif // NRFX_CONFIG_NRF91_H__ diff --git a/templates/nrfx_glue.h b/templates/nrfx_glue.h index e2660755d..91484f0ff 100644 --- a/templates/nrfx_glue.h +++ b/templates/nrfx_glue.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/templates/nrfx_log.h b/templates/nrfx_log.h index 8d03ffa60..081364abb 100644 --- a/templates/nrfx_log.h +++ b/templates/nrfx_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2022, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause