From 23fb4437c08a9edfdf6d34f002322f693a15e8fe Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Tue, 25 Oct 2022 11:11:16 +0200 Subject: [PATCH] nrfx 2.10.0 release --- CHANGELOG.md | 22 + doc/nrfx.doxyfile | 12 +- doc/sphinx/requirements.txt | 11 +- drivers/include/nrfx_clock.h | 6 +- drivers/include/nrfx_egu.h | 9 + drivers/include/nrfx_ipc.h | 33 +- drivers/include/nrfx_pwm.h | 9 + drivers/include/nrfx_rtc.h | 9 + drivers/include/nrfx_saadc.h | 6 +- drivers/include/nrfx_spi.h | 9 + drivers/include/nrfx_spim.h | 9 + drivers/include/nrfx_spis.h | 9 + drivers/include/nrfx_timer.h | 12 +- drivers/include/nrfx_twi.h | 9 + drivers/include/nrfx_twim.h | 9 + drivers/include/nrfx_twis.h | 9 + drivers/include/nrfx_uart.h | 9 + drivers/include/nrfx_uarte.h | 9 + drivers/include/nrfx_wdt.h | 11 +- drivers/nrfx_common.h | 6 +- drivers/src/nrfx_clock.c | 2 +- drivers/src/nrfx_ipc.c | 17 +- drivers/src/nrfx_nfct.c | 4 +- drivers/src/nrfx_rtc.c | 2 +- drivers/src/nrfx_spis.c | 8 +- drivers/src/nrfx_timer.c | 11 +- hal/nrf_common.h | 4 + hal/nrf_egu.h | 9 + hal/nrf_pwm.h | 9 + hal/nrf_rtc.h | 9 + hal/nrf_spi.h | 9 + hal/nrf_spim.h | 9 + hal/nrf_spis.h | 9 + hal/nrf_timer.h | 30 + hal/nrf_twi.h | 9 + hal/nrf_twim.h | 11 +- hal/nrf_twis.h | 9 + hal/nrf_uarte.h | 9 + hal/nrf_wdt.h | 9 + helpers/nrfx_reset_reason.h | 35 +- mdk/arm_startup_nrf9160.s | 24 +- mdk/compiler_abstraction.h | 22 +- mdk/gcc_startup_nrf9160.S | 16 +- mdk/iar_startup_nrf9160.s | 24 +- mdk/nrf.h | 2 +- mdk/nrf51.h | 65 +- mdk/nrf51_to_nrf52810.h | 13 + mdk/nrf52.h | 52 +- mdk/nrf52805.h | 65 +- mdk/nrf52805.svd | 2 +- mdk/nrf52810.h | 65 +- mdk/nrf52810.svd | 2 +- mdk/nrf52811.h | 65 +- mdk/nrf52811.svd | 2 +- mdk/nrf52820.h | 65 +- mdk/nrf52820.svd | 2 +- mdk/nrf52833.h | 65 +- mdk/nrf52833.svd | 2 +- mdk/nrf52840.h | 65 +- mdk/nrf52840.svd | 2 +- mdk/nrf52_erratas.h | 83 ++ mdk/nrf5340_application.h | 52 +- mdk/nrf5340_application.svd | 8 +- mdk/nrf5340_application_bitfields.h | 6 +- mdk/nrf5340_application_name_change.h | 28 +- mdk/nrf5340_application_peripherals.h | 8 +- mdk/nrf5340_network.h | 52 +- mdk/nrf5340_network.svd | 2 +- mdk/nrf5340_network_name_change.h | 6 + mdk/nrf5340_network_peripherals.h | 8 +- mdk/nrf53_erratas.h | 429 +++++++- mdk/nrf9160.h | 189 ++-- mdk/nrf9160.svd | 1424 ++++++++++++++----------- mdk/nrf9160_bitfields.h | 1099 ++++++++++--------- mdk/nrf9160_name_change.h | 47 +- mdk/nrf9160_peripherals.h | 8 +- mdk/nrf91_erratas.h | 45 + mdk/ses_startup_nrf51.s | 32 +- mdk/ses_startup_nrf52.s | 160 +-- mdk/ses_startup_nrf52805.s | 186 ++-- mdk/ses_startup_nrf52810.s | 180 ++-- mdk/ses_startup_nrf52811.s | 180 ++-- mdk/ses_startup_nrf52820.s | 182 ++-- mdk/ses_startup_nrf52833.s | 152 +-- mdk/ses_startup_nrf52840.s | 148 +-- mdk/ses_startup_nrf5340_application.s | 406 +++---- mdk/ses_startup_nrf5340_network.s | 228 ++-- mdk/ses_startup_nrf9160.s | 434 ++++---- mdk/system_nrf53.h | 63 ++ mdk/system_nrf5340_application.c | 2 +- mdk/system_nrf5340_network.c | 2 +- mdk/system_nrf91.c | 326 ++++++ mdk/system_nrf91.h | 63 ++ mdk/system_nrf9160.c | 340 +----- soc/nrfx_irqs_nrf9160.h | 56 +- templates/nrfx_config.h | 1 + templates/nrfx_config_common.h | 54 + 97 files changed, 4576 insertions(+), 3165 deletions(-) create mode 100644 mdk/system_nrf53.h create mode 100644 mdk/system_nrf91.c create mode 100644 mdk/system_nrf91.h create mode 100644 templates/nrfx_config_common.h diff --git a/CHANGELOG.md b/CHANGELOG.md index 9d85e6c3b..48c5be3cc 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,28 @@ # Changelog All notable changes to this project are documented in this file. +## [2.10.0] - 2022-10-25 +### Added +- Added NRFX_CONFIG_API_VER_2_9 and NRFX_CONFIG_API_VER_2_10 symbols that guard API-breaking changes. Deprecated API is used by default. +- Added new signature for the event handler in the IPC driver that accepts event index instead of event bitmask. The previous signature is deprecated. +- Added nrfx_ipc_gpmem_get() function that is used to get data from the GPMEM register in IPC. It should be now used instead of nrfx_ipc_mem_get(), which is deprecated. +- Added samples for the following drivers: EGU, PWM, RNG, SAADC, SPIM, SPIS, TEMP, TIMER, TWIM, TWIS, UARTE. They are a part of `zephyrproject-rtos/hal_nordic/nrfx` repository. +- Introduced the NRFX_{PERIPH}_INST_HANDLER_GET() macro for getting interrupt handler associated with the specified driver instance. +- Introduced the NRFX_{PERIPH}_INST_GET() macro for getting pointer to the structure of the registers of the specified peripheral. +- Introduced the NRF_TIMER_PRESCALER_CALCULATE() macro for computing prescaler value for given TIMER base frequency and desired frequency. +- Introduced the NRF_TIMER_BASE_FREQUENCY_GET() macro for getting base frequency in Hz for the specified TIMER instance. +- Added missing NRFX_RESET_REASON_CTRLAP_MASK in nrfx_reset_reason_mask_t for nRF9160. +- Added missing NRFX_RESET_REASON_SREQ_MASK in nrfx_reset_reason_mask_t. + +### Changed +- Updated MDK to version 8.51.0. +- Refactored the TIMER driver to allow user handler to be NULL. +- Removed magic numbers from nrf_twim_event_t type in TWIM HAL. + +### Fixed +- Fixed the NRFX_ROUNDED_DIV() macro for negative numbers. +- Disabled array bounds warning for nrf_clock_is_running() function that was false positive in GCC 12 and above. + ## [2.9.0] - 2022-07-19 ### Added - Added configuration parameter NRFX_NFCT_PARAM_ID_FDT_MIN that allows settting the value of the FRAMEDELAYMIN register. diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index 5526524c5..29d6c76ca 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -40,7 +40,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "2.9" +PROJECT_NUMBER = "2.10" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a @@ -2077,15 +2077,7 @@ INCLUDE_FILE_PATTERNS = # This tag requires that the tag ENABLE_PREPROCESSING is set to YES. PREDEFINED = SUPPRESS_INLINE_IMPLEMENTATION \ - __NRFX_DOXYGEN__ \ - CONFIG_PURGE_ENABLED=1 \ - CONFIG_DISASSOCIATE_ENABLED=1 \ - CONFIG_GTS_ENABLED=1 \ - CONFIG_ORPHAN_ENABLED=1 \ - CONFIG_RXE_ENABLED=1 \ - CONFIG_START_ENABLED=1 \ - CONFIG_SYNC_ENABLED=1 \ - CONFIG_PANID_CONFLICT_ENABLED=1 + __NRFX_DOXYGEN__ # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this # tag can be used to specify a list of macro names that should be expanded. The diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 36fb32cc7..ebdaca8f5 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -1,4 +1,7 @@ -sphinx~=3.5 -sphinx-ncs-theme~=0.6.2 -breathe~=4.28 -m2r2~=0.2 +Sphinx!=5.0.0,<6,>=4.0 +sphinx-ncs-theme==0.6.5 +sphinx-rtd-theme==0.5.2 +breathe==4.34.0 +m2r2==0.3.2 +Jinja2==3.0.3 +docutils<0.17 \ No newline at end of file diff --git a/drivers/include/nrfx_clock.h b/drivers/include/nrfx_clock.h index 51a928dfb..ec6d1c391 100644 --- a/drivers/include/nrfx_clock.h +++ b/drivers/include/nrfx_clock.h @@ -253,7 +253,8 @@ void nrfx_clock_calibration_timer_start(uint8_t interval); /** @brief Function for stopping the calibration timer. */ void nrfx_clock_calibration_timer_stop(void); -/**@brief Function for returning a requested task address for the clock driver module. +/** + * @brief Function for returning a requested task address for the clock driver module. * * @param[in] task One of the peripheral tasks. * @@ -261,7 +262,8 @@ void nrfx_clock_calibration_timer_stop(void); */ NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task); -/**@brief Function for returning a requested event address for the clock driver module. +/** + * @brief Function for returning a requested event address for the clock driver module. * * @param[in] event One of the peripheral events. * diff --git a/drivers/include/nrfx_egu.h b/drivers/include/nrfx_egu.h index e62725bd1..df894c6ea 100644 --- a/drivers/include/nrfx_egu.h +++ b/drivers/include/nrfx_egu.h @@ -143,6 +143,15 @@ void nrfx_egu_trigger(nrfx_egu_t const * p_instance, uint8_t event_idx); */ void nrfx_egu_uninit(nrfx_egu_t const * p_instance); +/** + * @brief Macro returning EGU interrupt handler. + * + * param[in] idx EGU index. + * + * @return Interrupt handler. + */ +#define NRFX_EGU_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_egu_, idx, _irq_handler) + /** @} */ void nrfx_egu_0_irq_handler(void); diff --git a/drivers/include/nrfx_ipc.h b/drivers/include/nrfx_ipc.h index 8f23b38bb..85f4aacd1 100644 --- a/drivers/include/nrfx_ipc.h +++ b/drivers/include/nrfx_ipc.h @@ -47,13 +47,25 @@ extern "C" { * @brief Interprocessor Communication (IPC) peripheral driver. */ +#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10) || defined(__NRFX_DOXYGEN__) /** * @brief IPC driver handler type. * + * @param[in] event_idx IPC event index. + * @param[in] p_context Context passed to the interrupt handler, set on initialization. + */ +typedef void (*nrfx_ipc_handler_t)(uint8_t event_idx, void * p_context); +#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9) +/** + * @brief IPC driver handler type. + * + * @note This function is deprecated. Use @ref NRFX_CONFIG_API_VER_2_10 variant instead. + * * @param[in] event_mask Bitmask with events that triggered the interrupt. * @param[in] p_context Context passed to the interrupt handler, set on initialization. */ typedef void (*nrfx_ipc_handler_t)(uint32_t event_mask, void * p_context); +#endif /** @brief IPC configuration structure. */ typedef struct @@ -67,7 +79,7 @@ typedef struct * @brief Function for initializing the IPC driver. * * @param irq_priority Interrupt priority. - * @param handler Event handler provided by the user. Cannot be NULL. + * @param handler Event handler provided by the user. * @param p_context Context passed to event handler. * * @retval NRFX_SUCCESS Initialization was successful. @@ -93,21 +105,34 @@ void nrfx_ipc_config_load(nrfx_ipc_config_t const * p_config); NRFX_STATIC_INLINE void nrfx_ipc_signal(uint8_t send_index); /** - * @brief Function for storing data in GPMEM register in the IPC peripheral. + * @brief Function for storing data in the general purpose memory register. * * @param mem_index Index of the memory cell. * @param data Data to be saved. */ NRFX_STATIC_INLINE void nrfx_ipc_gpmem_set(uint8_t mem_index, uint32_t data); +#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for getting data from the general purpose memory register. + * + * @param mem_index Index of the memory cell. + * + * @return Saved data. + */ +NRFX_STATIC_INLINE uint32_t nrfx_ipc_gpmem_get(uint8_t mem_index); +#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9) /** * @brief Function for getting data from the GPMEM register in the IPC peripheral. * + * @note This function is deprecated. Use @ref nrfx_ipc_gpmem_get instead. + * * @param mem_index Index of the memory cell. * * @return Saved data. */ NRFX_STATIC_INLINE uint32_t nrfx_ipc_mem_get(uint8_t mem_index); +#endif /** @brief Function for uninitializing the IPC module. */ void nrfx_ipc_uninit(void); @@ -183,7 +208,11 @@ NRFX_STATIC_INLINE void nrfx_ipc_gpmem_set(uint8_t mem_index, uint32_t data) nrf_ipc_gpmem_set(NRF_IPC, mem_index, data); } +#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10) +NRFX_STATIC_INLINE uint32_t nrfx_ipc_gpmem_get(uint8_t mem_index) +#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9) NRFX_STATIC_INLINE uint32_t nrfx_ipc_mem_get(uint8_t mem_index) +#endif { NRFX_ASSERT(mem_index < NRFX_ARRAY_SIZE(NRF_IPC->GPMEM)); return nrf_ipc_gpmem_get(NRF_IPC, mem_index); diff --git a/drivers/include/nrfx_pwm.h b/drivers/include/nrfx_pwm.h index 4cdf50276..519fb4fa7 100644 --- a/drivers/include/nrfx_pwm.h +++ b/drivers/include/nrfx_pwm.h @@ -483,6 +483,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * p_inst } #endif // NRFX_DECLARE_ONLY +/** + * @brief Macro returning PWM interrupt handler. + * + * param[in] idx PWM index. + * + * @return Interrupt handler. + */ +#define NRFX_PWM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_pwm_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_rtc.h b/drivers/include/nrfx_rtc.h index 8469e81c2..ef5ee0d3c 100644 --- a/drivers/include/nrfx_rtc.h +++ b/drivers/include/nrfx_rtc.h @@ -361,6 +361,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * p_inst } #endif // NRFX_DECLARE_ONLY +/** + * @brief Macro returning RTC interrupt handler. + * + * param[in] idx RTC index. + * + * @return Interrupt handler. + */ +#define NRFX_RTC_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_rtc_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_saadc.h b/drivers/include/nrfx_saadc.h index 7efdc90c3..6dc9d4590 100644 --- a/drivers/include/nrfx_saadc.h +++ b/drivers/include/nrfx_saadc.h @@ -328,8 +328,10 @@ nrfx_err_t nrfx_saadc_simple_mode_set(uint32_t channel_mask, * @retval NRFX_SUCCESS Initialization was successful. * @retval NRFX_ERROR_BUSY There is a conversion or calibration ongoing. * @retval NRFX_ERROR_INVALID_PARAM Attempt to activate channel that is not configured. - * @retval NRFX_ERROR_NOT_SUPPORTED Attempt to activate internal timer or oversampling without burst - * with multiple channels enabled. + * @retval NRFX_ERROR_NOT_SUPPORTED Attempt to activate either of the following: + * * internal timer in the blocking mode, + * * internal timer with multiple channels enabled, + * * oversampling without burst with multiple channels enabled. */ nrfx_err_t nrfx_saadc_advanced_mode_set(uint32_t channel_mask, nrf_saadc_resolution_t resolution, diff --git a/drivers/include/nrfx_spi.h b/drivers/include/nrfx_spi.h index cd40c9741..966092ad5 100644 --- a/drivers/include/nrfx_spi.h +++ b/drivers/include/nrfx_spi.h @@ -271,6 +271,15 @@ nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * p_instance, */ void nrfx_spi_abort(nrfx_spi_t const * p_instance); +/** + * @brief Macro returning SPI interrupt handler. + * + * param[in] idx SPI index. + * + * @return Interrupt handler. + */ +#define NRFX_SPI_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spi_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_spim.h b/drivers/include/nrfx_spim.h index b60368eba..ad3f3312f 100644 --- a/drivers/include/nrfx_spim.h +++ b/drivers/include/nrfx_spim.h @@ -417,6 +417,15 @@ uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance); */ void nrfx_spim_abort(nrfx_spim_t const * p_instance); +/** + * @brief Macro returning SPIM interrupt handler. + * + * param[in] idx SPIM index. + * + * @return Interrupt handler. + */ +#define NRFX_SPIM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spim_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_spis.h b/drivers/include/nrfx_spis.h index 571791887..363d5c95e 100644 --- a/drivers/include/nrfx_spis.h +++ b/drivers/include/nrfx_spis.h @@ -256,6 +256,15 @@ nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * p_instance, uint8_t * p_rx_buffer, size_t rx_buffer_length); +/** + * @brief Macro returning SPIS interrupt handler. + * + * param[in] idx SPIS index. + * + * @return Interrupt handler. + */ +#define NRFX_SPIS_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spis_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_timer.h b/drivers/include/nrfx_timer.h index 3bf5b326a..8781b73d6 100644 --- a/drivers/include/nrfx_timer.h +++ b/drivers/include/nrfx_timer.h @@ -131,8 +131,7 @@ typedef void (* nrfx_timer_event_handler_t)(nrf_timer_event_t event_type, * * @param[in] p_instance Pointer to the driver instance structure. * @param[in] p_config Pointer to the structure with the initial configuration. - * @param[in] timer_event_handler Event handler provided by the user. - * Must not be NULL. + * @param[in] timer_event_handler Event handler provided by the user. Can be NULL. * * @retval NRFX_SUCCESS Initialization was successful. * @retval NRFX_ERROR_INVALID_STATE The instance is already initialized. @@ -386,6 +385,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * p_instan } #endif // NRFX_DECLARE_ONLY +/** + * @brief Macro returning TIMER interrupt handler. + * + * param[in] idx TIMER index. + * + * @return Interrupt handler. + */ +#define NRFX_TIMER_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_timer_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_twi.h b/drivers/include/nrfx_twi.h index 6ad06c07b..a1e28d703 100644 --- a/drivers/include/nrfx_twi.h +++ b/drivers/include/nrfx_twi.h @@ -349,6 +349,15 @@ NRFX_STATIC_INLINE nrfx_err_t nrfx_twi_bus_recover(uint32_t scl_pin, uint32_t sd } #endif +/** + * @brief Macro returning TWI interrupt handler. + * + * param[in] idx TWI index. + * + * @return Interrupt handler. + */ +#define NRFX_TWI_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twi_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_twim.h b/drivers/include/nrfx_twim.h index 3e378fc8f..da83ecce9 100644 --- a/drivers/include/nrfx_twim.h +++ b/drivers/include/nrfx_twim.h @@ -389,6 +389,15 @@ NRFX_STATIC_INLINE nrfx_err_t nrfx_twim_bus_recover(uint32_t scl_pin, uint32_t s } #endif +/** + * @brief Macro returning TWIM interrupt handler. + * + * param[in] idx TWIM index. + * + * @return Interrupt handler. + */ +#define NRFX_TWIM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twim_, idx, _irq_handler) + /** @} */ void nrfx_twim_0_irq_handler(void); diff --git a/drivers/include/nrfx_twis.h b/drivers/include/nrfx_twis.h index 30d3a7491..91fc5c907 100644 --- a/drivers/include/nrfx_twis.h +++ b/drivers/include/nrfx_twis.h @@ -404,6 +404,15 @@ NRFX_STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance) } #endif // NRFX_DECLARE_ONLY +/** + * @brief Macro returning TWIS interrupt handler. + * + * param[in] idx TWIS index. + * + * @return Interrupt handler. + */ +#define NRFX_TWIS_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twis_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_uart.h b/drivers/include/nrfx_uart.h index a88eceee8..178aabeb1 100644 --- a/drivers/include/nrfx_uart.h +++ b/drivers/include/nrfx_uart.h @@ -384,6 +384,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_in } #endif // NRFX_DECLARE_ONLY +/** + * @brief Macro returning UART interrupt handler. + * + * param[in] idx UART index. + * + * @return Interrupt handler. + */ +#define NRFX_UART_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_uart_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_uarte.h b/drivers/include/nrfx_uarte.h index bc64a907d..51a0b9156 100644 --- a/drivers/include/nrfx_uarte.h +++ b/drivers/include/nrfx_uarte.h @@ -399,6 +399,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_ } #endif // NRFX_DECLARE_ONLY +/** + * @brief Macro returning UARTE interrupt handler. + * + * param[in] idx UARTE index. + * + * @return Interrupt handler. + */ +#define NRFX_UARTE_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_uarte_, idx, _irq_handler) + /** @} */ diff --git a/drivers/include/nrfx_wdt.h b/drivers/include/nrfx_wdt.h index 75911d740..b052b0680 100644 --- a/drivers/include/nrfx_wdt.h +++ b/drivers/include/nrfx_wdt.h @@ -87,7 +87,7 @@ enum { .drv_inst_idx = NRFX_CONCAT_3(NRFX_WDT, id, _INST_IDX), \ } -/**@brief Struct for WDT initialization. */ +/** @brief Struct for WDT initialization. */ typedef struct { nrf_wdt_behaviour_t behaviour; /**< WDT behaviour when CPU in sleep/halt mode. */ @@ -205,6 +205,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_wdt_event_address_get(nrfx_wdt_t const * p_inst } #endif // NRFX_DECLARE_ONLY +/** + * @brief Macro returning WDT interrupt handler. + * + * param[in] idx WDT index. + * + * @return Interrupt handler. + */ +#define NRFX_WDT_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_wdt_, idx, _irq_handler) + /** @} */ diff --git a/drivers/nrfx_common.h b/drivers/nrfx_common.h index b47750e48..6db8cc7b6 100644 --- a/drivers/nrfx_common.h +++ b/drivers/nrfx_common.h @@ -177,7 +177,8 @@ extern "C" { * * @return Rounded (integer) result of dividing @c a by @c b. */ -#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) +#define NRFX_ROUNDED_DIV(a, b) \ + ((((a) < 0) ^ ((b) < 0)) ? (((a) - (b) / 2) / (b)) : (((a) + (b) / 2) / (b))) /** * @brief Macro for performing integer division, making sure the result is rounded up. @@ -212,7 +213,8 @@ extern "C" { */ #define NRFX_OFFSETOF(type, member) ((size_t)&(((type *)0)->member)) -/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed +/** + * @brief Macro for checking if given lengths of EasyDMA transfers do not exceed * the limit of the specified peripheral. * * @param[in] peripheral Peripheral to check the lengths against. diff --git a/drivers/src/nrfx_clock.c b/drivers/src/nrfx_clock.c index 8deb8cf3f..4847d75bc 100644 --- a/drivers/src/nrfx_clock.c +++ b/drivers/src/nrfx_clock.c @@ -127,7 +127,7 @@ typedef enum } nrfx_clock_cal_state_t; #endif -/**@brief CLOCK control block. */ +/** @brief CLOCK control block. */ typedef struct { nrfx_clock_event_handler_t event_handler; diff --git a/drivers/src/nrfx_ipc.c b/drivers/src/nrfx_ipc.c index 8646a0942..16464f846 100644 --- a/drivers/src/nrfx_ipc.c +++ b/drivers/src/nrfx_ipc.c @@ -49,7 +49,6 @@ static ipc_control_block_t m_ipc_cb; nrfx_err_t nrfx_ipc_init(uint8_t irq_priority, nrfx_ipc_handler_t handler, void * p_context) { - NRFX_ASSERT(handler); if (m_ipc_cb.state != NRFX_DRV_STATE_UNINITIALIZED) { return NRFX_ERROR_ALREADY_INITIALIZED; @@ -147,18 +146,26 @@ void nrfx_ipc_irq_handler(void) { // Get the information about events that fire this interrupt uint32_t events_map = nrf_ipc_int_pending_get(NRF_IPC); - // Clear these events uint32_t bitmask = events_map; + while (bitmask) { uint8_t event_idx = NRF_CTZ(bitmask); bitmask &= ~(1UL << event_idx); nrf_ipc_event_clear(NRF_IPC, nrf_ipc_receive_event_get(event_idx)); +#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10) + if (m_ipc_cb.handler) + { + m_ipc_cb.handler(event_idx, m_ipc_cb.p_context); + } +#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9) + } + if (m_ipc_cb.handler) + { + m_ipc_cb.handler(events_map, m_ipc_cb.p_context); +#endif } - - // Execute interrupt handler to provide information about events to app - m_ipc_cb.handler(events_map, m_ipc_cb.p_context); } #endif // NRFX_CHECK(NRFX_IPC_ENABLED) diff --git a/drivers/src/nrfx_nfct.c b/drivers/src/nrfx_nfct.c index 8d043f89d..db48a28cb 100644 --- a/drivers/src/nrfx_nfct.c +++ b/drivers/src/nrfx_nfct.c @@ -136,7 +136,7 @@ typedef enum NRFX_NFC_FIELD_STATE_UNKNOWN /**< Both NFCT field events have been set - ambiguous state. */ } nrfx_nfct_field_state_t; -/**@brief NFCT control block. */ +/** @brief NFCT control block. */ typedef struct { nrfx_nfct_config_t config; @@ -175,7 +175,7 @@ static void nrfx_nfct_frame_delay_max_set(bool default_delay) } } -/**@brief Function for evaluating and handling the NFC field events. +/** @brief Function for evaluating and handling the NFC field events. * * @param[in] field_state Current field state. */ diff --git a/drivers/src/nrfx_rtc.c b/drivers/src/nrfx_rtc.c index acafa54d7..936ab1c82 100644 --- a/drivers/src/nrfx_rtc.c +++ b/drivers/src/nrfx_rtc.c @@ -55,7 +55,7 @@ "UNKNOWN EVENT")))))) -/**@brief RTC driver instance control block structure. */ +/** @brief RTC driver instance control block structure. */ typedef struct { nrfx_drv_state_t state; /**< Instance state. */ diff --git a/drivers/src/nrfx_spis.c b/drivers/src/nrfx_spis.c index ba946b767..ffa975caa 100644 --- a/drivers/src/nrfx_spis.c +++ b/drivers/src/nrfx_spis.c @@ -101,7 +101,7 @@ static void csn_event_handler(nrfx_gpiote_pin_t pin, #endif -/**@brief States of the SPI transaction state machine. */ +/** @brief States of the SPI transaction state machine. */ typedef enum { SPIS_STATE_INIT, /**< Initialization state. In this state the module waits for a call to @ref spi_slave_buffers_set. */ @@ -110,7 +110,7 @@ typedef enum SPIS_XFER_COMPLETED /**< State where SPI transaction has been completed. */ } nrfx_spis_state_t; -/**@brief SPIS control block - driver instance local data. */ +/** @brief SPIS control block - driver instance local data. */ typedef struct { volatile uint32_t tx_buffer_size; //!< SPI slave TX buffer size in bytes. @@ -344,7 +344,7 @@ void nrfx_spis_uninit(nrfx_spis_t const * p_instance) } -/**@brief Function for executing the state entry action. */ +/** @brief Function for executing the state entry action. */ static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis, spis_cb_t * p_cb) { @@ -383,7 +383,7 @@ static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis, } } -/**@brief Function for changing the state of the SPI state machine. +/** @brief Function for changing the state of the SPI state machine. * * @param[in] p_spis SPIS instance register. * @param[in] p_cb SPIS instance control block. diff --git a/drivers/src/nrfx_timer.c b/drivers/src/nrfx_timer.c index f8d2c674b..da00b928c 100644 --- a/drivers/src/nrfx_timer.c +++ b/drivers/src/nrfx_timer.c @@ -62,7 +62,7 @@ #define NRFX_LOG_MODULE TIMER #include -/**@brief Timer control block. */ +/** @brief Timer control block. */ typedef struct { nrfx_timer_event_handler_t handler; @@ -81,7 +81,6 @@ nrfx_err_t nrfx_timer_init(nrfx_timer_t const * p_instance, NRFX_ASSERT(p_instance->p_reg != NRF_TIMER0); #endif NRFX_ASSERT(p_config); - NRFX_ASSERT(timer_event_handler); nrfx_err_t err_code; @@ -112,7 +111,8 @@ nrfx_err_t nrfx_timer_init(nrfx_timer_t const * p_instance, nrf_timer_mode_set(p_instance->p_reg, p_config->mode); nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width); - nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency); + // nrf_timer_frequency_t is mapped to prescaler for 16MHz base clock frequency timers + nrf_timer_prescaler_set(p_instance->p_reg, (uint32_t)p_config->frequency); p_cb->state = NRFX_DRV_STATE_INITIALIZED; @@ -282,7 +282,10 @@ static void irq_handler(NRF_TIMER_Type * p_reg, { nrf_timer_event_clear(p_reg, event); NRFX_LOG_DEBUG("Compare event, channel: %d.", i); - p_cb->handler(event, p_cb->context); + if (p_cb->handler) + { + p_cb->handler(event, p_cb->context); + } } } } diff --git a/hal/nrf_common.h b/hal/nrf_common.h index a39529291..9e3f2cca2 100644 --- a/hal/nrf_common.h +++ b/hal/nrf_common.h @@ -42,6 +42,10 @@ extern "C" { #define NRFX_EVENT_READBACK_ENABLED 1 #endif +#if !defined(NRFX_CONFIG_API_VER_2_9) && !defined(NRFX_CONFIG_API_VER_2_10) +#define NRFX_CONFIG_API_VER_2_9 1 +#endif + #if defined(NRFX_CLZ) #define NRF_CLZ(value) NRFX_CLZ(value) #else diff --git a/hal/nrf_egu.h b/hal/nrf_egu.h index f91a32709..9154191f0 100644 --- a/hal/nrf_egu.h +++ b/hal/nrf_egu.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the EGU peripheral. + * + * @param[in] idx EGU instance index. + * + * @return Pointer to the structure of registers of the EGU peripheral. + */ +#define NRF_EGU_INST_GET(idx) NRFX_CONCAT_2(NRF_EGU, idx) + /** @brief EGU tasks. */ typedef enum { diff --git a/hal/nrf_pwm.h b/hal/nrf_pwm.h index 75ca1e2ad..9745a193f 100644 --- a/hal/nrf_pwm.h +++ b/hal/nrf_pwm.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the PWM peripheral. + * + * @param[in] idx PWM instance index. + * + * @return Pointer to the structure of registers of the PWM peripheral. + */ + #define NRF_PWM_INST_GET(idx) NRFX_CONCAT_2(NRF_PWM, idx) + /** * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set * function call to specify that a given output channel shall not be diff --git a/hal/nrf_rtc.h b/hal/nrf_rtc.h index e93d52a15..126af564c 100644 --- a/hal/nrf_rtc.h +++ b/hal/nrf_rtc.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the Real Time Counter (RTC) peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the RTC peripheral. + * + * @param[in] idx RTC instance index. + * + * @return Pointer to the structure of registers of the RTC peripheral. + */ +#define NRF_RTC_INST_GET(idx) NRFX_CONCAT_2(NRF_RTC, idx) + /** @brief Macro for getting the number of compare channels available in a given RTC instance. */ #define NRF_RTC_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(RTC, id, _CC_NUM) diff --git a/hal/nrf_spi.h b/hal/nrf_spi.h index f9c5fe8ae..39f368c0e 100644 --- a/hal/nrf_spi.h +++ b/hal/nrf_spi.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the SPI peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the SPI peripheral. + * + * @param[in] idx SPI instance index. + * + * @return Pointer to the structure of registers of the SPI peripheral. + */ +#define NRF_SPI_INST_GET(idx) NRFX_CONCAT_2(NRF_SPI, idx) + /** * @brief This value can be used as a parameter for the @ref nrf_spi_pins_set * function to specify that a given SPI signal (SCK, MOSI, or MISO) diff --git a/hal/nrf_spim.h b/hal/nrf_spim.h index 12a5947c2..d7cd1ed08 100644 --- a/hal/nrf_spim.h +++ b/hal/nrf_spim.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the SPIM peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the SPIM peripheral. + * + * @param[in] idx SPIM instance index. + * + * @return Pointer to the structure of registers of the SPIM peripheral. + */ +#define NRF_SPIM_INST_GET(idx) NRFX_CONCAT_2(NRF_SPIM, idx) + #if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether 32 MHz clock frequency is available. */ #define NRF_SPIM_HAS_32_MHZ_FREQ 1 diff --git a/hal/nrf_spis.h b/hal/nrf_spis.h index 710a8efa6..7dc267493 100644 --- a/hal/nrf_spis.h +++ b/hal/nrf_spis.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the SPIS peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the SPIS peripheral. + * + * @param[in] idx SPIS instance index. + * + * @return Pointer to the structure of registers of the SPIS peripheral. + */ +#define NRF_SPIS_INST_GET(idx) NRFX_CONCAT_2(NRF_SPIS, idx) + /** * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set * function to specify that a given SPI signal (SCK, MOSI, or MISO) diff --git a/hal/nrf_timer.h b/hal/nrf_timer.h index ada9dfd0a..e98c7bd6b 100644 --- a/hal/nrf_timer.h +++ b/hal/nrf_timer.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the TIMER peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the TIMER peripheral. + * + * @param[in] idx TIMER instance index. + * + * @return Pointer to the structure of registers of the TIMER peripheral. + */ +#define NRF_TIMER_INST_GET(idx) NRFX_CONCAT_2(NRF_TIMER, idx) + #if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether timer has capture/compare channel 4. */ #define NRF_TIMER_HAS_CC4 1 @@ -89,6 +98,9 @@ extern "C" { #define NRF_TIMER_HAS_ONE_SHOT 0 #endif +/** @brief Base frequency value 16 MHz for timer. */ +#define NRF_TIMER_BASE_FREQUENCY_16MHZ (16000000UL) + /** @brief Maximum value of PRESCALER register. */ #define NRF_TIMER_PRESCALER_MAX 9 @@ -154,6 +166,24 @@ extern "C" { #error "Not supported timer count" #endif +/** + * @brief Macro for getting base frequency value in Hz for the specified timer. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +#define NRF_TIMER_BASE_FREQUENCY_GET(p_reg) NRF_TIMER_BASE_FREQUENCY_16MHZ + +/** + * @brief Macro for computing prescaler value for given base frequency and desired frequency. + * + * @warning Not every combination of base frequency and desired frequency is supported. + * + * @param[in] base_freq Base clock frequency for timer in Hz. + * @param[in] frequency Desired frequency value in Hz. + */ +#define NRF_TIMER_PRESCALER_CALCULATE(base_freq, frequency) \ + NRF_CTZ((uint32_t)(base_freq) / (uint32_t)(frequency)) + /** * @brief Macro for getting the number of capture/compare channels available * in a given timer instance. diff --git a/hal/nrf_twi.h b/hal/nrf_twi.h index df76f9832..e86c9d2b3 100644 --- a/hal/nrf_twi.h +++ b/hal/nrf_twi.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the TWI peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the TWI peripheral. + * + * @param[in] idx TWI instance index. + * + * @return Pointer to the structure of registers of the TWI peripheral. + */ +#define NRF_TWI_INST_GET(idx) NRFX_CONCAT_2(NRF_TWI, idx) + /** @brief TWI tasks. */ typedef enum { diff --git a/hal/nrf_twim.h b/hal/nrf_twim.h index 75dcb2dbc..3a0d68b28 100644 --- a/hal/nrf_twim.h +++ b/hal/nrf_twim.h @@ -47,6 +47,15 @@ extern "C" { * @brief Hardware access layer for managing the TWIM peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the TWIM peripheral. + * + * @param[in] idx TWIM instance index. + * + * @return Pointer to the structure of registers of the TWIM peripheral. + */ +#define NRF_TWIM_INST_GET(idx) NRFX_CONCAT_2(NRF_TWIM, idx) + #if defined(TWIM_FREQUENCY_FREQUENCY_K1000) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether 1000 kHz clock frequency is available. */ #define NRF_TWIM_HAS_1000_KHZ_FREQ 1 @@ -69,7 +78,7 @@ typedef enum { NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped. NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error. - NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended. + NRF_TWIM_EVENT_SUSPENDED = offsetof(NRF_TWIM_Type, EVENTS_SUSPENDED), ///< TWI suspended. NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started. NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started. NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte. diff --git a/hal/nrf_twis.h b/hal/nrf_twis.h index bf03f8730..949a5b584 100644 --- a/hal/nrf_twis.h +++ b/hal/nrf_twis.h @@ -48,6 +48,15 @@ extern "C" { * (TWIS) peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the TWIS peripheral. + * + * @param[in] idx TWIS instance index. + * + * @return Pointer to the structure of registers of the TWIS peripheral. + */ +#define NRF_TWIS_INST_GET(idx) NRFX_CONCAT_2(NRF_TWIS, idx) + /** @brief TWIS tasks. */ typedef enum { diff --git a/hal/nrf_uarte.h b/hal/nrf_uarte.h index 3e47ef6a0..58c8d3a5b 100644 --- a/hal/nrf_uarte.h +++ b/hal/nrf_uarte.h @@ -49,6 +49,15 @@ extern "C" { * @brief Hardware access layer for managing the UARTE peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the UARTE peripheral. + * + * @param[in] idx UARTE instance index. + * + * @return Pointer to the structure of registers of the UARTE peripheral. + */ +#define NRF_UARTE_INST_GET(idx) NRFX_CONCAT_2(NRF_UARTE, idx) + /** @brief UARTE tasks. */ typedef enum { diff --git a/hal/nrf_wdt.h b/hal/nrf_wdt.h index 457378f13..9cd3a2a12 100644 --- a/hal/nrf_wdt.h +++ b/hal/nrf_wdt.h @@ -51,6 +51,15 @@ extern "C" { * @brief Hardware access layer for managing the Watchdog Timer (WDT) peripheral. */ +/** + * @brief Macro getting pointer to the structure of registers of the WDT peripheral. + * + * @param[in] idx WDT instance index. + * + * @return Pointer to the structure of registers of the WDT peripheral. + */ +#define NRF_WDT_INST_GET(idx) NRFX_CONCAT_2(NRF_WDT, idx) + /** @brief Number of WDT channels. */ #define NRF_WDT_CHANNEL_NUMBER 0x8UL diff --git a/helpers/nrfx_reset_reason.h b/helpers/nrfx_reset_reason.h index b2c1b3cd2..c87758398 100644 --- a/helpers/nrfx_reset_reason.h +++ b/helpers/nrfx_reset_reason.h @@ -59,46 +59,48 @@ extern "C" { typedef enum { #if !NRF_POWER_HAS_RESETREAS || defined(__NRFX_DOXYGEN__) - NRFX_RESET_REASON_RESETPIN_MASK = RESET_RESETREAS_RESETPIN_Msk, /**< Reset from pin-reset detected. */ + NRFX_RESET_REASON_RESETPIN_MASK = RESET_RESETREAS_RESETPIN_Msk, + /**< Reset from watchdog/application watchdog timer 0 detected. */ NRFX_RESET_REASON_DOG0_MASK = RESET_RESETREAS_DOG0_Msk, /**< Reset from watchdog/application watchdog timer 0 detected. */ NRFX_RESET_REASON_DOG_MASK = NRFX_RESET_REASON_DOG0_MASK, - /**< Reset from watchdog/application watchdog timer 0 detected. */ - NRFX_RESET_REASON_CTRLAP_MASK = RESET_RESETREAS_CTRLAP_Msk, /**< Reset from application CTRL-AP detected. */ + NRFX_RESET_REASON_CTRLAP_MASK = RESET_RESETREAS_CTRLAP_Msk, + /**< Reset from soft reset/application soft reset detected. Deprecated. */ NRFX_RESETREAS_SREQ_MASK = RESET_RESETREAS_SREQ_Msk, /**< Reset from soft reset/application soft reset detected. */ - NRFX_RESET_REASON_LOCKUP_MASK = RESET_RESETREAS_LOCKUP_Msk, + NRFX_RESET_REASON_SREQ_MASK = RESET_RESETREAS_SREQ_Msk, /**< Reset from CPU lockup/application CPU lockup detected. */ - NRFX_RESET_REASON_OFF_MASK = RESET_RESETREAS_OFF_Msk, + NRFX_RESET_REASON_LOCKUP_MASK = RESET_RESETREAS_LOCKUP_Msk, /**< Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from * GPIO. */ - NRFX_RESET_REASON_LPCOMP_MASK = RESET_RESETREAS_LPCOMP_Msk, + NRFX_RESET_REASON_OFF_MASK = RESET_RESETREAS_OFF_Msk, /**< Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from * LPCOMP. */ - NRFX_RESET_REASON_DIF_MASK = RESET_RESETREAS_DIF_Msk, + NRFX_RESET_REASON_LPCOMP_MASK = RESET_RESETREAS_LPCOMP_Msk, /**< Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug * interface mode. */ + NRFX_RESET_REASON_DIF_MASK = RESET_RESETREAS_DIF_Msk, #if NRF_RESET_HAS_NETWORK - NRFX_RESET_REASON_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk, /**< Reset from network soft reset detected. */ - NRFX_RESET_REASON_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk, + NRFX_RESET_REASON_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk, /**< Reset from network CPU lockup detected. */ - NRFX_RESET_REASON_LDOG_MASK = RESET_RESETREAS_LDOG_Msk, + NRFX_RESET_REASON_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk, /**< Reset from network watchdog timer detected. */ - NRFX_RESET_REASON_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk, + NRFX_RESET_REASON_LDOG_MASK = RESET_RESETREAS_LDOG_Msk, /**< Force off reset from application core detected. */ + NRFX_RESET_REASON_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk, #endif // NRF_RESET_HAS_NETWORK + /**< Reset after wakeup from System OFF mode due to NFC field being detected. */ NRFX_RESET_REASON_NFC_MASK = RESET_RESETREAS_NFC_Msk, - /**< Reset after wakeup from System OFF mode due to NRF field being detected. */ - NRFX_RESET_REASON_DOG1_MASK = RESET_RESETREAS_DOG1_Msk, /**< Reset from application watchdog timer 1 detected. */ - NRFX_RESET_REASON_VBUS_MASK = RESET_RESETREAS_VBUS_Msk, + NRFX_RESET_REASON_DOG1_MASK = RESET_RESETREAS_DOG1_Msk, /**< Reset after wakeup from System OFF mode due to VBUS rising into valid range. */ + NRFX_RESET_REASON_VBUS_MASK = RESET_RESETREAS_VBUS_Msk, #if NRF_RESET_HAS_NETWORK - NRFX_RESET_REASON_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk, /**< Reset from network CTRL-AP detected. */ + NRFX_RESET_REASON_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk, #endif // NRF_RESET_HAS_NETWORK #else NRFX_RESET_REASON_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, @@ -106,6 +108,9 @@ typedef enum NRFX_RESET_REASON_SREQ_MASK = POWER_RESETREAS_SREQ_Msk , NRFX_RESET_REASON_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk, NRFX_RESET_REASON_OFF_MASK = POWER_RESETREAS_OFF_Msk, +#if defined(POWER_RESETREAS_CTRLAP_Msk) + NRFX_RESET_REASON_CTRLAP_MASK = POWER_RESETREAS_CTRLAP_Msk, +#endif #if defined(POWER_RESETREAS_LPCOMP_Msk) NRFX_RESET_REASON_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk, #endif diff --git a/mdk/arm_startup_nrf9160.s b/mdk/arm_startup_nrf9160.s index d47dbcd27..ab461044f 100644 --- a/mdk/arm_startup_nrf9160.s +++ b/mdk/arm_startup_nrf9160.s @@ -92,10 +92,10 @@ __Vectors DCD __initial_sp ; Top of Stack DCD CLOCK_POWER_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved - DCD UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler - DCD UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler - DCD UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler - DCD UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler + DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler DCD 0 ; Reserved DCD GPIOTE0_IRQHandler DCD SAADC_IRQHandler @@ -399,10 +399,10 @@ Default_Handler PROC EXPORT SPU_IRQHandler [WEAK] EXPORT CLOCK_POWER_IRQHandler [WEAK] - EXPORT UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler [WEAK] - EXPORT UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler [WEAK] - EXPORT UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler [WEAK] - EXPORT UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler [WEAK] + EXPORT SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler [WEAK] + EXPORT SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler [WEAK] + EXPORT SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler [WEAK] + EXPORT SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler [WEAK] EXPORT GPIOTE0_IRQHandler [WEAK] EXPORT SAADC_IRQHandler [WEAK] EXPORT TIMER0_IRQHandler [WEAK] @@ -430,10 +430,10 @@ Default_Handler PROC EXPORT CRYPTOCELL_IRQHandler [WEAK] SPU_IRQHandler CLOCK_POWER_IRQHandler -UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler -UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler -UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler -UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler +SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler GPIOTE0_IRQHandler SAADC_IRQHandler TIMER0_IRQHandler diff --git a/mdk/compiler_abstraction.h b/mdk/compiler_abstraction.h index 80e9d0bb6..0503aa3f6 100644 --- a/mdk/compiler_abstraction.h +++ b/mdk/compiler_abstraction.h @@ -57,7 +57,7 @@ POSSIBILITY OF SUCH DAMAGE. #ifndef __WEAK #define __WEAK __weak #endif - + #ifndef __ALIGN #define __ALIGN(n) __align(n) #endif @@ -72,6 +72,10 @@ POSSIBILITY OF SUCH DAMAGE. #define GET_SP() __current_sp() + #ifndef __DEPRECATED + #define __DEPRECATED(msg) __attribute__((deprecated(msg))) + #endif + #ifndef NRF_STATIC_ASSERT #define NRF_STATIC_ASSERT(cond, msg) \ ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) } @@ -105,6 +109,10 @@ POSSIBILITY OF SUCH DAMAGE. #define GET_SP() __current_sp() + #ifndef __DEPRECATED + #define __DEPRECATED(msg) __attribute__((deprecated(msg))) + #endif + #ifndef NRF_STATIC_ASSERT #ifdef __cplusplus #ifndef _Static_assert @@ -153,6 +161,10 @@ POSSIBILITY OF SUCH DAMAGE. #define GET_SP() __get_SP() + #ifndef __DEPRECATED + #define __DEPRECATED(msg) __attribute__((deprecated(msg))) + #endif + #ifndef NRF_STATIC_ASSERT #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) #endif @@ -185,6 +197,10 @@ POSSIBILITY OF SUCH DAMAGE. #define GET_SP() gcc_current_sp() + #ifndef __DEPRECATED + #define __DEPRECATED(msg) __attribute__((deprecated(msg))) + #endif + static inline unsigned int gcc_current_sp(void) { unsigned int stack_pointer = 0; @@ -230,6 +246,10 @@ POSSIBILITY OF SUCH DAMAGE. #define GET_SP() __get_MSP() + #ifndef __DEPRECATED + #define __DEPRECATED(msg) + #endif + #ifndef NRF_STATIC_ASSERT #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) #endif diff --git a/mdk/gcc_startup_nrf9160.S b/mdk/gcc_startup_nrf9160.S index 37d3843d4..6e8953163 100644 --- a/mdk/gcc_startup_nrf9160.S +++ b/mdk/gcc_startup_nrf9160.S @@ -98,10 +98,10 @@ __isr_vector: .long CLOCK_POWER_IRQHandler .long 0 /*Reserved */ .long 0 /*Reserved */ - .long UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler - .long UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler - .long UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler - .long UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + .long SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + .long SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler .long 0 /*Reserved */ .long GPIOTE0_IRQHandler .long SAADC_IRQHandler @@ -502,10 +502,10 @@ Default_Handler: IRQ SPU_IRQHandler IRQ CLOCK_POWER_IRQHandler - IRQ UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler - IRQ UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler - IRQ UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler - IRQ UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + IRQ SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + IRQ SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler IRQ GPIOTE0_IRQHandler IRQ SAADC_IRQHandler IRQ TIMER0_IRQHandler diff --git a/mdk/iar_startup_nrf9160.s b/mdk/iar_startup_nrf9160.s index 1a5dac62b..ec4350b0d 100644 --- a/mdk/iar_startup_nrf9160.s +++ b/mdk/iar_startup_nrf9160.s @@ -93,10 +93,10 @@ __vector_table DCD CLOCK_POWER_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved - DCD UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler - DCD UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler - DCD UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler - DCD UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler + DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler DCD 0 ; Reserved DCD GPIOTE0_IRQHandler DCD SAADC_IRQHandler @@ -409,24 +409,24 @@ SPU_IRQHandler CLOCK_POWER_IRQHandler B . - PUBWEAK UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler + PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler +SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler B . - PUBWEAK UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler + PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler +SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler B . - PUBWEAK UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler + PUBWEAK SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler +SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler B . - PUBWEAK UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler + PUBWEAK SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler +SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler B . PUBWEAK GPIOTE0_IRQHandler diff --git a/mdk/nrf.h b/mdk/nrf.h index 7538a2de3..bba19a570 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -37,7 +37,7 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 47 +#define MDK_MINOR_VERSION 51 #define MDK_MICRO_VERSION 0 diff --git a/mdk/nrf51.h b/mdk/nrf51.h index 8c5e431da..b2df90f16 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -1,41 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n * * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:35 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:46 * from File 'nrf51.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -112,6 +112,7 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ #define __CM0_REV 0x0301U /*!< CM0 Core Revision */ +#define __INTERRUPTS_MAX 32 /*!< Top interrupt number */ #define __DSP_PRESENT 0 /*!< DSP present or not */ #define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ diff --git a/mdk/nrf51_to_nrf52810.h b/mdk/nrf51_to_nrf52810.h index cf357a192..a356295a5 100644 --- a/mdk/nrf51_to_nrf52810.h +++ b/mdk/nrf51_to_nrf52810.h @@ -171,6 +171,19 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk #endif +/* UART */ +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif /* From nrf51_deprecated.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ diff --git a/mdk/nrf52.h b/mdk/nrf52.h index a8894c4d3..2ca8b725b 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -1,28 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD - * -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt - * ed provided that the following conditions are met:1. Redistributions of source code must retain the - * above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b - * inary form must reproduce the above copyright notice, this list of conditions and the following disc - * laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam - * e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr - * oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE - * D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, - * BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA - * RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I - * NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO - * CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW - * EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP - * OSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. * * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:39 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:56 * from File 'nrf52.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -117,6 +130,7 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ diff --git a/mdk/nrf52805.h b/mdk/nrf52805.h index 32491bdc6..d19291bb9 100644 --- a/mdk/nrf52805.h +++ b/mdk/nrf52805.h @@ -1,41 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n * * @file nrf52805.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:36 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:52 * from File 'nrf52805.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -117,6 +117,7 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ diff --git a/mdk/nrf52805.svd b/mdk/nrf52805.svd index 153ace40a..34133c0eb 100644 --- a/mdk/nrf52805.svd +++ b/mdk/nrf52805.svd @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52805 + system_nrf52 NRF_ 2048 diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index 926c67a75..f437081f3 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -1,41 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n * * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:36 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:53 * from File 'nrf52810.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -120,6 +120,7 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ diff --git a/mdk/nrf52810.svd b/mdk/nrf52810.svd index cdd949c3e..64157c531 100644 --- a/mdk/nrf52810.svd +++ b/mdk/nrf52810.svd @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52810 + system_nrf52 NRF_ 2048 diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index ddf6187fb..5fcfeef2e 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -1,41 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n * * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:37 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:54 * from File 'nrf52811.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -120,6 +120,7 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ diff --git a/mdk/nrf52811.svd b/mdk/nrf52811.svd index 5862a4fd4..70a3d47b1 100644 --- a/mdk/nrf52811.svd +++ b/mdk/nrf52811.svd @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52811 + system_nrf52 NRF_ 2048 diff --git a/mdk/nrf52820.h b/mdk/nrf52820.h index 9b6a88643..9bedd926d 100644 --- a/mdk/nrf52820.h +++ b/mdk/nrf52820.h @@ -1,41 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n * * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:38 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:55 * from File 'nrf52820.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -119,6 +119,7 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ diff --git a/mdk/nrf52820.svd b/mdk/nrf52820.svd index 755bf4711..b5aebb1e5 100644 --- a/mdk/nrf52820.svd +++ b/mdk/nrf52820.svd @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52820 + system_nrf52 NRF_ 2048 diff --git a/mdk/nrf52833.h b/mdk/nrf52833.h index 902e2f070..ea03f8b78 100644 --- a/mdk/nrf52833.h +++ b/mdk/nrf52833.h @@ -1,41 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n * * @file nrf52833.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:41 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:57 * from File 'nrf52833.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -134,6 +134,7 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ diff --git a/mdk/nrf52833.svd b/mdk/nrf52833.svd index bacf9b180..79ddf77b8 100644 --- a/mdk/nrf52833.svd +++ b/mdk/nrf52833.svd @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52833 + system_nrf52 NRF_ 2048 diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index 02ffe70fa..48d1e7c14 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -1,41 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n * * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:43 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:59 * from File 'nrf52840.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -136,6 +136,7 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ diff --git a/mdk/nrf52840.svd b/mdk/nrf52840.svd index c0e7765c9..97a115337 100644 --- a/mdk/nrf52840.svd +++ b/mdk/nrf52840.svd @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52840 + system_nrf52 NRF_ 2048 diff --git a/mdk/nrf52_erratas.h b/mdk/nrf52_erratas.h index 90e381c1b..e809468db 100644 --- a/mdk/nrf52_erratas.h +++ b/mdk/nrf52_erratas.h @@ -230,6 +230,7 @@ static bool nrf52_configuration_255(void) __UNUSED; static bool nrf52_configuration_256(void) __UNUSED; static bool nrf52_configuration_257(void) __UNUSED; static bool nrf52_errata_258(void) __UNUSED; +static bool nrf52_errata_259(void) __UNUSED; static bool nrf52_errata_262(void) __UNUSED; /* ========= Errata 1 ========= */ @@ -13658,6 +13659,88 @@ static bool nrf52_errata_258(void) #endif } +/* ========= Errata 259 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_259_PRESENT 1 +#else + #define NRF52_ERRATA_259_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_259_ENABLE_WORKAROUND + #define NRF52_ERRATA_259_ENABLE_WORKAROUND NRF52_ERRATA_259_PRESENT +#endif + +static bool nrf52_errata_259(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + /* ========= Errata 262 ========= */ #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ diff --git a/mdk/nrf5340_application.h b/mdk/nrf5340_application.h index 0ccd5e73d..ffb4b5a83 100644 --- a/mdk/nrf5340_application.h +++ b/mdk/nrf5340_application.h @@ -1,28 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD - * -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt - * ed provided that the following conditions are met:1. Redistributions of source code must retain the - * above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b - * inary form must reproduce the above copyright notice, this list of conditions and the following disc - * laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam - * e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr - * oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE - * D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, - * BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA - * RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I - * NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO - * CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW - * EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP - * OSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. * * @file nrf5340_application.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:45 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:00 * from File 'nrf5340_application.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -122,6 +135,7 @@ typedef enum { /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ +#define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ diff --git a/mdk/nrf5340_application.svd b/mdk/nrf5340_application.svd index f220e43f6..7e1192d05 100644 --- a/mdk/nrf5340_application.svd +++ b/mdk/nrf5340_application.svd @@ -54,7 +54,7 @@ POSSIBILITY OF SUCH DAMAGE. 69 0 - system_nrf5340_application + system_nrf53 NRF_ 240 @@ -40335,7 +40335,7 @@ POSSIBILITY OF SUCH DAMAGE. SCKDELAY - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). + Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns). 0 7 @@ -40442,13 +40442,13 @@ POSSIBILITY OF SUCH DAMAGE. ENTER - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. + Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns 0 15 EXIT - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. + Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns. 16 31 diff --git a/mdk/nrf5340_application_bitfields.h b/mdk/nrf5340_application_bitfields.h index 27ac107ee..5202e3c0d 100644 --- a/mdk/nrf5340_application_bitfields.h +++ b/mdk/nrf5340_application_bitfields.h @@ -10555,7 +10555,7 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */ #define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */ -/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */ +/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns). */ #define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */ #define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */ @@ -10581,11 +10581,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_DPMDUR */ /* Description: Set the duration required to enter/exit deep power-down mode (DPM). */ -/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */ +/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns. */ #define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */ #define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */ -/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */ +/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns */ #define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */ #define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */ diff --git a/mdk/nrf5340_application_name_change.h b/mdk/nrf5340_application_name_change.h index 775ba6d3d..641bd4619 100644 --- a/mdk/nrf5340_application_name_change.h +++ b/mdk/nrf5340_application_name_change.h @@ -41,17 +41,23 @@ POSSIBILITY OF SUCH DAMAGE. * nrf5340_application_bitfields.h. The macros defined in this file were available previously. Do not use these * macros on purpose. Use the ones defined in nrf5340_application.h and nrf5340_application_bitfields.h instead. */ - + /* The serial box interrupt ISRs were renamed. Adding old names as macros. */ -#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SERIAL0_IRQHandler -#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn SERIAL0_IRQn -#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler SERIAL1_IRQHandler -#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn SERIAL1_IRQn -#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler SERIAL2_IRQHandler -#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn SERIAL2_IRQn -#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler SERIAL3_IRQHandler -#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn SERIAL3_IRQn - - /*lint --flb "Leave library region" */ +#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SERIAL0_IRQHandler +#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn SERIAL0_IRQn +#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler SERIAL1_IRQHandler +#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn SERIAL1_IRQn +#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler SERIAL2_IRQHandler +#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn SERIAL2_IRQn +#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler SERIAL3_IRQHandler +#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn SERIAL3_IRQn + +/* DPPI */ +#define DPPI_PRESENT DPPIC_PRESENT +#define DPPI_COUNT DPPIC_COUNT +#define DPPI_CH_NUM DPPIC_CH_NUM +#define DPPI_GROUP_NUM DPPIC_GROUP_NUM + +/*lint --flb "Leave library region" */ #endif /* NRF5340_APPLICATION_NAME_CHANGE_H */ diff --git a/mdk/nrf5340_application_peripherals.h b/mdk/nrf5340_application_peripherals.h index d5231fe9e..158d48246 100644 --- a/mdk/nrf5340_application_peripherals.h +++ b/mdk/nrf5340_application_peripherals.h @@ -107,11 +107,11 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_EASYDMA_MAXCNT_SIZE 9 /* Distributed Peripheral to Peripheral Interconnect */ -#define DPPI_PRESENT -#define DPPI_COUNT 1 +#define DPPIC_PRESENT +#define DPPIC_COUNT 1 -#define DPPI_CH_NUM 32 -#define DPPI_GROUP_NUM 6 +#define DPPIC_CH_NUM 32 +#define DPPIC_GROUP_NUM 6 /* Event Generator Unit */ #define EGU_PRESENT diff --git a/mdk/nrf5340_network.h b/mdk/nrf5340_network.h index 7acf5cf46..57718fde0 100644 --- a/mdk/nrf5340_network.h +++ b/mdk/nrf5340_network.h @@ -1,28 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD - * -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt - * ed provided that the following conditions are met:1. Redistributions of source code must retain the - * above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b - * inary form must reproduce the above copyright notice, this list of conditions and the following disc - * laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam - * e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr - * oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE - * D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, - * BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA - * RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I - * NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO - * CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW - * EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP - * OSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. * * @file nrf5340_network.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:54 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:09 * from File 'nrf5340_network.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -101,6 +114,7 @@ typedef enum { /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ +#define __INTERRUPTS_MAX 129 /*!< Top interrupt number */ #define __DSP_PRESENT 0 /*!< DSP present or not */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ diff --git a/mdk/nrf5340_network.svd b/mdk/nrf5340_network.svd index e3165502f..06f8e3bd1 100644 --- a/mdk/nrf5340_network.svd +++ b/mdk/nrf5340_network.svd @@ -54,7 +54,7 @@ POSSIBILITY OF SUCH DAMAGE. 30 0 - system_nrf5340_network + system_nrf53 NRF_ 129 diff --git a/mdk/nrf5340_network_name_change.h b/mdk/nrf5340_network_name_change.h index 963b01808..31303e43f 100644 --- a/mdk/nrf5340_network_name_change.h +++ b/mdk/nrf5340_network_name_change.h @@ -46,6 +46,12 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SERIAL0_IRQHandler #define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn SERIAL0_IRQn + /* DPPI */ +#define DPPI_PRESENT DPPIC_PRESENT +#define DPPI_COUNT DPPIC_COUNT +#define DPPI_CH_NUM DPPIC_CH_NUM +#define DPPI_GROUP_NUM DPPIC_GROUP_NUM + /*lint --flb "Leave library region" */ #endif /* NRF5340_NETWORK_NAME_CHANGE_H */ diff --git a/mdk/nrf5340_network_peripherals.h b/mdk/nrf5340_network_peripherals.h index ad7e92c4f..18165cb20 100644 --- a/mdk/nrf5340_network_peripherals.h +++ b/mdk/nrf5340_network_peripherals.h @@ -112,11 +112,11 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_COUNT 1 /* Distributed Peripheral to Peripheral Interconnect */ -#define DPPI_PRESENT -#define DPPI_COUNT 1 +#define DPPIC_PRESENT +#define DPPIC_COUNT 1 -#define DPPI_CH_NUM 32 -#define DPPI_GROUP_NUM 6 +#define DPPIC_CH_NUM 32 +#define DPPIC_GROUP_NUM 6 /* Event Generator Unit */ #define EGU_PRESENT diff --git a/mdk/nrf53_erratas.h b/mdk/nrf53_erratas.h index 920922c43..e910757ff 100644 --- a/mdk/nrf53_erratas.h +++ b/mdk/nrf53_erratas.h @@ -139,6 +139,9 @@ static bool nrf53_errata_136(void) __UNUSED; static bool nrf53_errata_137(void) __UNUSED; static bool nrf53_errata_138(void) __UNUSED; static bool nrf53_errata_140(void) __UNUSED; +static bool nrf53_errata_152(void) __UNUSED; +static bool nrf53_errata_153(void) __UNUSED; +static bool nrf53_errata_154(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -5178,7 +5181,15 @@ static bool nrf53_errata_122(void) } /* ========= Errata 133 ========= */ -#define NRF53_ERRATA_133_PRESENT 0 +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_133_PRESENT 1 + #else + #define NRF53_ERRATA_133_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_133_PRESENT 0 +#endif #ifndef NRF53_ERRATA_133_ENABLE_WORKAROUND #define NRF53_ERRATA_133_ENABLE_WORKAROUND NRF53_ERRATA_133_PRESENT @@ -5189,12 +5200,51 @@ static bool nrf53_errata_133(void) #ifndef NRF53_SERIES return false; #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif return false; #endif } /* ========= Errata 134 ========= */ -#define NRF53_ERRATA_134_PRESENT 0 +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_134_PRESENT 1 + #else + #define NRF53_ERRATA_134_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_134_PRESENT 0 +#endif #ifndef NRF53_ERRATA_134_ENABLE_WORKAROUND #define NRF53_ERRATA_134_ENABLE_WORKAROUND NRF53_ERRATA_134_PRESENT @@ -5205,12 +5255,47 @@ static bool nrf53_errata_134(void) #ifndef NRF53_SERIES return false; #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif return false; #endif } /* ========= Errata 135 ========= */ -#define NRF53_ERRATA_135_PRESENT 0 +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_135_PRESENT 1 + #else + #define NRF53_ERRATA_135_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_135_PRESENT 0 +#endif #ifndef NRF53_ERRATA_135_ENABLE_WORKAROUND #define NRF53_ERRATA_135_ENABLE_WORKAROUND NRF53_ERRATA_135_PRESENT @@ -5221,12 +5306,55 @@ static bool nrf53_errata_135(void) #ifndef NRF53_SERIES return false; #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif return false; #endif } /* ========= Errata 136 ========= */ -#define NRF53_ERRATA_136_PRESENT 0 +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_136_PRESENT 1 + #else + #define NRF53_ERRATA_136_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_136_PRESENT 0 +#endif #ifndef NRF53_ERRATA_136_ENABLE_WORKAROUND #define NRF53_ERRATA_136_ENABLE_WORKAROUND NRF53_ERRATA_136_PRESENT @@ -5237,12 +5365,52 @@ static bool nrf53_errata_136(void) #ifndef NRF53_SERIES return false; #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif return false; #endif } /* ========= Errata 137 ========= */ -#define NRF53_ERRATA_137_PRESENT 0 +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_137_PRESENT 1 + #else + #define NRF53_ERRATA_137_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_137_PRESENT 0 +#endif #ifndef NRF53_ERRATA_137_ENABLE_WORKAROUND #define NRF53_ERRATA_137_ENABLE_WORKAROUND NRF53_ERRATA_137_PRESENT @@ -5253,12 +5421,55 @@ static bool nrf53_errata_137(void) #ifndef NRF53_SERIES return false; #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif return false; #endif } /* ========= Errata 138 ========= */ -#define NRF53_ERRATA_138_PRESENT 0 +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_138_PRESENT 1 + #else + #define NRF53_ERRATA_138_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_138_PRESENT 0 +#endif #ifndef NRF53_ERRATA_138_ENABLE_WORKAROUND #define NRF53_ERRATA_138_ENABLE_WORKAROUND NRF53_ERRATA_138_PRESENT @@ -5269,6 +5480,37 @@ static bool nrf53_errata_138(void) #ifndef NRF53_SERIES return false; #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif return false; #endif } @@ -5328,4 +5570,179 @@ static bool nrf53_errata_140(void) #endif } +/* ========= Errata 152 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_152_PRESENT 1 + #else + #define NRF53_ERRATA_152_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_152_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_152_ENABLE_WORKAROUND + #define NRF53_ERRATA_152_ENABLE_WORKAROUND NRF53_ERRATA_152_PRESENT +#endif + +static bool nrf53_errata_152(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 153 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_153_PRESENT 1 + #else + #define NRF53_ERRATA_153_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_153_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_153_ENABLE_WORKAROUND + #define NRF53_ERRATA_153_ENABLE_WORKAROUND NRF53_ERRATA_153_PRESENT +#endif + +static bool nrf53_errata_153(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 154 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_154_PRESENT 1 + #else + #define NRF53_ERRATA_154_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_154_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_154_ENABLE_WORKAROUND + #define NRF53_ERRATA_154_ENABLE_WORKAROUND NRF53_ERRATA_154_PRESENT +#endif + +static bool nrf53_errata_154(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + #endif /* NRF53_ERRATAS_H */ diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index d429bf257..d37082a6d 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -1,41 +1,41 @@ /* - * Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. * * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 11. May 2022 - * @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:55 + * @date 19. October 2022 + * @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:10 * from File 'nrf9160.svd', - * last modified on Wednesday, 11.05.2022 10:25:34 + * last modified on Wednesday, 19.10.2022 09:13:55 */ @@ -86,10 +86,10 @@ typedef enum { /* ========================================== nrf9160 Specific Interrupt Numbers =========================================== */ SPU_IRQn = 3, /*!< 3 SPU */ CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn= 8, /*!< 8 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 */ - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn= 9, /*!< 9 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 */ - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn= 10, /*!< 10 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 */ - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn= 11, /*!< 11 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 */ + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */ + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */ + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */ GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ SAADC_IRQn = 14, /*!< 14 SAADC */ TIMER0_IRQn = 15, /*!< 15 TIMER0 */ @@ -125,6 +125,7 @@ typedef enum { /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ +#define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ #define __DSP_PRESENT 1 /*!< DSP present or not */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ @@ -161,16 +162,25 @@ typedef enum { */ +/** + * @brief FICR_SIPINFO [SIPINFO] (SIP-specific device info) + */ +typedef struct { + __IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */ + __IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) Description collection: SIP hardware revision, + encoded in ASCII, ex B0A or B1A */ + __IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded + in ASCII, ex SIAA, SIBA or SICA */ +} FICR_SIPINFO_Type; /*!< Size = 12 (0xc) */ + + /** * @brief FICR_INFO [INFO] (Device info) */ typedef struct { __IM uint32_t RESERVED; __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ - __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ - __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production - configuration */ - __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ + __IM uint32_t RESERVED1[3]; __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ @@ -210,11 +220,11 @@ typedef struct { __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 ) will be pushed by KMU. Note that this - address MUST match that of a peripherals + address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially - read! */ + read. */ __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */ @@ -243,11 +253,11 @@ typedef struct { * @brief TAD_PSEL [PSEL] (Unspecified) */ typedef struct { - __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin number configuration for TRACECLK */ - __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin number configuration for TRACEDATA[0] */ - __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin number configuration for TRACEDATA[1] */ - __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin number configuration for TRACEDATA[2] */ - __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin number configuration for TRACEDATA[3] */ + __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ + __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ + __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ + __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ + __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ @@ -335,17 +345,28 @@ typedef struct { } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ +/** + * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem) + */ +typedef struct { + __IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */ + __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */ +} POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */ + + /** * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) */ typedef struct { - __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */ - __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger - to the CPU has been read */ + __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ + __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if + data sent from the debugger to the CPU has + been read. */ __IM uint32_t RESERVED[30]; - __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */ - __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU - to the debugger has been read */ + __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ + __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if + the data sent from the CPU to the debugger + has been read. */ } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ @@ -353,9 +374,10 @@ typedef struct { * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) */ typedef struct { - __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register ERASEPROTECT.DISABLE from being - written until next reset */ - __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable ERASEPROTECT and perform ERASEALL */ + __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE + register from being written until next reset. */ + __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register + and performs an ERASEALL operation. */ } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ @@ -719,11 +741,13 @@ typedef struct { */ typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ - __IM uint32_t RESERVED[128]; + __IM uint32_t RESERVED[80]; + __IOM FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000140) SIP-specific device info */ + __IM uint32_t RESERVED1[45]; __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ - __IM uint32_t RESERVED1[53]; + __IM uint32_t RESERVED2[53]; __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ - __IM uint32_t RESERVED2[64]; + __IM uint32_t RESERVED3[64]; __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ @@ -745,7 +769,10 @@ typedef struct { /*!< (@ 0x00FF8000) UICR_S Struc __IM uint32_t RESERVED1; __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ - __IM uint32_t RESERVED2[2]; + __IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE + for Application NVM in POFWARN condition + . */ + __IM uint32_t RESERVED2; __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ __IM uint32_t RESERVED3[53]; @@ -766,12 +793,13 @@ typedef struct { /*!< (@ 0x00FF8000) UICR_S Struc */ typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ - __OM uint32_t CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */ - __OM uint32_t CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */ + __OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */ + __OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */ __IM uint32_t RESERVED[318]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ - __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface */ + __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface + Reset behavior is the same as debug components */ } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ @@ -835,7 +863,9 @@ typedef struct { /*!< (@ 0x50003000) SPU_S Struct typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ __IM uint32_t RESERVED[320]; __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ - __IM uint32_t RESERVED1[29]; + __IM uint32_t RESERVED1[4]; + __IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */ + __IM uint32_t RESERVED2[24]; __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */ } NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ @@ -931,7 +961,9 @@ typedef struct { /*!< (@ 0x40005000) POWER_NS Str __IM uint32_t RESERVED9[54]; __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention register */ -} NRF_POWER_Type; /*!< Size = 1316 (0x524) */ + __IM uint32_t RESERVED10[59]; + __IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */ +} NRF_POWER_Type; /*!< Size = 1560 (0x618) */ @@ -1289,8 +1321,8 @@ typedef struct { /*!< (@ 0x40008000) UARTE0_NS St __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED17[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ __IM uint32_t RESERVED18[31]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ __IM uint32_t RESERVED19; @@ -1351,7 +1383,7 @@ typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S St __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED7[129]; __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], - SET[n] and CLR[n] tasks and IN[n] event */ + SET[n], and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ @@ -1527,7 +1559,7 @@ typedef struct { /*!< (@ 0x40014000) RTC0_NS Stru /** - * @brief Distributed Programmable Peripheral Interconnect Controller 0 (DPPIC_NS) + * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS) */ typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ @@ -1540,8 +1572,9 @@ typedef struct { /*!< (@ 0x40017000) DPPIC_NS Str __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ __IM uint32_t RESERVED2[189]; __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: - Writes to this register is ignored if either - SUBSCRIBE_CHG[n].EN/DIS are enabled. */ + Writes to this register are ignored if either + SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS + is enabled */ } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ @@ -1785,18 +1818,18 @@ typedef struct { /*!< (@ 0x40028000) I2S_NS Struc /** - * @brief Inter Processor Communication 0 (IPC_NS) + * @brief Interprocessor communication 0 (IPC_NS) */ typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ - __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on channel - enabled in SEND_CNF[n]. */ + __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC + channel enabled in SEND_CNF[n] */ __IM uint32_t RESERVED[24]; __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration for task SEND[n] */ __IM uint32_t RESERVED1[24]; __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one - or more of the enabled channels in RECEIVE_CNF[n]. */ + or more of the enabled IPC channels in RECEIVE_CNF[n] */ __IM uint32_t RESERVED2[24]; __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration for event RECEIVE[n] */ @@ -1807,12 +1840,12 @@ typedef struct { /*!< (@ 0x4002A000) IPC_NS Struc __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ __IM uint32_t RESERVED4[128]; __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration - for TASKS_SEND[n]. */ + for TASKS_SEND[n] */ __IM uint32_t RESERVED5[24]; __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration - for EVENTS_RECEIVE[n]. */ + for EVENTS_RECEIVE[n] */ __IM uint32_t RESERVED6[24]; - __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory. */ + __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */ } NRF_IPC_Type; /*!< Size = 1568 (0x620) */ diff --git a/mdk/nrf9160.svd b/mdk/nrf9160.svd index c45e7dff4..faea2831e 100644 --- a/mdk/nrf9160.svd +++ b/mdk/nrf9160.svd @@ -6,43 +6,44 @@ nrf9160 nrf91 1 - nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller + nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller -Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n -\n -SPDX-License-Identifier: BSD-3-Clause\n -\n -Redistribution and use in source and binary forms, with or without\n -modification, are permitted provided that the following conditions are met:\n -\n -1. Redistributions of source code must retain the above copyright notice, this\n - list of conditions and the following disclaimer.\n -\n -2. Redistributions in binary form must reproduce the above copyright\n - notice, this list of conditions and the following disclaimer in the\n - documentation and/or other materials provided with the distribution.\n -\n -3. Neither the name of Nordic Semiconductor ASA nor the names of its\n - contributors may be used to endorse or promote products derived from this\n - software without specific prior written permission.\n -\n -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n -POSSIBILITY OF SUCH DAMAGE.\n - +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + 8 32 32 0x00000000 0xFFFFFFFF + NRF_ CM33 r0p4 @@ -54,8 +55,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 69 0 - system_nrf9160 - NRF_ + system_nrf91 240 @@ -76,96 +76,89 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x20 - INFO - Device info - FICR_INFO + SIPINFO + SIP-specific device info + FICR_SIPINFO read-write - 0x200 + 0x140 - 0x2 - 0x4 - DEVICEID[%s] - Description collection: Device identifier - 0x004 + PARTNO + SIP part number + 0x000 read-only 0xFFFFFFFF - DEVICEID - 64 bit unique device identifier + PARTNO 0 31 + + + 9160 + Device is an nRF9160 sip + 0x00009160 + + - PART - Part code - 0x00C + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 read-only - 0x00009160 + 0x000000FF + uint8_t + 0x8 - PART - Part code + HWREVISION 0 - 31 - - - N9160 - nRF9160 - 0x9160 - - + 7 - VARIANT - Part Variant, Hardware version and Production configuration - 0x010 + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 read-only - 0x0FFFFFFF + 0x000000FF + uint8_t + 0x8 VARIANT - Part Variant, Hardware version and Production configuration, encoded as ASCII 0 - 31 - - - AAAA - AAAA - 0x41414141 - - - AAA0 - AAA0 - 0x41414130 - - + 7 + + + INFO + Device info + FICR_INFO + read-write + 0x200 - PACKAGE - Package option - 0x014 + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x004 read-only - 0x00002000 + 0xFFFFFFFF - PACKAGE - Package option + DEVICEID + 64 bit unique device identifier 0 31 - - - CC - CCxx - 236 ball wlCSP - 0x2000 - - @@ -371,7 +364,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Amount of bytes for the startup tests 0x00C read-only - 0x00000210 + 0xFFFFFFFF STARTUP @@ -556,6 +549,33 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPNVMCPOFGUARD + Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . + 0x024 + read-write + 0xFFFFFFFF + + + NVMCPOFGUARDEN + Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition + 0 + 0 + + + Disabled + NVM WRITE and NVM ERASE are not blocked in POFWARN condition + 0 + + + Enabled + NVM WRITE and NVM ERASE are blocked in POFWARN condition + 1 + + + + + SECUREAPPROTECT Secure access port protection @@ -653,9 +673,9 @@ POSSIBILITY OF SUCH DAMAGE.\n DEST Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) - will be pushed by KMU. Note that this address MUST match that of a peripherals + will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into - an address range which the CPU can potentially read! + an address range which the CPU can potentially read. 0x000 read-write 0xFFFFFFFF @@ -795,19 +815,20 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x20 - CLOCKSTART + TASKS_CLOCKSTART Start all trace and debug clocks. 0x000 write-only - START + TASKS_CLOCKSTART + Start all trace and debug clocks. 0 0 - Start - Start all trace and debug clocks. + Trigger + Trigger task 1 @@ -815,19 +836,20 @@ POSSIBILITY OF SUCH DAMAGE.\n - CLOCKSTOP + TASKS_CLOCKSTOP Stop all trace and debug clocks. 0x004 write-only - STOP + TASKS_CLOCKSTOP + Stop all trace and debug clocks. 0 0 - Stop - Stop all trace and debug clocks. + Trigger + Trigger task 1 @@ -867,7 +889,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x504 TRACECLK - Pin number configuration for TRACECLK + Pin configuration for TRACECLK 0x000 read-write 0xFFFFFFFF @@ -877,6 +899,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Traceclk + TRACECLK pin + 21 + + CONNECT @@ -900,7 +929,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEDATA0 - Pin number configuration for TRACEDATA[0] + Pin configuration for TRACEDATA[0] 0x004 read-write 0xFFFFFFFF @@ -910,6 +939,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Tracedata0 + TRACEDATA0 pin + 22 + + CONNECT @@ -933,7 +969,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEDATA1 - Pin number configuration for TRACEDATA[1] + Pin configuration for TRACEDATA[1] 0x008 read-write 0xFFFFFFFF @@ -943,6 +979,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Tracedata1 + TRACEDATA1 pin + 23 + + CONNECT @@ -966,7 +1009,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEDATA2 - Pin number configuration for TRACEDATA[2] + Pin configuration for TRACEDATA[2] 0x00C read-write 0xFFFFFFFF @@ -976,6 +1019,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Tracedata2 + TRACEDATA2 pin + 24 + + CONNECT @@ -999,7 +1049,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEDATA3 - Pin number configuration for TRACEDATA[3] + Pin configuration for TRACEDATA[3] 0x010 read-write 0xFFFFFFFF @@ -1009,6 +1059,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Tracedata3 + TRACEDATA3 pin + 25 + + CONNECT @@ -1033,35 +1090,35 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEPORTSPEED - Clocking options for the Trace Port debug interface + Clocking options for the Trace Port debug interface Reset behavior is the same as debug components 0x518 read-write 0x00000000 TRACEPORTSPEED - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. + Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. 0 1 32MHz - 32 MHz Trace Port clock (TRACECLK = 16 MHz) + Trace Port clock is: 32MHz 0 16MHz - 16 MHz Trace Port clock (TRACECLK = 8 MHz) + Trace Port clock is: 16MHz 1 8MHz - 8 MHz Trace Port clock (TRACECLK = 4 MHz) + Trace Port clock is: 8MHz 2 4MHz - 4 MHz Trace Port clock (TRACECLK = 2 MHz) + Trace Port clock is: 4MHz 3 @@ -1175,9 +1232,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RAMACCERR will publish to. + DPPI channel that event RAMACCERR will publish to 0 - 3 + 7 EN @@ -1206,9 +1263,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event FLASHACCERR will publish to. + DPPI channel that event FLASHACCERR will publish to 0 - 3 + 7 EN @@ -1237,9 +1294,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event PERIPHACCERR will publish to. + DPPI channel that event PERIPHACCERR will publish to 0 - 3 + 7 EN @@ -1544,9 +1601,10 @@ POSSIBILITY OF SUCH DAMAGE.\n SECUREMAPPING - Define configuration capabilities for TrustZone Cortex-M secure attribute + Define configuration capabilities for TrustZone Cortex-M secure attribute 0 1 + read-only NonSecure @@ -2694,7 +2752,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION Region number 0 - 3 + 4 LOCK @@ -3190,6 +3248,32 @@ POSSIBILITY OF SUCH DAMAGE.\n + + EXTPOFCON + External power failure warning configuration + 0x514 + read-write + + + POF + Enable or disable external power failure warning + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DCDCEN Enable DC/DC mode of the main voltage regulator. @@ -3336,9 +3420,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task HFCLKSTART will subscribe to + DPPI channel that task HFCLKSTART will subscribe to 0 - 3 + 7 EN @@ -3367,9 +3451,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task HFCLKSTOP will subscribe to + DPPI channel that task HFCLKSTOP will subscribe to 0 - 3 + 7 EN @@ -3398,9 +3482,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task LFCLKSTART will subscribe to + DPPI channel that task LFCLKSTART will subscribe to 0 - 3 + 7 EN @@ -3429,9 +3513,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task LFCLKSTOP will subscribe to + DPPI channel that task LFCLKSTOP will subscribe to 0 - 3 + 7 EN @@ -3512,9 +3596,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event HFCLKSTARTED will publish to. + DPPI channel that event HFCLKSTARTED will publish to 0 - 3 + 7 EN @@ -3543,9 +3627,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event LFCLKSTARTED will publish to. + DPPI channel that event LFCLKSTARTED will publish to 0 - 3 + 7 EN @@ -3818,6 +3902,11 @@ POSSIBILITY OF SUCH DAMAGE.\n 0 0 + + HFINT + HFINT - 64 MHz on-chip oscillator + 0 + HFXO HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator @@ -4056,9 +4145,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CONSTLAT will subscribe to + DPPI channel that task CONSTLAT will subscribe to 0 - 3 + 7 EN @@ -4087,9 +4176,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task LOWPWR will subscribe to + DPPI channel that task LOWPWR will subscribe to 0 - 3 + 7 EN @@ -4196,9 +4285,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event POFWARN will publish to. + DPPI channel that event POFWARN will publish to 0 - 3 + 7 EN @@ -4227,9 +4316,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SLEEPENTER will publish to. + DPPI channel that event SLEEPENTER will publish to 0 - 3 + 7 EN @@ -4258,9 +4347,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SLEEPEXIT will publish to. + DPPI channel that event SLEEPEXIT will publish to 0 - 3 + 7 EN @@ -4697,6 +4786,67 @@ POSSIBILITY OF SUCH DAMAGE.\n + + LTEMODEM + LTE Modem + POWER_LTEMODEM + read-write + 0x610 + + STARTN + Start LTE modem + 0x000 + read-write + 0x00000001 + + + STARTN + Start LTE modem + 0 + 0 + + + Start + Start LTE modem + 0 + + + Hold + Hold LTE modem disabled + 1 + + + + + + + FORCEOFF + Force off LTE modem + 0x004 + read-write + 0x00000000 + + + FORCEOFF + Force off LTE modem + 0 + 0 + + + Release + Release force off + 0 + + + Hold + Hold force off active + 1 + + + + + + @@ -4745,7 +4895,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x400 RXDATA - Data sent from the debugger to the CPU + Data sent from the debugger to the CPU. 0x000 read-only 0x00000000 @@ -4760,7 +4910,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXSTATUS - Status to indicate if data sent from the debugger to the CPU has been read + This register shows a status that indicates if data sent from the debugger to the CPU has been read. 0x004 read-only 0x00000000 @@ -4787,7 +4937,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXDATA - Data sent from the CPU to the debugger + Data sent from the CPU to the debugger. 0x80 read-write 0x00000000 @@ -4802,7 +4952,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTATUS - Status to indicate if data sent from the CPU to the debugger has been read + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. 0x84 read-only 0x00000000 @@ -4836,14 +4986,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x500 LOCK - Lock register ERASEPROTECT.DISABLE from being written until next reset + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. 0x000 read-writeonce 0x00000000 LOCK - Lock register ERASEPROTECT.DISABLE from being written until next reset + Lock ERASEPROTECT.DISABLE register from being written until next reset 0 0 @@ -4863,14 +5013,14 @@ POSSIBILITY OF SUCH DAMAGE.\n DISABLE - Disable ERASEPROTECT and perform ERASEALL + This register disables the ERASEPROTECT register and performs an ERASEALL operation. 0x004 read-write 0x00000000 KEY - The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. 0 31 @@ -4892,7 +5042,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 SPIM @@ -4990,9 +5140,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -5021,9 +5171,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -5052,9 +5202,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 - 3 + 7 EN @@ -5083,9 +5233,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 - 3 + 7 EN @@ -5244,9 +5394,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -5275,9 +5425,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to 0 - 3 + 7 EN @@ -5306,9 +5456,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to 0 - 3 + 7 EN @@ -5337,9 +5487,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDTX will publish to. + DPPI channel that event ENDTX will publish to 0 - 3 + 7 EN @@ -5368,9 +5518,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STARTED will publish to. + DPPI channel that event STARTED will publish to 0 - 3 + 7 EN @@ -6129,7 +6279,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 SPIS @@ -6185,9 +6335,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task ACQUIRE will subscribe to + DPPI channel that task ACQUIRE will subscribe to 0 - 3 + 7 EN @@ -6216,9 +6366,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task RELEASE will subscribe to + DPPI channel that task RELEASE will subscribe to 0 - 3 + 7 EN @@ -6325,9 +6475,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to 0 - 3 + 7 EN @@ -6356,9 +6506,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to 0 - 3 + 7 EN @@ -6387,9 +6537,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ACQUIRED will publish to. + DPPI channel that event ACQUIRED will publish to 0 - 3 + 7 EN @@ -7134,7 +7284,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 TWIM @@ -7253,9 +7403,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STARTRX will subscribe to + DPPI channel that task STARTRX will subscribe to 0 - 3 + 7 EN @@ -7284,9 +7434,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STARTTX will subscribe to + DPPI channel that task STARTTX will subscribe to 0 - 3 + 7 EN @@ -7315,9 +7465,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -7346,9 +7496,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 - 3 + 7 EN @@ -7377,9 +7527,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 - 3 + 7 EN @@ -7590,9 +7740,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -7621,9 +7771,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to 0 - 3 + 7 EN @@ -7652,9 +7802,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SUSPENDED will publish to. + DPPI channel that event SUSPENDED will publish to 0 - 3 + 7 EN @@ -7683,9 +7833,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to 0 - 3 + 7 EN @@ -7714,9 +7864,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to 0 - 3 + 7 EN @@ -7745,9 +7895,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event LASTRX will publish to. + DPPI channel that event LASTRX will publish to 0 - 3 + 7 EN @@ -7776,9 +7926,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event LASTTX will publish to. + DPPI channel that event LASTTX will publish to 0 - 3 + 7 EN @@ -8817,7 +8967,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 TWIS @@ -8936,9 +9086,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -8967,9 +9117,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 - 3 + 7 EN @@ -8998,9 +9148,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 - 3 + 7 EN @@ -9029,9 +9179,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task PREPARERX will subscribe to + DPPI channel that task PREPARERX will subscribe to 0 - 3 + 7 EN @@ -9060,9 +9210,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task PREPARETX will subscribe to + DPPI channel that task PREPARETX will subscribe to 0 - 3 + 7 EN @@ -9247,9 +9397,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -9278,9 +9428,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to 0 - 3 + 7 EN @@ -9309,9 +9459,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to 0 - 3 + 7 EN @@ -9340,9 +9490,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to 0 - 3 + 7 EN @@ -9371,9 +9521,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event WRITE will publish to. + DPPI channel that event WRITE will publish to 0 - 3 + 7 EN @@ -9402,9 +9552,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event READ will publish to. + DPPI channel that event READ will publish to 0 - 3 + 7 EN @@ -9996,7 +10146,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -10342,7 +10492,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 UARTE @@ -10461,9 +10611,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STARTRX will subscribe to + DPPI channel that task STARTRX will subscribe to 0 - 3 + 7 EN @@ -10492,9 +10642,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOPRX will subscribe to + DPPI channel that task STOPRX will subscribe to 0 - 3 + 7 EN @@ -10523,9 +10673,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STARTTX will subscribe to + DPPI channel that task STARTTX will subscribe to 0 - 3 + 7 EN @@ -10554,9 +10704,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOPTX will subscribe to + DPPI channel that task STOPTX will subscribe to 0 - 3 + 7 EN @@ -10585,9 +10735,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task FLUSHRX will subscribe to + DPPI channel that task FLUSHRX will subscribe to 0 - 3 + 7 EN @@ -10902,9 +11052,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event CTS will publish to. + DPPI channel that event CTS will publish to 0 - 3 + 7 EN @@ -10933,9 +11083,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event NCTS will publish to. + DPPI channel that event NCTS will publish to 0 - 3 + 7 EN @@ -10964,9 +11114,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXDRDY will publish to. + DPPI channel that event RXDRDY will publish to 0 - 3 + 7 EN @@ -10995,9 +11145,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to 0 - 3 + 7 EN @@ -11026,9 +11176,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXDRDY will publish to. + DPPI channel that event TXDRDY will publish to 0 - 3 + 7 EN @@ -11057,9 +11207,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDTX will publish to. + DPPI channel that event ENDTX will publish to 0 - 3 + 7 EN @@ -11088,9 +11238,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to 0 - 3 + 7 EN @@ -11119,9 +11269,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXTO will publish to. + DPPI channel that event RXTO will publish to 0 - 3 + 7 EN @@ -11150,9 +11300,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to 0 - 3 + 7 EN @@ -11181,9 +11331,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to 0 - 3 + 7 EN @@ -11212,9 +11362,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXSTOPPED will publish to. + DPPI channel that event TXSTOPPED will publish to 0 - 3 + 7 EN @@ -12097,7 +12247,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORSRC - Error source Note : this register is read / write one to clear. + Error source This register is read/write one to clear. 0x480 read-write oneToClear @@ -12445,7 +12595,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -12621,7 +12771,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12633,7 +12783,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12645,7 +12795,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12657,7 +12807,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12669,7 +12819,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12680,7 +12830,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12692,7 +12842,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12704,7 +12854,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12716,7 +12866,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12728,7 +12878,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12739,7 +12889,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12751,7 +12901,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12763,7 +12913,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12775,7 +12925,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12787,7 +12937,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12798,7 +12948,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12810,7 +12960,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12822,7 +12972,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12834,7 +12984,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12846,7 +12996,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12857,7 +13007,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12869,7 +13019,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12881,7 +13031,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12893,7 +13043,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12905,7 +13055,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12916,7 +13066,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12928,7 +13078,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12940,7 +13090,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12952,7 +13102,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12964,7 +13114,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12975,7 +13125,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12987,7 +13137,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12999,7 +13149,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -13011,7 +13161,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -13023,7 +13173,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -13125,9 +13275,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task OUT[n] will subscribe to + DPPI channel that task OUT[n] will subscribe to 0 - 3 + 7 EN @@ -13158,9 +13308,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SET[n] will subscribe to + DPPI channel that task SET[n] will subscribe to 0 - 3 + 7 EN @@ -13191,9 +13341,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CLR[n] will subscribe to + DPPI channel that task CLR[n] will subscribe to 0 - 3 + 7 EN @@ -13278,9 +13428,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event IN[n] will publish to. + DPPI channel that event IN[n] will publish to 0 - 3 + 7 EN @@ -13309,9 +13459,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event PORT will publish to. + DPPI channel that event PORT will publish to 0 - 3 + 7 EN @@ -13838,7 +13988,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 CONFIG[%s] - Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event 0x510 read-write @@ -13867,7 +14017,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PSEL - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event 8 12 @@ -14032,9 +14182,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -14063,9 +14213,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SAMPLE will subscribe to + DPPI channel that task SAMPLE will subscribe to 0 - 3 + 7 EN @@ -14094,9 +14244,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -14125,9 +14275,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CALIBRATEOFFSET will subscribe to + DPPI channel that task CALIBRATEOFFSET will subscribe to 0 - 3 + 7 EN @@ -14373,9 +14523,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STARTED will publish to. + DPPI channel that event STARTED will publish to 0 - 3 + 7 EN @@ -14404,9 +14554,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to 0 - 3 + 7 EN @@ -14435,9 +14585,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event DONE will publish to. + DPPI channel that event DONE will publish to 0 - 3 + 7 EN @@ -14466,9 +14616,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RESULTDONE will publish to. + DPPI channel that event RESULTDONE will publish to 0 - 3 + 7 EN @@ -14497,9 +14647,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event CALIBRATEDONE will publish to. + DPPI channel that event CALIBRATEDONE will publish to 0 - 3 + 7 EN @@ -14528,9 +14678,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -14567,9 +14717,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event CH[n].LIMITH will publish to. + DPPI channel that event CH[n].LIMITH will publish to 0 - 3 + 7 EN @@ -14598,9 +14748,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event CH[n].LIMITL will publish to. + DPPI channel that event CH[n].LIMITL will publish to 0 - 3 + 7 EN @@ -16998,9 +17148,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -17029,9 +17179,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -17060,9 +17210,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task COUNT will subscribe to + DPPI channel that task COUNT will subscribe to 0 - 3 + 7 EN @@ -17091,9 +17241,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CLEAR will subscribe to + DPPI channel that task CLEAR will subscribe to 0 - 3 + 7 EN @@ -17122,9 +17272,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SHUTDOWN will subscribe to + DPPI channel that task SHUTDOWN will subscribe to 0 - 3 + 7 EN @@ -17155,9 +17305,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CAPTURE[n] will subscribe to + DPPI channel that task CAPTURE[n] will subscribe to 0 - 3 + 7 EN @@ -17216,9 +17366,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event COMPARE[n] will publish to. + DPPI channel that event COMPARE[n] will publish to 0 - 3 + 7 EN @@ -18097,9 +18247,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -18128,9 +18278,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -18159,9 +18309,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CLEAR will subscribe to + DPPI channel that task CLEAR will subscribe to 0 - 3 + 7 EN @@ -18190,9 +18340,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task TRIGOVRFLW will subscribe to + DPPI channel that task TRIGOVRFLW will subscribe to 0 - 3 + 7 EN @@ -18301,9 +18451,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TICK will publish to. + DPPI channel that event TICK will publish to 0 - 3 + 7 EN @@ -18332,9 +18482,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event OVRFLW will publish to. + DPPI channel that event OVRFLW will publish to 0 - 3 + 7 EN @@ -18365,9 +18515,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event COMPARE[n] will publish to. + DPPI channel that event COMPARE[n] will publish to 0 - 3 + 7 EN @@ -18747,7 +18897,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18765,7 +18915,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18783,7 +18933,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18801,7 +18951,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18819,7 +18969,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18837,7 +18987,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -19265,7 +19415,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DPPIC_NS - Distributed Programmable Peripheral Interconnect Controller 0 + Distributed programmable peripheral interconnect controller 0 0x40017000 DPPIC @@ -19345,9 +19495,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CHG[n].EN will subscribe to + DPPI channel that task CHG[n].EN will subscribe to 0 - 3 + 7 EN @@ -19376,9 +19526,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CHG[n].DIS will subscribe to + DPPI channel that task CHG[n].DIS will subscribe to 0 - 3 + 7 EN @@ -19705,19 +19855,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable set register. Writing '0' has no effect + Channel 0 enable set register. Writing 0 has no effect. 0 0 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19732,19 +19882,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable set register. Writing '0' has no effect + Channel 1 enable set register. Writing 0 has no effect. 1 1 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19759,19 +19909,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable set register. Writing '0' has no effect + Channel 2 enable set register. Writing 0 has no effect. 2 2 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19786,19 +19936,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable set register. Writing '0' has no effect + Channel 3 enable set register. Writing 0 has no effect. 3 3 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19813,19 +19963,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable set register. Writing '0' has no effect + Channel 4 enable set register. Writing 0 has no effect. 4 4 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19840,19 +19990,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable set register. Writing '0' has no effect + Channel 5 enable set register. Writing 0 has no effect. 5 5 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19867,19 +20017,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable set register. Writing '0' has no effect + Channel 6 enable set register. Writing 0 has no effect. 6 6 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19894,19 +20044,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable set register. Writing '0' has no effect + Channel 7 enable set register. Writing 0 has no effect. 7 7 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19921,19 +20071,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable set register. Writing '0' has no effect + Channel 8 enable set register. Writing 0 has no effect. 8 8 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19948,19 +20098,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable set register. Writing '0' has no effect + Channel 9 enable set register. Writing 0 has no effect. 9 9 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19975,19 +20125,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable set register. Writing '0' has no effect + Channel 10 enable set register. Writing 0 has no effect. 10 10 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20002,19 +20152,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable set register. Writing '0' has no effect + Channel 11 enable set register. Writing 0 has no effect. 11 11 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20029,19 +20179,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable set register. Writing '0' has no effect + Channel 12 enable set register. Writing 0 has no effect. 12 12 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20056,19 +20206,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable set register. Writing '0' has no effect + Channel 13 enable set register. Writing 0 has no effect. 13 13 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20083,19 +20233,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable set register. Writing '0' has no effect + Channel 14 enable set register. Writing 0 has no effect. 14 14 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20110,19 +20260,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable set register. Writing '0' has no effect + Channel 15 enable set register. Writing 0 has no effect. 15 15 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20146,19 +20296,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable clear register. Writing '0' has no effect + Channel 0 enable clear register. Writing 0 has no effect. 0 0 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20166,26 +20316,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH1 - Channel 1 enable clear register. Writing '0' has no effect + Channel 1 enable clear register. Writing 0 has no effect. 1 1 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20193,26 +20343,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH2 - Channel 2 enable clear register. Writing '0' has no effect + Channel 2 enable clear register. Writing 0 has no effect. 2 2 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20220,26 +20370,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH3 - Channel 3 enable clear register. Writing '0' has no effect + Channel 3 enable clear register. Writing 0 has no effect. 3 3 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20247,26 +20397,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH4 - Channel 4 enable clear register. Writing '0' has no effect + Channel 4 enable clear register. Writing 0 has no effect. 4 4 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20274,26 +20424,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH5 - Channel 5 enable clear register. Writing '0' has no effect + Channel 5 enable clear register. Writing 0 has no effect. 5 5 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20301,26 +20451,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH6 - Channel 6 enable clear register. Writing '0' has no effect + Channel 6 enable clear register. Writing 0 has no effect. 6 6 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20328,26 +20478,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH7 - Channel 7 enable clear register. Writing '0' has no effect + Channel 7 enable clear register. Writing 0 has no effect. 7 7 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20355,26 +20505,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH8 - Channel 8 enable clear register. Writing '0' has no effect + Channel 8 enable clear register. Writing 0 has no effect. 8 8 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20382,26 +20532,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH9 - Channel 9 enable clear register. Writing '0' has no effect + Channel 9 enable clear register. Writing 0 has no effect. 9 9 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20409,26 +20559,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH10 - Channel 10 enable clear register. Writing '0' has no effect + Channel 10 enable clear register. Writing 0 has no effect. 10 10 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20436,26 +20586,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH11 - Channel 11 enable clear register. Writing '0' has no effect + Channel 11 enable clear register. Writing 0 has no effect. 11 11 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20463,26 +20613,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH12 - Channel 12 enable clear register. Writing '0' has no effect + Channel 12 enable clear register. Writing 0 has no effect. 12 12 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20490,26 +20640,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH13 - Channel 13 enable clear register. Writing '0' has no effect + Channel 13 enable clear register. Writing 0 has no effect. 13 13 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20517,26 +20667,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH14 - Channel 14 enable clear register. Writing '0' has no effect + Channel 14 enable clear register. Writing 0 has no effect. 14 14 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20544,26 +20694,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH15 - Channel 15 enable clear register. Writing '0' has no effect + Channel 15 enable clear register. Writing 0 has no effect. 15 15 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20571,7 +20721,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 @@ -20582,7 +20732,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x6 0x4 CHG[%s] - Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG[n].EN/DIS are enabled. + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled 0x800 read-write @@ -20880,7 +21030,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DPPIC_S - Distributed Programmable Peripheral Interconnect Controller 1 + Distributed programmable peripheral interconnect controller 1 0x50017000 @@ -20933,9 +21083,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -20990,9 +21140,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TIMEOUT will publish to. + DPPI channel that event TIMEOUT will publish to 0 - 3 + 7 EN @@ -21563,9 +21713,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task TRIGGER[n] will subscribe to + DPPI channel that task TRIGGER[n] will subscribe to 0 - 3 + 7 EN @@ -21624,9 +21774,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TRIGGERED[n] will publish to. + DPPI channel that event TRIGGERED[n] will publish to 0 - 3 + 7 EN @@ -23038,9 +23188,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -23071,9 +23221,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SEQSTART[n] will subscribe to + DPPI channel that task SEQSTART[n] will subscribe to 0 - 3 + 7 EN @@ -23102,9 +23252,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task NEXTSTEP will subscribe to + DPPI channel that task NEXTSTEP will subscribe to 0 - 3 + 7 EN @@ -23267,9 +23417,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -23300,9 +23450,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SEQSTARTED[n] will publish to. + DPPI channel that event SEQSTARTED[n] will publish to 0 - 3 + 7 EN @@ -23333,9 +23483,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SEQEND[n] will publish to. + DPPI channel that event SEQEND[n] will publish to 0 - 3 + 7 EN @@ -23364,9 +23514,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event PWMPERIODEND will publish to. + DPPI channel that event PWMPERIODEND will publish to 0 - 3 + 7 EN @@ -23395,9 +23545,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event LOOPSDONE will publish to. + DPPI channel that event LOOPSDONE will publish to 0 - 3 + 7 EN @@ -24520,9 +24670,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -24551,9 +24701,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -24660,9 +24810,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STARTED will publish to. + DPPI channel that event STARTED will publish to 0 - 3 + 7 EN @@ -24691,9 +24841,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -24722,9 +24872,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to 0 - 3 + 7 EN @@ -25021,7 +25171,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FREQ - PDM_CLK frequency + PDM_CLK frequency configuration. 0 31 @@ -25074,19 +25224,19 @@ POSSIBILITY OF SUCH DAMAGE.\n Stereo - Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] 0 Mono - Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] 1 EDGE - Defines on which PDM_CLK edge Left (or mono) is sampled + Defines on which PDM_CLK edge left (or mono) is sampled 1 1 @@ -25119,17 +25269,17 @@ POSSIBILITY OF SUCH DAMAGE.\n MinGain - -20dB gain adjustment (minimum) + -20 dB gain adjustment (minimum) 0x00 DefaultGain - 0dB gain adjustment + 0 dB gain adjustment 0x28 MaxGain - +20dB gain adjustment (maximum) + +20 dB gain adjustment (maximum) 0x50 @@ -25151,17 +25301,17 @@ POSSIBILITY OF SUCH DAMAGE.\n MinGain - -20dB gain adjustment (minimum) + -20 dB gain adjustment (minimum) 0x00 DefaultGain - 0dB gain adjustment + 0 dB gain adjustment 0x28 MaxGain - +20dB gain adjustment (maximum) + +20 dB gain adjustment (maximum) 0x50 @@ -25385,9 +25535,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -25416,9 +25566,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -25529,9 +25679,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXPTRUPD will publish to. + DPPI channel that event RXPTRUPD will publish to 0 - 3 + 7 EN @@ -25560,9 +25710,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -25591,9 +25741,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXPTRUPD will publish to. + DPPI channel that event TXPTRUPD will publish to 0 - 3 + 7 EN @@ -26511,7 +26661,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IPC_NS - Inter Processor Communication 0 + Interprocessor communication 0 0x4002A000 IPC @@ -26532,13 +26682,13 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 TASKS_SEND[%s] - Description collection: Trigger events on channel enabled in SEND_CNF[n]. + Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] 0x000 write-only TASKS_SEND - Trigger events on channel enabled in SEND_CNF[n]. + Trigger events on IPC channel enabled in SEND_CNF[n] 0 0 @@ -26561,9 +26711,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SEND[n] will subscribe to + DPPI channel that task SEND[n] will subscribe to 0 - 3 + 7 EN @@ -26588,13 +26738,13 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 EVENTS_RECEIVE[%s] - Description collection: Event received on one or more of the enabled channels in RECEIVE_CNF[n]. + Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] 0x100 read-write EVENTS_RECEIVE - Event received on one or more of the enabled channels in RECEIVE_CNF[n]. + Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] 0 0 @@ -26622,9 +26772,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RECEIVE[n] will publish to. + DPPI channel that event RECEIVE[n] will publish to 0 - 3 + 7 EN @@ -27409,151 +27559,151 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 SEND_CNF[%s] - Description collection: Send event configuration for TASKS_SEND[n]. + Description collection: Send event configuration for TASKS_SEND[n] 0x510 read-write 0x00000000 CHEN0 - Enable broadcasting on channel 0. + Enable broadcasting on IPC channel 0 0 0 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN1 - Enable broadcasting on channel 1. + Enable broadcasting on IPC channel 1 1 1 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN2 - Enable broadcasting on channel 2. + Enable broadcasting on IPC channel 2 2 2 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN3 - Enable broadcasting on channel 3. + Enable broadcasting on IPC channel 3 3 3 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN4 - Enable broadcasting on channel 4. + Enable broadcasting on IPC channel 4 4 4 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN5 - Enable broadcasting on channel 5. + Enable broadcasting on IPC channel 5 5 5 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN6 - Enable broadcasting on channel 6. + Enable broadcasting on IPC channel 6 6 6 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN7 - Enable broadcasting on channel 7. + Enable broadcasting on IPC channel 7 7 7 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 @@ -27564,151 +27714,151 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 RECEIVE_CNF[%s] - Description collection: Receive event configuration for EVENTS_RECEIVE[n]. + Description collection: Receive event configuration for EVENTS_RECEIVE[n] 0x590 read-write 0x00000000 CHEN0 - Enable subscription to channel 0. + Enable subscription to IPC channel 0 0 0 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN1 - Enable subscription to channel 1. + Enable subscription to IPC channel 1 1 1 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN2 - Enable subscription to channel 2. + Enable subscription to IPC channel 2 2 2 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN3 - Enable subscription to channel 3. + Enable subscription to IPC channel 3 3 3 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN4 - Enable subscription to channel 4. + Enable subscription to IPC channel 4 4 4 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN5 - Enable subscription to channel 5. + Enable subscription to IPC channel 5 5 5 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN6 - Enable subscription to channel 6. + Enable subscription to IPC channel 6 6 6 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN7 - Enable subscription to channel 7. + Enable subscription to IPC channel 7 7 7 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 @@ -27719,7 +27869,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x4 0x4 GPMEM[%s] - Description collection: General purpose memory. + Description collection: General purpose memory 0x610 read-write 0x00000000 @@ -27736,7 +27886,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IPC_S - Inter Processor Communication 1 + Interprocessor communication 1 0x5002A000 @@ -28272,7 +28422,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ID - Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1 + Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. 0 7 @@ -28302,7 +28452,6 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x400 read-only 0x00000001 - READY @@ -28330,7 +28479,6 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x408 read-only 0x00000001 - READYNEXT @@ -28513,7 +28661,6 @@ POSSIBILITY OF SUCH DAMAGE.\n Unspecified 0x584 read-write - WEN @@ -28545,7 +28692,6 @@ POSSIBILITY OF SUCH DAMAGE.\n Non-secure APPROTECT enable register 0x588 write-only - SET @@ -34505,7 +34651,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. 0 0 @@ -34523,7 +34669,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. 1 1 @@ -34541,7 +34687,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. 2 2 @@ -34559,7 +34705,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. 3 3 @@ -34577,7 +34723,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. 4 4 @@ -34595,7 +34741,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. 5 5 @@ -34613,7 +34759,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. 6 6 @@ -34631,7 +34777,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. 7 7 @@ -34649,7 +34795,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. 8 8 @@ -34667,7 +34813,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. 9 9 @@ -34685,7 +34831,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. 10 10 @@ -34703,7 +34849,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. 11 11 @@ -34721,7 +34867,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. 12 12 @@ -34739,7 +34885,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. 13 13 @@ -34757,7 +34903,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. 14 14 @@ -34775,7 +34921,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. 15 15 @@ -34793,7 +34939,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. 16 16 @@ -34811,7 +34957,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. 17 17 @@ -34829,7 +34975,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. 18 18 @@ -34847,7 +34993,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. 19 19 @@ -34865,7 +35011,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. 20 20 @@ -34883,7 +35029,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. 21 21 @@ -34901,7 +35047,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. 22 22 @@ -34919,7 +35065,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. 23 23 @@ -34937,7 +35083,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. 24 24 @@ -34955,7 +35101,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. 25 25 @@ -34973,7 +35119,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. 26 26 @@ -34991,7 +35137,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. 27 27 @@ -35009,7 +35155,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. 28 28 @@ -35027,7 +35173,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. 29 29 @@ -35045,7 +35191,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. 30 30 @@ -35063,7 +35209,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. 31 31 diff --git a/mdk/nrf9160_bitfields.h b/mdk/nrf9160_bitfields.h index 2abc6c4c5..5dbd7f711 100644 --- a/mdk/nrf9160_bitfields.h +++ b/mdk/nrf9160_bitfields.h @@ -147,9 +147,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task HFCLKSTART will subscribe to */ +/* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */ #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */ /* Description: Subscribe configuration for task HFCLKSTOP */ @@ -160,9 +160,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task HFCLKSTOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */ #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */ /* Description: Subscribe configuration for task LFCLKSTART */ @@ -173,9 +173,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task LFCLKSTART will subscribe to */ +/* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */ #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */ /* Description: Subscribe configuration for task LFCLKSTOP */ @@ -186,9 +186,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task LFCLKSTOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */ #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: CLOCK_EVENTS_HFCLKSTARTED */ /* Description: HFCLK oscillator started */ @@ -217,9 +217,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event HFCLKSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */ #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: CLOCK_PUBLISH_LFCLKSTARTED */ /* Description: Publish configuration for event LFCLKSTARTED */ @@ -230,9 +230,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event LFCLKSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */ #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: CLOCK_INTEN */ /* Description: Enable or disable interrupt */ @@ -319,6 +319,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Active clock source */ #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< HFINT - 64 MHz on-chip oscillator */ #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */ /* Register: CLOCK_LFCLKRUN */ @@ -384,14 +385,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Control access port */ /* Register: CTRLAPPERI_MAILBOX_RXDATA */ -/* Description: Data sent from the debugger to the CPU */ +/* Description: Data sent from the debugger to the CPU. */ /* Bits 31..0 : Data received from debugger */ #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */ #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */ /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */ -/* Description: Status to indicate if data sent from the debugger to the CPU has been read */ +/* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */ /* Bit 0 : Status of data in register RXDATA */ #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ @@ -400,14 +401,14 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */ /* Register: CTRLAPPERI_MAILBOX_TXDATA */ -/* Description: Data sent from the CPU to the debugger */ +/* Description: Data sent from the CPU to the debugger. */ /* Bits 31..0 : Data sent to debugger */ #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */ #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */ /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */ -/* Description: Status to indicate if data sent from the CPU to the debugger has been read */ +/* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */ /* Bit 0 : Status of data in register TXDATA */ #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ @@ -416,24 +417,24 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */ /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */ -/* Description: Lock register ERASEPROTECT.DISABLE from being written until next reset */ +/* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */ -/* Bit 0 : Lock register ERASEPROTECT.DISABLE from being written until next reset */ +/* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */ /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */ -/* Description: Disable ERASEPROTECT and perform ERASEALL */ +/* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */ -/* Bits 31..0 : The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */ +/* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ /* Peripheral: DPPIC */ -/* Description: Distributed Programmable Peripheral Interconnect Controller 0 */ +/* Description: Distributed programmable peripheral interconnect controller 0 */ /* Register: DPPIC_TASKS_CHG_EN */ /* Description: Description cluster: Enable channel group n */ @@ -460,9 +461,9 @@ POSSIBILITY OF SUCH DAMAGE. #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */ #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task CHG[n].EN will subscribe to */ +/* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */ #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: DPPIC_SUBSCRIBE_CHG_DIS */ /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */ @@ -473,9 +474,9 @@ POSSIBILITY OF SUCH DAMAGE. #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */ #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task CHG[n].DIS will subscribe to */ +/* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */ #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: DPPIC_CHEN */ /* Description: Channel enable register */ @@ -579,235 +580,235 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: DPPIC_CHENSET */ /* Description: Channel enable set register */ -/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ -/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ -/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ -/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ -/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ -/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ -/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ -/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ -/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ -/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ -/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ -/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ -/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ -/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ -/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ -/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */ #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ /* Register: DPPIC_CHENCLR */ /* Description: Channel enable clear register */ -/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */ -/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ -#define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ -#define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ +#define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */ /* Register: DPPIC_CHG */ -/* Description: Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG[n].EN/DIS are enabled. */ +/* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */ /* Bit 15 : Include or exclude channel 15 */ #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ @@ -926,9 +927,9 @@ POSSIBILITY OF SUCH DAMAGE. #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */ #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task TRIGGER[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */ #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: EGU_EVENTS_TRIGGERED */ /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ @@ -948,9 +949,9 @@ POSSIBILITY OF SUCH DAMAGE. #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */ #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TRIGGERED[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */ #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: EGU_INTEN */ /* Description: Enable or disable interrupt */ @@ -1285,37 +1286,34 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: FICR */ /* Description: Factory Information Configuration Registers */ -/* Register: FICR_INFO_DEVICEID */ -/* Description: Description collection: Device identifier */ +/* Register: FICR_SIPINFO_PARTNO */ +/* Description: SIP part number */ -/* Bits 31..0 : 64 bit unique device identifier */ -#define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ -#define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ +/* Bits 31..0 : */ +#define FICR_SIPINFO_PARTNO_PARTNO_Pos (0UL) /*!< Position of PARTNO field. */ +#define FICR_SIPINFO_PARTNO_PARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PARTNO_PARTNO_Pos) /*!< Bit mask of PARTNO field. */ +#define FICR_SIPINFO_PARTNO_PARTNO_9160 (0x00009160UL) /*!< Device is an nRF9160 sip */ -/* Register: FICR_INFO_PART */ -/* Description: Part code */ +/* Register: FICR_SIPINFO_HWREVISION */ +/* Description: Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A */ -/* Bits 31..0 : Part code */ -#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ -#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ -#define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */ +/* Bits 7..0 : */ +#define FICR_SIPINFO_HWREVISION_HWREVISION_Pos (0UL) /*!< Position of HWREVISION field. */ +#define FICR_SIPINFO_HWREVISION_HWREVISION_Msk (0xFFUL << FICR_SIPINFO_HWREVISION_HWREVISION_Pos) /*!< Bit mask of HWREVISION field. */ -/* Register: FICR_INFO_VARIANT */ -/* Description: Part Variant, Hardware version and Production configuration */ +/* Register: FICR_SIPINFO_VARIANT */ +/* Description: Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA */ -/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ -#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ -#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ -#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ -#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +/* Bits 7..0 : */ +#define FICR_SIPINFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_SIPINFO_VARIANT_VARIANT_Msk (0xFFUL << FICR_SIPINFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ -/* Register: FICR_INFO_PACKAGE */ -/* Description: Package option */ +/* Register: FICR_INFO_DEVICEID */ +/* Description: Description collection: Device identifier */ -/* Bits 31..0 : Package option */ -#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_CC (0x2000UL) /*!< CCxx - 236 ball wlCSP */ +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ /* Register: FICR_INFO_RAM */ /* Description: RAM variant */ @@ -1464,9 +1462,9 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */ #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task OUT[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: GPIOTE_SUBSCRIBE_SET */ /* Description: Description collection: Subscribe configuration for task SET[n] */ @@ -1477,9 +1475,9 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */ #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task SET[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: GPIOTE_SUBSCRIBE_CLR */ /* Description: Description collection: Subscribe configuration for task CLR[n] */ @@ -1490,9 +1488,9 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */ #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task CLR[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: GPIOTE_EVENTS_IN */ /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ @@ -1521,9 +1519,9 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */ #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event IN[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event IN[n] will publish to */ #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: GPIOTE_PUBLISH_PORT */ /* Description: Publish configuration for event PORT */ @@ -1534,9 +1532,9 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */ #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event PORT will publish to. */ +/* Bits 7..0 : DPPI channel that event PORT will publish to */ #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: GPIOTE_INTENSET */ /* Description: Enable interrupt */ @@ -1671,7 +1669,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -1687,7 +1685,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ -/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ @@ -1727,9 +1725,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: I2S_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -1740,9 +1738,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: I2S_EVENTS_RXPTRUPD */ /* Description: The RXD.PTR register has been copied to internal double-buffers. @@ -1784,9 +1782,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */ #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RXPTRUPD will publish to. */ +/* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */ #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: I2S_PUBLISH_STOPPED */ /* Description: Publish configuration for event STOPPED */ @@ -1797,9 +1795,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: I2S_PUBLISH_TXPTRUPD */ /* Description: Publish configuration for event TXPTRUPD */ @@ -1810,9 +1808,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */ #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TXPTRUPD will publish to. */ +/* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */ #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: I2S_INTEN */ /* Description: Enable or disable interrupt */ @@ -2090,12 +2088,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: IPC */ -/* Description: Inter Processor Communication 0 */ +/* Description: Interprocessor communication 0 */ /* Register: IPC_TASKS_SEND */ -/* Description: Description collection: Trigger events on channel enabled in SEND_CNF[n]. */ +/* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */ -/* Bit 0 : Trigger events on channel enabled in SEND_CNF[n]. */ +/* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */ #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */ #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */ #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */ @@ -2109,14 +2107,14 @@ POSSIBILITY OF SUCH DAMAGE. #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */ #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task SEND[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */ #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: IPC_EVENTS_RECEIVE */ -/* Description: Description collection: Event received on one or more of the enabled channels in RECEIVE_CNF[n]. */ +/* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ -/* Bit 0 : Event received on one or more of the enabled channels in RECEIVE_CNF[n]. */ +/* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */ #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */ #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */ @@ -2131,9 +2129,9 @@ POSSIBILITY OF SUCH DAMAGE. #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */ #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RECEIVE[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */ #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: IPC_INTEN */ /* Description: Enable or disable interrupt */ @@ -2356,109 +2354,109 @@ POSSIBILITY OF SUCH DAMAGE. #define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */ /* Register: IPC_SEND_CNF */ -/* Description: Description collection: Send event configuration for TASKS_SEND[n]. */ +/* Description: Description collection: Send event configuration for TASKS_SEND[n] */ -/* Bit 7 : Enable broadcasting on channel 7. */ +/* Bit 7 : Enable broadcasting on IPC channel 7 */ #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ -#define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast. */ -#define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast. */ +#define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */ -/* Bit 6 : Enable broadcasting on channel 6. */ +/* Bit 6 : Enable broadcasting on IPC channel 6 */ #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ -#define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast. */ -#define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast. */ +#define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */ -/* Bit 5 : Enable broadcasting on channel 5. */ +/* Bit 5 : Enable broadcasting on IPC channel 5 */ #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ -#define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast. */ -#define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast. */ +#define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */ -/* Bit 4 : Enable broadcasting on channel 4. */ +/* Bit 4 : Enable broadcasting on IPC channel 4 */ #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ -#define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast. */ -#define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast. */ +#define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */ -/* Bit 3 : Enable broadcasting on channel 3. */ +/* Bit 3 : Enable broadcasting on IPC channel 3 */ #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ -#define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast. */ -#define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast. */ +#define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */ -/* Bit 2 : Enable broadcasting on channel 2. */ +/* Bit 2 : Enable broadcasting on IPC channel 2 */ #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ -#define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast. */ -#define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast. */ +#define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */ -/* Bit 1 : Enable broadcasting on channel 1. */ +/* Bit 1 : Enable broadcasting on IPC channel 1 */ #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ -#define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast. */ -#define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast. */ +#define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */ -/* Bit 0 : Enable broadcasting on channel 0. */ +/* Bit 0 : Enable broadcasting on IPC channel 0 */ #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ -#define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast. */ -#define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast. */ +#define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */ /* Register: IPC_RECEIVE_CNF */ -/* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n]. */ +/* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */ -/* Bit 7 : Enable subscription to channel 7. */ +/* Bit 7 : Enable subscription to IPC channel 7 */ #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ -#define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events. */ -#define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events. */ +#define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */ -/* Bit 6 : Enable subscription to channel 6. */ +/* Bit 6 : Enable subscription to IPC channel 6 */ #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ -#define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events. */ -#define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events. */ +#define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */ -/* Bit 5 : Enable subscription to channel 5. */ +/* Bit 5 : Enable subscription to IPC channel 5 */ #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ -#define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events. */ -#define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events. */ +#define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */ -/* Bit 4 : Enable subscription to channel 4. */ +/* Bit 4 : Enable subscription to IPC channel 4 */ #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ -#define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events. */ -#define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events. */ +#define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */ -/* Bit 3 : Enable subscription to channel 3. */ +/* Bit 3 : Enable subscription to IPC channel 3 */ #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ -#define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events. */ -#define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events. */ +#define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */ -/* Bit 2 : Enable subscription to channel 2. */ +/* Bit 2 : Enable subscription to IPC channel 2 */ #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ -#define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events. */ -#define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events. */ +#define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */ -/* Bit 1 : Enable subscription to channel 1. */ +/* Bit 1 : Enable subscription to IPC channel 1 */ #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ -#define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events. */ -#define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events. */ +#define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */ -/* Bit 0 : Enable subscription to channel 0. */ +/* Bit 0 : Enable subscription to IPC channel 0 */ #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ -#define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events. */ -#define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events. */ +#define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */ /* Register: IPC_GPMEM */ -/* Description: Description collection: General purpose memory. */ +/* Description: Description collection: General purpose memory */ /* Bits 31..0 : General purpose memory */ #define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */ @@ -2611,7 +2609,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: KMU_SELECTKEYSLOT */ /* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */ -/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1 */ +/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */ #define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */ #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */ @@ -4216,193 +4214,193 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ -/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +/* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ -/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +/* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ -/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +/* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ -/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +/* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ -/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +/* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ -/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +/* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ -/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +/* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ -/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +/* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ -/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +/* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ -/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +/* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ -/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +/* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ -/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +/* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ -/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +/* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ -/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +/* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ -/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +/* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ -/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +/* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ -/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +/* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ -/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +/* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ -/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +/* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ -/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +/* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ -/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +/* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ -/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +/* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ -/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +/* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ -/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +/* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ -/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +/* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ -/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +/* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ -/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +/* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ -/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +/* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ -/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +/* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ -/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +/* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ -/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +/* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ -/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +/* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ @@ -4496,9 +4494,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PDM_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -4509,9 +4507,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PDM_EVENTS_STARTED */ /* Description: PDM transfer has started */ @@ -4549,9 +4547,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event STARTED will publish to */ #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PDM_PUBLISH_STOPPED */ /* Description: Publish configuration for event STOPPED */ @@ -4562,9 +4560,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PDM_PUBLISH_END */ /* Description: Publish configuration for event END */ @@ -4575,9 +4573,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ #define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event END will publish to. */ +/* Bits 7..0 : DPPI channel that event END will publish to */ #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PDM_PUBLISH_END_CHIDX_Msk (0xFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PDM_INTEN */ /* Description: Enable or disable interrupt */ @@ -4660,7 +4658,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_PDMCLKCTRL */ /* Description: PDM clock generator control */ -/* Bits 31..0 : PDM_CLK frequency */ +/* Bits 31..0 : PDM_CLK frequency configuration. */ #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ @@ -4673,7 +4671,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_MODE */ /* Description: Defines the routing of the connected PDM microphones' signals */ -/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +/* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */ #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ @@ -4682,8 +4680,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Mono or stereo operation */ #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ -#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ -#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */ /* Register: PDM_GAINL */ /* Description: Left output gain adjustment */ @@ -4691,9 +4689,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ -#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ -#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ /* Register: PDM_GAINR */ /* Description: Right output gain adjustment */ @@ -4701,9 +4699,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ -#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ -#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ /* Register: PDM_RATIO */ /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ @@ -4783,9 +4781,9 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */ #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task CONSTLAT will subscribe to */ +/* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */ #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: POWER_SUBSCRIBE_LOWPWR */ /* Description: Subscribe configuration for task LOWPWR */ @@ -4796,9 +4794,9 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */ #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task LOWPWR will subscribe to */ +/* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */ #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: POWER_EVENTS_POFWARN */ /* Description: Power failure warning */ @@ -4836,9 +4834,9 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */ #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event POFWARN will publish to. */ +/* Bits 7..0 : DPPI channel that event POFWARN will publish to */ #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: POWER_PUBLISH_SLEEPENTER */ /* Description: Publish configuration for event SLEEPENTER */ @@ -4849,9 +4847,9 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */ #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event SLEEPENTER will publish to. */ +/* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */ #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: POWER_PUBLISH_SLEEPEXIT */ /* Description: Publish configuration for event SLEEPEXIT */ @@ -4862,9 +4860,9 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */ #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event SLEEPEXIT will publish to. */ +/* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */ #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: POWER_INTEN */ /* Description: Enable or disable interrupt */ @@ -4996,6 +4994,24 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ +/* Register: POWER_LTEMODEM_STARTN */ +/* Description: Start LTE modem */ + +/* Bit 0 : Start LTE modem */ +#define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */ +#define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */ +#define POWER_LTEMODEM_STARTN_STARTN_Start (0UL) /*!< Start LTE modem */ +#define POWER_LTEMODEM_STARTN_STARTN_Hold (1UL) /*!< Hold LTE modem disabled */ + +/* Register: POWER_LTEMODEM_FORCEOFF */ +/* Description: Force off LTE modem */ + +/* Bit 0 : Force off LTE modem */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off active */ + /* Peripheral: PWM */ /* Description: Pulse width modulation unit 0 */ @@ -5033,9 +5049,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PWM_SUBSCRIBE_SEQSTART */ /* Description: Description collection: Subscribe configuration for task SEQSTART[n] */ @@ -5046,9 +5062,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */ #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task SEQSTART[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */ #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PWM_SUBSCRIBE_NEXTSTEP */ /* Description: Subscribe configuration for task NEXTSTEP */ @@ -5059,9 +5075,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */ #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task NEXTSTEP will subscribe to */ +/* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */ #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PWM_EVENTS_STOPPED */ /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ @@ -5117,9 +5133,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PWM_PUBLISH_SEQSTARTED */ /* Description: Description collection: Publish configuration for event SEQSTARTED[n] */ @@ -5130,9 +5146,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event SEQSTARTED[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */ #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PWM_PUBLISH_SEQEND */ /* Description: Description collection: Publish configuration for event SEQEND[n] */ @@ -5143,9 +5159,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */ #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event SEQEND[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */ #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PWM_PUBLISH_PWMPERIODEND */ /* Description: Publish configuration for event PWMPERIODEND */ @@ -5156,9 +5172,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */ #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event PWMPERIODEND will publish to. */ +/* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */ #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PWM_PUBLISH_LOOPSDONE */ /* Description: Publish configuration for event LOOPSDONE */ @@ -5169,9 +5185,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */ #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event LOOPSDONE will publish to. */ +/* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */ #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: PWM_SHORTS */ /* Description: Shortcuts between local events and tasks */ @@ -5475,6 +5491,15 @@ POSSIBILITY OF SUCH DAMAGE. #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */ +/* Register: REGULATORS_EXTPOFCON */ +/* Description: External power failure warning configuration */ + +/* Bit 0 : Enable or disable external power failure warning */ +#define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define REGULATORS_EXTPOFCON_POF_Disabled (0UL) /*!< Disable */ +#define REGULATORS_EXTPOFCON_POF_Enabled (1UL) /*!< Enable */ + /* Register: REGULATORS_DCDCEN */ /* Description: Enable DC/DC mode of the main voltage regulator. */ @@ -5529,9 +5554,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: RTC_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -5542,9 +5567,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: RTC_SUBSCRIBE_CLEAR */ /* Description: Subscribe configuration for task CLEAR */ @@ -5555,9 +5580,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task CLEAR will subscribe to */ +/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */ /* Description: Subscribe configuration for task TRIGOVRFLW */ @@ -5568,9 +5593,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task TRIGOVRFLW will subscribe to */ +/* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */ #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: RTC_EVENTS_TICK */ /* Description: Event on counter increment */ @@ -5608,9 +5633,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */ #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TICK will publish to. */ +/* Bits 7..0 : DPPI channel that event TICK will publish to */ #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define RTC_PUBLISH_TICK_CHIDX_Msk (0xFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: RTC_PUBLISH_OVRFLW */ /* Description: Publish configuration for event OVRFLW */ @@ -5621,9 +5646,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */ #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event OVRFLW will publish to. */ +/* Bits 7..0 : DPPI channel that event OVRFLW will publish to */ #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: RTC_PUBLISH_COMPARE */ /* Description: Description collection: Publish configuration for event COMPARE[n] */ @@ -5634,9 +5659,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event COMPARE[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: RTC_INTENSET */ /* Description: Enable interrupt */ @@ -5735,37 +5760,37 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ /* Bit 18 : Enable or disable event routing for event COMPARE[2] */ #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ /* Bit 17 : Enable or disable event routing for event COMPARE[1] */ #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ /* Bit 16 : Enable or disable event routing for event COMPARE[0] */ #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ /* Bit 1 : Enable or disable event routing for event OVRFLW */ #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ /* Bit 0 : Enable or disable event routing for event TICK */ #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ /* Register: RTC_EVTENSET */ /* Description: Enable event routing */ @@ -5923,9 +5948,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_SUBSCRIBE_SAMPLE */ /* Description: Subscribe configuration for task SAMPLE */ @@ -5936,9 +5961,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */ #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task SAMPLE will subscribe to */ +/* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */ #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -5949,9 +5974,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */ /* Description: Subscribe configuration for task CALIBRATEOFFSET */ @@ -5962,9 +5987,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */ #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task CALIBRATEOFFSET will subscribe to */ +/* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */ #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_EVENTS_STARTED */ /* Description: The ADC has started */ @@ -6047,9 +6072,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event STARTED will publish to */ #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_PUBLISH_END */ /* Description: Publish configuration for event END */ @@ -6060,9 +6085,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ #define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event END will publish to. */ +/* Bits 7..0 : DPPI channel that event END will publish to */ #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_PUBLISH_END_CHIDX_Msk (0xFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_PUBLISH_DONE */ /* Description: Publish configuration for event DONE */ @@ -6073,9 +6098,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */ #define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event DONE will publish to. */ +/* Bits 7..0 : DPPI channel that event DONE will publish to */ #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_PUBLISH_RESULTDONE */ /* Description: Publish configuration for event RESULTDONE */ @@ -6086,9 +6111,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */ #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RESULTDONE will publish to. */ +/* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */ #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_PUBLISH_CALIBRATEDONE */ /* Description: Publish configuration for event CALIBRATEDONE */ @@ -6099,9 +6124,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */ #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event CALIBRATEDONE will publish to. */ +/* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */ #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_PUBLISH_STOPPED */ /* Description: Publish configuration for event STOPPED */ @@ -6112,9 +6137,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_PUBLISH_CH_LIMITH */ /* Description: Description cluster: Publish configuration for event CH[n].LIMITH */ @@ -6125,9 +6150,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */ #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event CH[n].LIMITH will publish to. */ +/* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */ #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_PUBLISH_CH_LIMITL */ /* Description: Description cluster: Publish configuration for event CH[n].LIMITL */ @@ -6138,9 +6163,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */ #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event CH[n].LIMITL will publish to. */ +/* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */ #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SAADC_INTEN */ /* Description: Enable or disable interrupt */ @@ -6819,9 +6844,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -6832,9 +6857,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_SUBSCRIBE_SUSPEND */ /* Description: Subscribe configuration for task SUSPEND */ @@ -6845,9 +6870,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task SUSPEND will subscribe to */ +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_SUBSCRIBE_RESUME */ /* Description: Subscribe configuration for task RESUME */ @@ -6858,9 +6883,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task RESUME will subscribe to */ +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_EVENTS_STOPPED */ /* Description: SPI transaction has stopped */ @@ -6916,9 +6941,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_PUBLISH_ENDRX */ /* Description: Publish configuration for event ENDRX */ @@ -6929,9 +6954,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ENDRX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDRX will publish to */ #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_PUBLISH_END */ /* Description: Publish configuration for event END */ @@ -6942,9 +6967,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event END will publish to. */ +/* Bits 7..0 : DPPI channel that event END will publish to */ #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_PUBLISH_END_CHIDX_Msk (0xFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_PUBLISH_ENDTX */ /* Description: Publish configuration for event ENDTX */ @@ -6955,9 +6980,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ENDTX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDTX will publish to */ #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_PUBLISH_STARTED */ /* Description: Publish configuration for event STARTED */ @@ -6968,9 +6993,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event STARTED will publish to */ #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIM_SHORTS */ /* Description: Shortcuts between local events and tasks */ @@ -7236,9 +7261,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task ACQUIRE will subscribe to */ +/* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */ #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIS_SUBSCRIBE_RELEASE */ /* Description: Subscribe configuration for task RELEASE */ @@ -7249,9 +7274,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task RELEASE will subscribe to */ +/* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */ #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIS_EVENTS_END */ /* Description: Granted transaction completed */ @@ -7289,9 +7314,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event END will publish to. */ +/* Bits 7..0 : DPPI channel that event END will publish to */ #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIS_PUBLISH_END_CHIDX_Msk (0xFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIS_PUBLISH_ENDRX */ /* Description: Publish configuration for event ENDRX */ @@ -7302,9 +7327,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ENDRX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDRX will publish to */ #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIS_PUBLISH_ACQUIRED */ /* Description: Publish configuration for event ACQUIRED */ @@ -7315,9 +7340,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ACQUIRED will publish to. */ +/* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */ #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPIS_SHORTS */ /* Description: Shortcuts between local events and tasks */ @@ -7600,9 +7625,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */ #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RAMACCERR will publish to. */ +/* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */ #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPU_PUBLISH_FLASHACCERR */ /* Description: Publish configuration for event FLASHACCERR */ @@ -7613,9 +7638,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */ #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event FLASHACCERR will publish to. */ +/* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */ #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPU_PUBLISH_PERIPHACCERR */ /* Description: Publish configuration for event PERIPHACCERR */ @@ -7626,9 +7651,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */ #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event PERIPHACCERR will publish to. */ +/* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */ #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: SPU_INTEN */ /* Description: Enable or disable interrupt */ @@ -7723,7 +7748,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */ #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */ -/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ +/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */ @@ -8086,9 +8111,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */ #define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ -/* Bits 3..0 : Region number */ +/* Bits 4..0 : Region number */ #define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ -#define SPU_RAMNSC_REGION_REGION_Msk (0xFUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */ +#define SPU_RAMNSC_REGION_REGION_Msk (0x1FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */ /* Register: SPU_RAMNSC_SIZE */ /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */ @@ -8224,21 +8249,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: TAD */ /* Description: Trace and debug control */ -/* Register: TAD_CLOCKSTART */ +/* Register: TAD_TASKS_CLOCKSTART */ /* Description: Start all trace and debug clocks. */ -/* Bit 0 : */ -#define TAD_CLOCKSTART_START_Pos (0UL) /*!< Position of START field. */ -#define TAD_CLOCKSTART_START_Msk (0x1UL << TAD_CLOCKSTART_START_Pos) /*!< Bit mask of START field. */ -#define TAD_CLOCKSTART_START_Start (1UL) /*!< Start all trace and debug clocks. */ +/* Bit 0 : Start all trace and debug clocks. */ +#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */ +#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */ +#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (1UL) /*!< Trigger task */ -/* Register: TAD_CLOCKSTOP */ +/* Register: TAD_TASKS_CLOCKSTOP */ /* Description: Stop all trace and debug clocks. */ -/* Bit 0 : */ -#define TAD_CLOCKSTOP_STOP_Pos (0UL) /*!< Position of STOP field. */ -#define TAD_CLOCKSTOP_STOP_Msk (0x1UL << TAD_CLOCKSTOP_STOP_Pos) /*!< Bit mask of STOP field. */ -#define TAD_CLOCKSTOP_STOP_Stop (1UL) /*!< Stop all trace and debug clocks. */ +/* Bit 0 : Stop all trace and debug clocks. */ +#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */ +#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */ +#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: TAD_ENABLE */ /* Description: Enable debug domain and aquire selected GPIOs */ @@ -8250,7 +8275,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */ /* Register: TAD_PSEL_TRACECLK */ -/* Description: Pin number configuration for TRACECLK */ +/* Description: Pin configuration for TRACECLK */ /* Bit 31 : Connection */ #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -8261,9 +8286,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACECLK_PIN_Traceclk (21UL) /*!< TRACECLK pin */ /* Register: TAD_PSEL_TRACEDATA0 */ -/* Description: Pin number configuration for TRACEDATA[0] */ +/* Description: Pin configuration for TRACEDATA[0] */ /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -8274,9 +8300,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (22UL) /*!< TRACEDATA0 pin */ /* Register: TAD_PSEL_TRACEDATA1 */ -/* Description: Pin number configuration for TRACEDATA[1] */ +/* Description: Pin configuration for TRACEDATA[1] */ /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -8287,9 +8314,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (23UL) /*!< TRACEDATA1 pin */ /* Register: TAD_PSEL_TRACEDATA2 */ -/* Description: Pin number configuration for TRACEDATA[2] */ +/* Description: Pin configuration for TRACEDATA[2] */ /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -8300,9 +8328,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (24UL) /*!< TRACEDATA2 pin */ /* Register: TAD_PSEL_TRACEDATA3 */ -/* Description: Pin number configuration for TRACEDATA[3] */ +/* Description: Pin configuration for TRACEDATA[3] */ /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -8313,17 +8342,18 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */ +#define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (25UL) /*!< TRACEDATA3 pin */ /* Register: TAD_TRACEPORTSPEED */ -/* Description: Clocking options for the Trace Port debug interface */ +/* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */ -/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ +/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */ #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< Trace Port clock is: 32MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< Trace Port clock is: 16MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< Trace Port clock is: 8MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< Trace Port clock is: 4MHz */ /* Peripheral: TIMER */ @@ -8386,9 +8416,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TIMER_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -8399,9 +8429,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TIMER_SUBSCRIBE_COUNT */ /* Description: Subscribe configuration for task COUNT */ @@ -8412,9 +8442,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task COUNT will subscribe to */ +/* Bits 7..0 : DPPI channel that task COUNT will subscribe to */ #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TIMER_SUBSCRIBE_CLEAR */ /* Description: Subscribe configuration for task CLEAR */ @@ -8425,9 +8455,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task CLEAR will subscribe to */ +/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TIMER_SUBSCRIBE_SHUTDOWN */ /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */ @@ -8438,9 +8468,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task SHUTDOWN will subscribe to */ +/* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */ #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TIMER_SUBSCRIBE_CAPTURE */ /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */ @@ -8451,9 +8481,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task CAPTURE[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TIMER_EVENTS_COMPARE */ /* Description: Description collection: Compare event on CC[n] match */ @@ -8473,9 +8503,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event COMPARE[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TIMER_SHORTS */ /* Description: Shortcuts between local events and tasks */ @@ -8739,9 +8769,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STARTRX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_SUBSCRIBE_STARTTX */ /* Description: Subscribe configuration for task STARTTX */ @@ -8752,9 +8782,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STARTTX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -8765,9 +8795,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_SUBSCRIBE_SUSPEND */ /* Description: Subscribe configuration for task SUSPEND */ @@ -8778,9 +8808,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task SUSPEND will subscribe to */ +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_SUBSCRIBE_RESUME */ /* Description: Subscribe configuration for task RESUME */ @@ -8791,9 +8821,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task RESUME will subscribe to */ +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_EVENTS_STOPPED */ /* Description: TWI stopped */ @@ -8867,9 +8897,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_PUBLISH_ERROR */ /* Description: Publish configuration for event ERROR */ @@ -8880,9 +8910,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ERROR will publish to. */ +/* Bits 7..0 : DPPI channel that event ERROR will publish to */ #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_PUBLISH_SUSPENDED */ /* Description: Publish configuration for event SUSPENDED */ @@ -8893,9 +8923,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event SUSPENDED will publish to. */ +/* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */ #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_PUBLISH_RXSTARTED */ /* Description: Publish configuration for event RXSTARTED */ @@ -8906,9 +8936,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_PUBLISH_TXSTARTED */ /* Description: Publish configuration for event TXSTARTED */ @@ -8919,9 +8949,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_PUBLISH_LASTRX */ /* Description: Publish configuration for event LASTRX */ @@ -8932,9 +8962,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event LASTRX will publish to. */ +/* Bits 7..0 : DPPI channel that event LASTRX will publish to */ #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_PUBLISH_LASTTX */ /* Description: Publish configuration for event LASTTX */ @@ -8945,9 +8975,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event LASTTX will publish to. */ +/* Bits 7..0 : DPPI channel that event LASTTX will publish to */ #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIM_SHORTS */ /* Description: Shortcuts between local events and tasks */ @@ -9323,9 +9353,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_SUBSCRIBE_SUSPEND */ /* Description: Subscribe configuration for task SUSPEND */ @@ -9336,9 +9366,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task SUSPEND will subscribe to */ +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_SUBSCRIBE_RESUME */ /* Description: Subscribe configuration for task RESUME */ @@ -9349,9 +9379,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task RESUME will subscribe to */ +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_SUBSCRIBE_PREPARERX */ /* Description: Subscribe configuration for task PREPARERX */ @@ -9362,9 +9392,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task PREPARERX will subscribe to */ +/* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */ #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_SUBSCRIBE_PREPARETX */ /* Description: Subscribe configuration for task PREPARETX */ @@ -9375,9 +9405,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task PREPARETX will subscribe to */ +/* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */ #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_EVENTS_STOPPED */ /* Description: TWI stopped */ @@ -9442,9 +9472,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_PUBLISH_ERROR */ /* Description: Publish configuration for event ERROR */ @@ -9455,9 +9485,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ERROR will publish to. */ +/* Bits 7..0 : DPPI channel that event ERROR will publish to */ #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_PUBLISH_RXSTARTED */ /* Description: Publish configuration for event RXSTARTED */ @@ -9468,9 +9498,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_PUBLISH_TXSTARTED */ /* Description: Publish configuration for event TXSTARTED */ @@ -9481,9 +9511,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_PUBLISH_WRITE */ /* Description: Publish configuration for event WRITE */ @@ -9494,9 +9524,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event WRITE will publish to. */ +/* Bits 7..0 : DPPI channel that event WRITE will publish to */ #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_PUBLISH_READ */ /* Description: Publish configuration for event READ */ @@ -9507,9 +9537,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event READ will publish to. */ +/* Bits 7..0 : DPPI channel that event READ will publish to */ #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define TWIS_PUBLISH_READ_CHIDX_Msk (0xFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: TWIS_SHORTS */ /* Description: Shortcuts between local events and tasks */ @@ -9679,7 +9709,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -9860,9 +9890,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STARTRX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_SUBSCRIBE_STOPRX */ /* Description: Subscribe configuration for task STOPRX */ @@ -9873,9 +9903,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOPRX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */ #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_SUBSCRIBE_STARTTX */ /* Description: Subscribe configuration for task STARTTX */ @@ -9886,9 +9916,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STARTTX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_SUBSCRIBE_STOPTX */ /* Description: Subscribe configuration for task STOPTX */ @@ -9899,9 +9929,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task STOPTX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */ #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_SUBSCRIBE_FLUSHRX */ /* Description: Subscribe configuration for task FLUSHRX */ @@ -9912,9 +9942,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task FLUSHRX will subscribe to */ +/* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */ #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_EVENTS_CTS */ /* Description: CTS is activated (set low). Clear To Send. */ @@ -10024,9 +10054,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event CTS will publish to. */ +/* Bits 7..0 : DPPI channel that event CTS will publish to */ #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_NCTS */ /* Description: Publish configuration for event NCTS */ @@ -10037,9 +10067,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event NCTS will publish to. */ +/* Bits 7..0 : DPPI channel that event NCTS will publish to */ #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_RXDRDY */ /* Description: Publish configuration for event RXDRDY */ @@ -10050,9 +10080,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RXDRDY will publish to. */ +/* Bits 7..0 : DPPI channel that event RXDRDY will publish to */ #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_ENDRX */ /* Description: Publish configuration for event ENDRX */ @@ -10063,9 +10093,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ENDRX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDRX will publish to */ #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_TXDRDY */ /* Description: Publish configuration for event TXDRDY */ @@ -10076,9 +10106,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TXDRDY will publish to. */ +/* Bits 7..0 : DPPI channel that event TXDRDY will publish to */ #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_ENDTX */ /* Description: Publish configuration for event ENDTX */ @@ -10089,9 +10119,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ENDTX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDTX will publish to */ #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_ERROR */ /* Description: Publish configuration for event ERROR */ @@ -10102,9 +10132,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event ERROR will publish to. */ +/* Bits 7..0 : DPPI channel that event ERROR will publish to */ #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_RXTO */ /* Description: Publish configuration for event RXTO */ @@ -10115,9 +10145,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RXTO will publish to. */ +/* Bits 7..0 : DPPI channel that event RXTO will publish to */ #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_RXSTARTED */ /* Description: Publish configuration for event RXSTARTED */ @@ -10128,9 +10158,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event RXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_TXSTARTED */ /* Description: Publish configuration for event TXSTARTED */ @@ -10141,9 +10171,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_PUBLISH_TXSTOPPED */ /* Description: Publish configuration for event TXSTOPPED */ @@ -10154,9 +10184,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TXSTOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */ #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: UARTE_SHORTS */ /* Description: Shortcuts between local events and tasks */ @@ -10403,7 +10433,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source This register is read/write one to clear. */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -10513,7 +10543,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ @@ -10617,6 +10647,15 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */ #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL) /*!< Max debounce time = (255*64 us + 0.5 us) */ +/* Register: UICR_APPNVMCPOFGUARD */ +/* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . */ + +/* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */ + /* Register: UICR_SECUREAPPROTECT */ /* Description: Secure access port protection */ @@ -10649,9 +10688,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UICR_KEYSLOT_CONFIG_DEST */ /* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) - will be pushed by KMU. Note that this address MUST match that of a peripherals + will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into - an address range which the CPU can potentially read! */ + an address range which the CPU can potentially read. */ /* Bits 31..0 : Secure APB destination address */ #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */ @@ -10853,9 +10892,9 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 3..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: WDT_EVENTS_TIMEOUT */ /* Description: Watchdog timeout */ @@ -10875,9 +10914,9 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */ #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 3..0 : Channel that event TIMEOUT will publish to. */ +/* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */ #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +#define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: WDT_INTENSET */ /* Description: Enable interrupt */ diff --git a/mdk/nrf9160_name_change.h b/mdk/nrf9160_name_change.h index 753a6487a..db74658b3 100644 --- a/mdk/nrf9160_name_change.h +++ b/mdk/nrf9160_name_change.h @@ -37,22 +37,43 @@ POSSIBILITY OF SUCH DAMAGE. /*lint ++flb "Enter library region */ -/* This file is given to prevent your SW from not compiling with the updates made to nrf9160.h and +/* This file is given to prevent your SW from not compiling with the updates made to nrf9160.h and * nrf9160_bitfields.h. The macros defined in this file were available previously. Do not use these * macros on purpose. Use the ones defined in nrf9160.h and nrf9160_bitfields.h instead. */ + +/* SAADC enums */ +/* Changes to enum names in SAADC */ +#define SAADC_CH_PSELP_PSELP_VDD SAADC_CH_PSELP_PSELP_VDDGPIO +#define SAADC_CH_PSELP_PSELN_VDD SAADC_CH_PSELP_PSELN_VDDGPIO + +/* CTRLAP PERI Fields */ +#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos +#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk +#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked +#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked + + /* DPPI */ + #define DPPI_PRESENT DPPIC_PRESENT + #define DPPI_COUNT DPPIC_COUNT + #define DPPI_CH_NUM DPPIC_CH_NUM + #define DPPI_GROUP_NUM DPPIC_GROUP_NUM - /* SAADC enums */ - /* Changes to enum names in SAADC */ - #define SAADC_CH_PSELP_PSELP_VDD SAADC_CH_PSELP_PSELP_VDDGPIO - #define SAADC_CH_PSELP_PSELN_VDD SAADC_CH_PSELP_PSELN_VDDGPIO - - /* CTRLAP PERI Fields */ - #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos - #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk - #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked - #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked - - /*lint --flb "Leave library region" */ +/* Serial box enums */ +#define UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 +#define UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 +#define UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 +#define UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + +/* TAD */ + +#define TAD_CLOCKSTART_START_Pos TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos +#define TAD_CLOCKSTART_START_Msk TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk +#define TAD_CLOCKSTART_START_Start TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger +#define TAD_CLOCKSTOP_STOP_Pos TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos +#define TAD_CLOCKSTOP_STOP_Msk TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk +#define TAD_CLOCKSTOP_STOP_Stop TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger + +/*lint --flb "Leave library region" */ #endif /* NRF9160_NAME_CHANGE_H */ diff --git a/mdk/nrf9160_peripherals.h b/mdk/nrf9160_peripherals.h index 5a2edae07..0a05b3bad 100644 --- a/mdk/nrf9160_peripherals.h +++ b/mdk/nrf9160_peripherals.h @@ -61,11 +61,11 @@ POSSIBILITY OF SUCH DAMAGE. #define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL /* Distributed Peripheral to Peripheral Interconnect */ -#define DPPI_PRESENT -#define DPPI_COUNT 1 +#define DPPIC_PRESENT +#define DPPIC_COUNT 1 -#define DPPI_CH_NUM 16 -#define DPPI_GROUP_NUM 6 +#define DPPIC_CH_NUM 16 +#define DPPIC_GROUP_NUM 6 /* Event Generator Unit */ #define EGU_PRESENT diff --git a/mdk/nrf91_erratas.h b/mdk/nrf91_erratas.h index ac724ba85..29590ad41 100644 --- a/mdk/nrf91_erratas.h +++ b/mdk/nrf91_erratas.h @@ -64,6 +64,7 @@ static bool nrf91_errata_30(void) __UNUSED; static bool nrf91_errata_31(void) __UNUSED; static bool nrf91_errata_32(void) __UNUSED; static bool nrf91_errata_33(void) __UNUSED; +static bool nrf91_errata_35(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) @@ -1165,4 +1166,48 @@ static bool nrf91_errata_33(void) #endif } +/* ========= Errata 35 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_35_PRESENT 1 +#else + #define NRF91_ERRATA_35_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_35_ENABLE_WORKAROUND + #define NRF91_ERRATA_35_ENABLE_WORKAROUND 0 +#endif + +static bool nrf91_errata_35(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + #endif /* NRF91_ERRATAS_H */ diff --git a/mdk/ses_startup_nrf51.s b/mdk/ses_startup_nrf51.s index 2f40a7d77..45573e6bc 100644 --- a/mdk/ses_startup_nrf51.s +++ b/mdk/ses_startup_nrf51.s @@ -155,16 +155,16 @@ _vectors: VECTOR Reset_Handler EXC_HANDLER NMI_Handler EXC_HANDLER HardFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler @@ -174,7 +174,7 @@ _vectors: ISR_HANDLER UART0_IRQHandler ISR_HANDLER SPI0_TWI0_IRQHandler ISR_HANDLER SPI1_TWI1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER GPIOTE_IRQHandler ISR_HANDLER ADC_IRQHandler ISR_HANDLER TIMER0_IRQHandler @@ -195,12 +195,12 @@ _vectors: ISR_HANDLER SWI3_IRQHandler ISR_HANDLER SWI4_IRQHandler ISR_HANDLER SWI5_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf52.s b/mdk/ses_startup_nrf52.s index 9380aa6b2..ac18315cf 100644 --- a/mdk/ses_startup_nrf52.s +++ b/mdk/ses_startup_nrf52.s @@ -144,13 +144,13 @@ _vectors: EXC_HANDLER MemoryManagement_Handler EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler @@ -185,8 +185,8 @@ _vectors: ISR_HANDLER TIMER4_IRQHandler ISR_HANDLER PWM0_IRQHandler ISR_HANDLER PDM_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER MWU_IRQHandler ISR_HANDLER PWM1_IRQHandler ISR_HANDLER PWM2_IRQHandler @@ -194,79 +194,79 @@ _vectors: ISR_HANDLER RTC2_IRQHandler ISR_HANDLER I2S_IRQHandler ISR_HANDLER FPU_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf52805.s b/mdk/ses_startup_nrf52805.s index 300fb5761..7ea9e6fc1 100644 --- a/mdk/ses_startup_nrf52805.s +++ b/mdk/ses_startup_nrf52805.s @@ -144,13 +144,13 @@ _vectors: EXC_HANDLER MemoryManagement_Handler EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler @@ -160,7 +160,7 @@ _vectors: ISR_HANDLER UARTE0_UART0_IRQHandler ISR_HANDLER TWIM0_TWIS0_TWI0_IRQHandler ISR_HANDLER SPIM0_SPIS0_SPI0_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER GPIOTE_IRQHandler ISR_HANDLER SAADC_IRQHandler ISR_HANDLER TIMER0_IRQHandler @@ -174,99 +174,99 @@ _vectors: ISR_HANDLER WDT_IRQHandler ISR_HANDLER RTC1_IRQHandler ISR_HANDLER QDEC_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER SWI0_EGU0_IRQHandler ISR_HANDLER SWI1_EGU1_IRQHandler ISR_HANDLER SWI2_IRQHandler ISR_HANDLER SWI3_IRQHandler ISR_HANDLER SWI4_IRQHandler ISR_HANDLER SWI5_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf52810.s b/mdk/ses_startup_nrf52810.s index 5d00dc38a..1fd61de59 100644 --- a/mdk/ses_startup_nrf52810.s +++ b/mdk/ses_startup_nrf52810.s @@ -167,13 +167,13 @@ _vectors: EXC_HANDLER MemoryManagement_Handler EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler @@ -183,7 +183,7 @@ _vectors: ISR_HANDLER UARTE0_UART0_IRQHandler ISR_HANDLER TWIM0_TWIS0_TWI0_IRQHandler ISR_HANDLER SPIM0_SPIS0_SPI0_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER GPIOTE_IRQHandler ISR_HANDLER SAADC_IRQHandler ISR_HANDLER TIMER0_IRQHandler @@ -204,92 +204,92 @@ _vectors: ISR_HANDLER SWI3_IRQHandler ISR_HANDLER SWI4_IRQHandler ISR_HANDLER SWI5_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER PWM0_IRQHandler ISR_HANDLER PDM_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf52811.s b/mdk/ses_startup_nrf52811.s index 9473cc4fb..8de68add3 100644 --- a/mdk/ses_startup_nrf52811.s +++ b/mdk/ses_startup_nrf52811.s @@ -144,13 +144,13 @@ _vectors: EXC_HANDLER MemoryManagement_Handler EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler @@ -160,7 +160,7 @@ _vectors: ISR_HANDLER UARTE0_UART0_IRQHandler ISR_HANDLER TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler ISR_HANDLER SPIM0_SPIS0_SPI0_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER GPIOTE_IRQHandler ISR_HANDLER SAADC_IRQHandler ISR_HANDLER TIMER0_IRQHandler @@ -181,92 +181,92 @@ _vectors: ISR_HANDLER SWI3_IRQHandler ISR_HANDLER SWI4_IRQHandler ISR_HANDLER SWI5_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER PWM0_IRQHandler ISR_HANDLER PDM_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf52820.s b/mdk/ses_startup_nrf52820.s index 7ed027acf..84087623d 100644 --- a/mdk/ses_startup_nrf52820.s +++ b/mdk/ses_startup_nrf52820.s @@ -144,13 +144,13 @@ _vectors: EXC_HANDLER MemoryManagement_Handler EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler @@ -160,9 +160,9 @@ _vectors: ISR_HANDLER UARTE0_UART0_IRQHandler ISR_HANDLER SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler ISR_HANDLER SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER GPIOTE_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER TIMER0_IRQHandler ISR_HANDLER TIMER1_IRQHandler ISR_HANDLER TIMER2_IRQHandler @@ -182,91 +182,91 @@ _vectors: ISR_HANDLER SWI4_EGU4_IRQHandler ISR_HANDLER SWI5_EGU5_IRQHandler ISR_HANDLER TIMER3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER USBD_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf52833.s b/mdk/ses_startup_nrf52833.s index ffc7b03f1..961748445 100644 --- a/mdk/ses_startup_nrf52833.s +++ b/mdk/ses_startup_nrf52833.s @@ -144,13 +144,13 @@ _vectors: EXC_HANDLER MemoryManagement_Handler EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler @@ -185,8 +185,8 @@ _vectors: ISR_HANDLER TIMER4_IRQHandler ISR_HANDLER PWM0_IRQHandler ISR_HANDLER PDM_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER MWU_IRQHandler ISR_HANDLER PWM1_IRQHandler ISR_HANDLER PWM2_IRQHandler @@ -196,77 +196,77 @@ _vectors: ISR_HANDLER FPU_IRQHandler ISR_HANDLER USBD_IRQHandler ISR_HANDLER UARTE1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER PWM3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER SPIM3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf52840.s b/mdk/ses_startup_nrf52840.s index 613389215..96e7b5cff 100644 --- a/mdk/ses_startup_nrf52840.s +++ b/mdk/ses_startup_nrf52840.s @@ -144,13 +144,13 @@ _vectors: EXC_HANDLER MemoryManagement_Handler EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler @@ -185,8 +185,8 @@ _vectors: ISR_HANDLER TIMER4_IRQHandler ISR_HANDLER PWM0_IRQHandler ISR_HANDLER PDM_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER MWU_IRQHandler ISR_HANDLER PWM1_IRQHandler ISR_HANDLER PWM2_IRQHandler @@ -198,75 +198,75 @@ _vectors: ISR_HANDLER UARTE1_IRQHandler ISR_HANDLER QSPI_IRQHandler ISR_HANDLER CRYPTOCELL_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER PWM3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER SPIM3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf5340_application.s b/mdk/ses_startup_nrf5340_application.s index 5f0eadf9d..636a7a80f 100644 --- a/mdk/ses_startup_nrf5340_application.s +++ b/mdk/ses_startup_nrf5340_application.s @@ -145,24 +145,24 @@ _vectors: EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler EXC_HANDLER SecureFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler /* External Interrupts */ ISR_HANDLER FPU_IRQHandler ISR_HANDLER CACHE_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER SPU_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER CLOCK_POWER_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER SERIAL0_IRQHandler ISR_HANDLER SERIAL1_IRQHandler ISR_HANDLER SPIM4_IRQHandler @@ -173,12 +173,12 @@ _vectors: ISR_HANDLER TIMER0_IRQHandler ISR_HANDLER TIMER1_IRQHandler ISR_HANDLER TIMER2_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER RTC0_IRQHandler ISR_HANDLER RTC1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER WDT0_IRQHandler ISR_HANDLER WDT1_IRQHandler ISR_HANDLER COMP_LPCOMP_IRQHandler @@ -192,209 +192,209 @@ _vectors: ISR_HANDLER PWM1_IRQHandler ISR_HANDLER PWM2_IRQHandler ISR_HANDLER PWM3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER PDM0_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER I2S0_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER IPC_IRQHandler ISR_HANDLER QSPI_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER NFCT_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER GPIOTE1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER QDEC0_IRQHandler ISR_HANDLER QDEC1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER USBD_IRQHandler ISR_HANDLER USBREGULATOR_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER KMU_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER CRYPTOCELL_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf5340_network.s b/mdk/ses_startup_nrf5340_network.s index 413d528f5..53b1d68ac 100644 --- a/mdk/ses_startup_nrf5340_network.s +++ b/mdk/ses_startup_nrf5340_network.s @@ -144,25 +144,25 @@ _vectors: EXC_HANDLER MemoryManagement_Handler EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler /* External Interrupts */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER CLOCK_POWER_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER RADIO_IRQHandler ISR_HANDLER RNG_IRQHandler ISR_HANDLER GPIOTE_IRQHandler @@ -170,120 +170,120 @@ _vectors: ISR_HANDLER TIMER0_IRQHandler ISR_HANDLER ECB_IRQHandler ISR_HANDLER AAR_CCM_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER TEMP_IRQHandler ISR_HANDLER RTC0_IRQHandler ISR_HANDLER IPC_IRQHandler ISR_HANDLER SERIAL0_IRQHandler ISR_HANDLER EGU0_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER RTC1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER TIMER1_IRQHandler ISR_HANDLER TIMER2_IRQHandler ISR_HANDLER SWI0_IRQHandler ISR_HANDLER SWI1_IRQHandler ISR_HANDLER SWI2_IRQHandler ISR_HANDLER SWI3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/ses_startup_nrf9160.s b/mdk/ses_startup_nrf9160.s index 42a4f4ddb..9dd95ad3e 100644 --- a/mdk/ses_startup_nrf9160.s +++ b/mdk/ses_startup_nrf9160.s @@ -145,43 +145,43 @@ _vectors: EXC_HANDLER BusFault_Handler EXC_HANDLER UsageFault_Handler EXC_HANDLER SecureFault_Handler - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER SVC_Handler EXC_HANDLER DebugMon_Handler - ISR_RESERVED /*Reserved */ + ISR_RESERVED /* Reserved */ EXC_HANDLER PendSV_Handler EXC_HANDLER SysTick_Handler /* External Interrupts */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER SPU_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER CLOCK_POWER_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_HANDLER UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler - ISR_HANDLER UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler - ISR_HANDLER UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler - ISR_HANDLER UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + ISR_HANDLER SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + ISR_HANDLER SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + ISR_HANDLER SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER GPIOTE0_IRQHandler ISR_HANDLER SAADC_IRQHandler ISR_HANDLER TIMER0_IRQHandler ISR_HANDLER TIMER1_IRQHandler ISR_HANDLER TIMER2_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER RTC0_IRQHandler ISR_HANDLER RTC1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER WDT_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER EGU0_IRQHandler ISR_HANDLER EGU1_IRQHandler ISR_HANDLER EGU2_IRQHandler @@ -192,209 +192,209 @@ _vectors: ISR_HANDLER PWM1_IRQHandler ISR_HANDLER PWM2_IRQHandler ISR_HANDLER PWM3_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER PDM_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER I2S_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER IPC_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER FPU_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER GPIOTE1_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER KMU_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ ISR_HANDLER CRYPTOCELL_IRQHandler - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ - ISR_RESERVED_DUMMY /*Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ _vectors_end: #ifdef VECTORS_IN_RAM diff --git a/mdk/system_nrf53.h b/mdk/system_nrf53.h new file mode 100644 index 000000000..2981a3c12 --- /dev/null +++ b/mdk/system_nrf53.h @@ -0,0 +1,63 @@ +/* + +Copyright (c) 2009-2022 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF53_H +#define SYSTEM_NRF53_H +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* SYSTEM_NRF53_H */ diff --git a/mdk/system_nrf5340_application.c b/mdk/system_nrf5340_application.c index 40bffe2f2..500449dae 100644 --- a/mdk/system_nrf5340_application.c +++ b/mdk/system_nrf5340_application.c @@ -28,7 +28,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include "nrf.h" #include "nrf_peripherals.h" #include "nrf53_erratas.h" -#include "system_nrf5340_application.h" +#include "system_nrf53.h" #include "system_nrf53_approtect.h" /*lint ++flb "Enter library region" */ diff --git a/mdk/system_nrf5340_network.c b/mdk/system_nrf5340_network.c index eff6b2102..504c88f67 100644 --- a/mdk/system_nrf5340_network.c +++ b/mdk/system_nrf5340_network.c @@ -27,7 +27,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include #include "nrf.h" #include "nrf53_erratas.h" -#include "system_nrf5340_network.h" +#include "system_nrf53.h" #include "system_nrf53_approtect.h" /*lint ++flb "Enter library region" */ diff --git a/mdk/system_nrf91.c b/mdk/system_nrf91.c new file mode 100644 index 000000000..610050005 --- /dev/null +++ b/mdk/system_nrf91.c @@ -0,0 +1,326 @@ +/* + +Copyright (c) 2009-2022 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include +#include +#include "nrf.h" +#include "nrf_peripherals.h" +#include "nrf91_erratas.h" +#include "system_nrf91.h" + +/*lint ++flb "Enter library region" */ + +void SystemStoreFICRNS(); + +#define __SYSTEM_CLOCK (64000000UL) /*!< nRF91 Application core uses a fixed System Clock Frequency of 64MHz */ + +#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \ + (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ + (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \ + (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \ + (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) ) +#define TRACE_TRACECLK_PIN (21) +#define TRACE_TRACEDATA0_PIN (22) +#define TRACE_TRACEDATA1_PIN (23) +#define TRACE_TRACEDATA2_PIN (24) +#define TRACE_TRACEDATA3_PIN (25) + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#endif + +/* Global values used used in Secure mode SystemInit. */ +#if !defined(NRF_TRUSTZONE_NONSECURE) + /* Global values used by UICR erase fix algorithm. */ + static uint32_t uicr_erased_value; + static uint32_t uicr_new_value; +#endif + +/* Errata are only handled in secure mode since they usually need access to FICR. */ +#if !defined(NRF_TRUSTZONE_NONSECURE) + static bool uicr_HFXOSRC_erased(void); + static bool uicr_HFXOCNT_erased(void); + static bool is_empty_word(uint32_t const volatile * word); +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +void SystemInit(void) +{ + #if !defined(NRF_TRUSTZONE_NONSECURE) + /* Perform Secure-mode initialization routines. */ + + /* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled. + * Nordic SPU should handle Secure Attribution tasks */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos); + #endif + + /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_6()){ + NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos); + NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos); + } + + /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_14()){ + *((volatile uint32_t *)0x50004A38) = 0x01ul; + NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; + } + + /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_15()){ + NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; + } + + /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_20()){ + *((volatile uint32_t *)0x5003AEE4) = 0xE; + } + + /* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_31()){ + *((volatile uint32_t *)0x5000470Cul) = 0x0; + *((volatile uint32_t *)0x50004710ul) = 0x1; + } + + #if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM) + SystemStoreFICRNS(); + #endif + + /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim + until one ADDR is not initialized. */ + + for (uint32_t index = 0; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){ + #if defined ( __ICCARM__ ) + #pragma diag_suppress=Pa082 + #endif + *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA; + #if defined ( __ICCARM__ ) + #pragma diag_default=Pa082 + #endif + } + + /* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */ + if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) { + __DSB(); + /* Wait for pending NVMC operations to finish */ + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + /* Enable write mode in NVMC */ + NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + if (uicr_HFXOSRC_erased()){ + /* Write default value to UICR->HFXOSRC */ + uicr_erased_value = NRF_UICR_S->HFXOSRC; + uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; + NRF_UICR_S->HFXOSRC = uicr_new_value; + __DSB(); + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + } + + if (uicr_HFXOCNT_erased()){ + /* Write default value to UICR->HFXOCNT */ + uicr_erased_value = NRF_UICR_S->HFXOCNT; + uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20; + NRF_UICR_S->HFXOCNT = uicr_new_value; + __DSB(); + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + } + + /* Enable read mode in NVMC */ + NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + /* Reset to apply clock select update */ + NVIC_SystemReset(); + } + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) + // Enable Trace And Debug peripheral + NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; + NRF_TAD_S->TASKS_CLOCKSTART = TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk; + + // Set up Trace pads SPU firewall + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN); + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN); + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN); + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN); + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN); + + // Configure trace port pads + NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE; + + // Select trace pins + NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN; + NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN; + NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN; + NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN; + NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN; + + // Set trace port speed to 32 MHz + NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz; + + *((volatile uint32_t *)(0xE0053000ul)) = 0x00000001ul; + + *((volatile uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul; + *((volatile uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul; + *((volatile uint32_t *)(0xE005A004ul)) = 0x00000009ul; + *((volatile uint32_t *)(0xE005A000ul)) = 0x00000303ul; + *((volatile uint32_t *)(0xE005AFB0ul)) = 0x00000000ul; + + *((volatile uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul; + *((volatile uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul; + *((volatile uint32_t *)(0xE005B004ul)) = 0x00003000ul; + *((volatile uint32_t *)(0xE005B000ul)) = 0x00000308ul; + *((volatile uint32_t *)(0xE005BFB0ul)) = 0x00000000ul; + + *((volatile uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul; + *((volatile uint32_t *)(0xE0058000ul)) = 0x00000000ul; + *((volatile uint32_t *)(0xE0058004ul)) = 0x00000000ul; + *((volatile uint32_t *)(0xE0058FB0ul)) = 0x00000000ul; + + /* Rom table does not list ETB, or TPIU base addresses. + * Some debug probes may require manual configuration of these peripherals to enable tracing. + * ETB_BASE = 0xE0051000 + * TPIU_BASE = 0xE0054000 + */ + #endif + + /* Allow Non-Secure code to run FPU instructions. + * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ + SCB->NSACR |= (3UL << 10); + #endif + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + SystemCoreClockUpdate(); +} + + +#if !defined(NRF_TRUSTZONE_NONSECURE) + + bool uicr_HFXOCNT_erased() + { + if (is_empty_word(&NRF_UICR_S->HFXOCNT)) { + return true; + } + return false; + } + + + bool uicr_HFXOSRC_erased() + { + uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC; + __DSB(); + if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { + return true; + } + return false; + } + + bool is_empty_word(uint32_t const volatile * word) + { + uint32_t val = *word; + __DSB(); + return val == 0xFFFFFFFFul; + } +#endif + + +/* Workaround to allow NS code to access FICR. Override NRF_FICR_NS to move FICR_NS buffer. */ +#define FICR_SIZE 0x1000ul +#define RAM_BASE 0x20000000ul +#define RAM_END 0x2FFFFFFFul + +/* Copy FICR_S to FICR_NS RAM region */ +void SystemStoreFICRNS() +{ + if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END) + { + /* FICR_NS is not in RAM. */ + return; + } + /* Copy FICR to NS-accessible RAM block. */ + volatile uint32_t * from = (volatile uint32_t *)((uint32_t)NRF_FICR_S + (FICR_SIZE - sizeof(uint32_t))); + volatile uint32_t * to = (volatile uint32_t *)((uint32_t)NRF_FICR_NS + (FICR_SIZE - sizeof(uint32_t))); + volatile uint32_t * copy_from_end = (volatile uint32_t *)NRF_FICR_S; + while (from >= copy_from_end) + { + *(to--) = *(from--); + } + + /* Make RAM region NS. */ + uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE; + __DSB(); + NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos); +} + +/* Block write and execute access to FICR RAM region */ +void SystemLockFICRNS() +{ + if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END) + { + /* FICR_NS is not in RAM. */ + return; + } + + uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE; + __DSB(); + NRF_SPU_S->RAMREGION[ram_region].PERM &= + ~( + (1 << SPU_RAMREGION_PERM_WRITE_Pos) | + (1 << SPU_RAMREGION_PERM_EXECUTE_Pos) + ); + NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos; +} + +/*lint --flb "Leave library region" */ diff --git a/mdk/system_nrf91.h b/mdk/system_nrf91.h new file mode 100644 index 000000000..e53faa63f --- /dev/null +++ b/mdk/system_nrf91.h @@ -0,0 +1,63 @@ +/* + +Copyright (c) 2009-2022 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF91_H +#define SYSTEM_NRF91_H +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* SYSTEM_NRF91_H */ diff --git a/mdk/system_nrf9160.c b/mdk/system_nrf9160.c index d39ea6661..9ab88b108 100644 --- a/mdk/system_nrf9160.c +++ b/mdk/system_nrf9160.c @@ -1,325 +1,35 @@ /* -Copyright (c) 2009-2022 ARM Limited. All rights reserved. +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. - SPDX-License-Identifier: Apache-2.0 +SPDX-License-Identifier: BSD-3-Clause -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: - www.apache.org/licenses/LICENSE-2.0 +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. -NOTICE: This file has been modified by Nordic Semiconductor ASA. +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. -*/ - -/* NOTE: Template files (including this one) are application specific and therefore expected to - be copied into the application project folder prior to its use! */ - -#include -#include -#include "nrf.h" -#include "nrf_peripherals.h" -#include "nrf91_erratas.h" -#include "system_nrf9160.h" - -/*lint ++flb "Enter library region" */ - -void SystemStoreFICRNS(); - -#define __SYSTEM_CLOCK (64000000UL) /*!< nRF9160 Application core uses a fixed System Clock Frequency of 64MHz */ - -#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \ - (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ - (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \ - (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \ - (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) ) -#define TRACE_TRACECLK_PIN (21) -#define TRACE_TRACEDATA0_PIN (22) -#define TRACE_TRACEDATA1_PIN (23) -#define TRACE_TRACEDATA2_PIN (24) -#define TRACE_TRACEDATA3_PIN (25) - -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#endif - -/* Global values used used in Secure mode SystemInit. */ -#if !defined(NRF_TRUSTZONE_NONSECURE) - /* Global values used by UICR erase fix algorithm. */ - static uint32_t uicr_erased_value; - static uint32_t uicr_new_value; -#endif - -/* Errata are only handled in secure mode since they usually need access to FICR. */ -#if !defined(NRF_TRUSTZONE_NONSECURE) - static bool uicr_HFXOSRC_erased(void); - static bool uicr_HFXOCNT_erased(void); - static bool is_empty_word(uint32_t const volatile * word); -#endif - -void SystemCoreClockUpdate(void) -{ - SystemCoreClock = __SYSTEM_CLOCK; -} - -void SystemInit(void) -{ - #if !defined(NRF_TRUSTZONE_NONSECURE) - /* Perform Secure-mode initialization routines. */ - - /* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled. - * Nordic SPU should handle Secure Attribution tasks */ - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos); - #endif - - /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_6()){ - NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos); - NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos); - } - - /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_14()){ - *((volatile uint32_t *)0x50004A38) = 0x01ul; - NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; - } - - /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_15()){ - NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; - } - - /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_20()){ - *((volatile uint32_t *)0x5003AEE4) = 0xE; - } - - /* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_31()){ - *((volatile uint32_t *)0x5000470Cul) = 0x0; - *((volatile uint32_t *)0x50004710ul) = 0x1; - } - - #if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM) - SystemStoreFICRNS(); - #endif - - /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim - until one ADDR is not initialized. */ - - for (uint32_t index = 0; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){ - #if defined ( __ICCARM__ ) - #pragma diag_suppress=Pa082 - #endif - *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA; - #if defined ( __ICCARM__ ) - #pragma diag_default=Pa082 - #endif - } - - /* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */ - if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) { - /* Wait for pending NVMC operations to finish */ - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - /* Enable write mode in NVMC */ - NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - if (uicr_HFXOSRC_erased()){ - /* Write default value to UICR->HFXOSRC */ - uicr_erased_value = NRF_UICR_S->HFXOSRC; - uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; - NRF_UICR_S->HFXOSRC = uicr_new_value; - __DSB(); - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - } +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. - if (uicr_HFXOCNT_erased()){ - /* Write default value to UICR->HFXOCNT */ - uicr_erased_value = NRF_UICR_S->HFXOCNT; - uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20; - NRF_UICR_S->HFXOCNT = uicr_new_value; - __DSB(); - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - } - - /* Enable read mode in NVMC */ - NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - /* Reset to apply clock select update */ - NVIC_SystemReset(); - } - - /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product - Specification to see which ones). */ - #if defined (ENABLE_TRACE) - // Enable Trace And Debug peripheral - NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; - NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk; - - // Set up Trace pads SPU firewall - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN); - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN); - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN); - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN); - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN); - - // Configure trace port pads - NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE; - NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE; - NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE; - NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE; - NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE; - - // Select trace pins - NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN; - NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN; - NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN; - NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN; - NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN; - - // Set trace port speed to 32 MHz - NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz; - - *((volatile uint32_t *)(0xE0053000ul)) = 0x00000001ul; - - *((volatile uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul; - *((volatile uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul; - *((volatile uint32_t *)(0xE005A004ul)) = 0x00000009ul; - *((volatile uint32_t *)(0xE005A000ul)) = 0x00000303ul; - *((volatile uint32_t *)(0xE005AFB0ul)) = 0x00000000ul; - - *((volatile uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul; - *((volatile uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul; - *((volatile uint32_t *)(0xE005B004ul)) = 0x00003000ul; - *((volatile uint32_t *)(0xE005B000ul)) = 0x00000308ul; - *((volatile uint32_t *)(0xE005BFB0ul)) = 0x00000000ul; - - *((volatile uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul; - *((volatile uint32_t *)(0xE0058000ul)) = 0x00000000ul; - *((volatile uint32_t *)(0xE0058004ul)) = 0x00000000ul; - *((volatile uint32_t *)(0xE0058FB0ul)) = 0x00000000ul; - - /* Rom table does not list ETB, or TPIU base addresses. - * Some debug probes may require manual configuration of these peripherals to enable tracing. - * ETB_BASE = 0xE0051000 - * TPIU_BASE = 0xE0054000 - */ - #endif - - /* Allow Non-Secure code to run FPU instructions. - * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ - SCB->NSACR |= (3UL << 10); - #endif - - /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the - * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit - * operations are not used in your code. */ - #if (__FPU_USED == 1) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); - #endif - - SystemCoreClockUpdate(); -} - - -#if !defined(NRF_TRUSTZONE_NONSECURE) - - bool uicr_HFXOCNT_erased() - { - if (is_empty_word(&NRF_UICR_S->HFXOCNT)) { - return true; - } - return false; - } - - - bool uicr_HFXOSRC_erased() - { - uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC; - __DSB(); - if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { - return true; - } - return false; - } - - bool is_empty_word(uint32_t const volatile * word) - { - uint32_t val = *word; - __DSB(); - return val == 0xFFFFFFFFul; - } -#endif - - -/* Workaround to allow NS code to access FICR. Override NRF_FICR_NS to move FICR_NS buffer. */ -#define FICR_SIZE 0x1000ul -#define RAM_BASE 0x20000000ul -#define RAM_END 0x2FFFFFFFul - -/* Copy FICR_S to FICR_NS RAM region */ -void SystemStoreFICRNS() -{ - if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END) - { - /* FICR_NS is not in RAM. */ - return; - } - /* Copy FICR to NS-accessible RAM block. */ - volatile uint32_t * from = (volatile uint32_t *)((uint32_t)NRF_FICR_S + (FICR_SIZE - sizeof(uint32_t))); - volatile uint32_t * to = (volatile uint32_t *)((uint32_t)NRF_FICR_NS + (FICR_SIZE - sizeof(uint32_t))); - volatile uint32_t * copy_from_end = (volatile uint32_t *)NRF_FICR_S; - while (from >= copy_from_end) - { - *(to--) = *(from--); - } - - /* Make RAM region NS. */ - uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE; - __DSB(); - NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos); -} - -/* Block write and execute access to FICR RAM region */ -void SystemLockFICRNS() -{ - if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END) - { - /* FICR_NS is not in RAM. */ - return; - } - - uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE; - __DSB(); - NRF_SPU_S->RAMREGION[ram_region].PERM &= - ~( - (1 << SPU_RAMREGION_PERM_WRITE_Pos) | - (1 << SPU_RAMREGION_PERM_EXECUTE_Pos) - ); - NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos; -} +*/ -/*lint --flb "Leave library region" */ +#include "system_nrf91.c" diff --git a/soc/nrfx_irqs_nrf9160.h b/soc/nrfx_irqs_nrf9160.h index a40860409..27ef83e4f 100644 --- a/soc/nrfx_irqs_nrf9160.h +++ b/soc/nrfx_irqs_nrf9160.h @@ -44,48 +44,48 @@ extern "C" { // CLOCK_POWER_IRQn #define nrfx_power_clock_irq_handler CLOCK_POWER_IRQHandler -// UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn +// SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) -#define nrfx_prs_box_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler +#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler #else -#define nrfx_spim_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler -#define nrfx_spis_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler -#define nrfx_twim_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler -#define nrfx_twis_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler -#define nrfx_uarte_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define nrfx_uarte_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler #endif -// UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn +// SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) -#define nrfx_prs_box_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler +#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler #else -#define nrfx_spim_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler -#define nrfx_spis_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler -#define nrfx_twim_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler -#define nrfx_twis_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler -#define nrfx_uarte_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler +#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +#define nrfx_uarte_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler #endif -// UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn +// SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) -#define nrfx_prs_box_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler +#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler #else -#define nrfx_spim_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler -#define nrfx_spis_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler -#define nrfx_twim_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler -#define nrfx_twis_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler -#define nrfx_uarte_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler +#define nrfx_spim_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +#define nrfx_spis_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +#define nrfx_twim_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +#define nrfx_twis_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +#define nrfx_uarte_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler #endif -// UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn +// SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) -#define nrfx_prs_box_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler +#define nrfx_prs_box_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler #else -#define nrfx_spim_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler -#define nrfx_spis_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler -#define nrfx_twim_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler -#define nrfx_twis_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler -#define nrfx_uarte_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler +#define nrfx_spim_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +#define nrfx_spis_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +#define nrfx_twim_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +#define nrfx_twis_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +#define nrfx_uarte_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler #endif // GPIOTE0_IRQn diff --git a/templates/nrfx_config.h b/templates/nrfx_config.h index f094a16c1..12a951219 100644 --- a/templates/nrfx_config.h +++ b/templates/nrfx_config.h @@ -34,6 +34,7 @@ #ifndef NRFX_CONFIG_H__ #define NRFX_CONFIG_H__ +#include #if defined(NRF51) #include #elif defined(NRF52805_XXAA) diff --git a/templates/nrfx_config_common.h b/templates/nrfx_config_common.h new file mode 100644 index 000000000..09bf58b47 --- /dev/null +++ b/templates/nrfx_config_common.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2022, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_CONFIG_COMMON_H__ +#define NRFX_CONFIG_COMMON_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + + +// NRFX API version 2.9 flag. When the flag is set NRFX API is compatible with the previous NRFX release. +#define NRFX_CONFIG_API_VER_2_9 1 + +// NRFX API version 2.10 flag. +/* When this flag is set the following changes to the nrfx API will be introduced: + * + * 1. IPC driver: + * - Change input parameters for @ref nrfx_ipc_handler_t + * - Rename function **nrfx_ipc_mem_get** to **nrfx_ipc_gpmem_get**. + */ +#define NRFX_CONFIG_API_VER_2_10 0 + +#endif /* NRFX_CONFIG_COMMON_H__ */