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Incorrect registers in PCIe initialisation code #3

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DualTachyon opened this issue Feb 15, 2024 · 0 comments

DualTachyon commented Feb 15, 2024

In the file arch/arm/mach-rockchip/spl_pcie_ep_boot.c, there's the following 2 register definitions:

#define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0

This has an incorrect offset because xxxx00F0 is the "Region Enable" register. Master registers are from xxxx0040 to xxxx00E8.

#define FIREWALL_PCIE_ACCESS 0xfe586040

This should be 0xfd586040 (SGRF_BUS->SOC_CON16), because 0xfe586xxx doesn't exist on RK3588.

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