references.bib

@article{Adve:1996,
    title={Shared memory consistency models: a tutorial},
    author={Adve, Sarita V and Gharachorloo, Kourosh},
    journal={Computer},
    volume={29},
    number={12},
    pages={66--76},
    month={Dec},
    year={1996},
    publisher={IEEE},
    keywords={data integrity;parallel programming;shared memory systems;software performance evaluation;software portability;computer professionals;hardware-based shared memory systems;performance;performance-enhancing features;portability;program behavior;programmability;programmer-centric;relaxed consistency models;shared memory consistency models;system designers;system optimizations;system-centric;Computer architecture;Hardware;High level languages;Magnetic heads;Message passing;Optimizing compilers;Programming profession;Read-write memory;Software design;Tutorial},
    doi={10.1109/2.546611},
    ISSN={0018-9162},
}

@inproceedings{Wagner:2008,
    title={M{C}jammer: {A}daptive {V}erification for {M}ulti-core {D}esigns},
    author={Wagner, Ilya and Bertacco, Valeria},
    booktitle={Design, Automation, and Test in Europe (DATE)},
    pages={{\color{red}670--675}},
    year={2008},
    keywords={cache storage;formal verification;logic design;multi-agent systems;multiprocessing systems;protocols;MCjammer;adaptive verification;complex protocols;constrained-random generator;cooperating agent distributed network;decision process;memory coherence protocol verification;memory coherence validation;multicore design;multiple level cache;multiprocessor design;system-level protocol;unpredictable software behavior;Computer architecture;Computer bugs;Feedback;Feeds;Formal verification;Frequency;Hardware;Protocols;Software tools;Testing},
    doi={10.1109/DATE.2008.4484755},
    ISSN={1530-1591},
}

@book{Hennessy:2011,
    author = {Hennessy, John L. and Patterson, David A.},
    title = {Computer Architecture: A Quantitative Approach},
    year = {2011},
    isbn = {012383872X, 9780123838728},
    edition = {5th},
    publisher = {Morgan Kaufmann Publishers Inc.},
}

@article{Devadas:2013,
    title={Toward a Coherent Multicore Memory Model},
    author={Devadas, Srinivas},
    journal={Computer},
    number={10},
    pages={30--31},
    year={2013},
    publisher={IEEE},
    doi = {10.1109/MC.2013.373},
}

@inproceedings{Shim:2013,
    title={Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine},
    author={Shim, Keun Sup and Lis, Marcin and Cho, Myong Hyon and Lebedev, Ilya and Devadas, Srinivas},
    booktitle={Computer Design (ICCD), 2013 IEEE 31st International Conference on},
    pages={145--153},
    year={2013},
    organization={IEEE}
}

@inproceedings{Elver:2016, 
    author={M. Elver and V. Nagarajan},
    booktitle={IEEE Int. Symp. on High Performance Computer Architecture (HPCA)},
    title={Mc{V}er{S}i: A test generation framework for fast memory consistency verification in simulation},
    year={2016},
    pages={618--630},
    keywords={digital simulation;formal specification;formal verification;genetic algorithms;parallel programming;program debugging;program testing;shared memory systems;GP;MCM;McVerSi;formal specification;formal verification;full-system simulation;genetic programming;memory consistency model;multiprocessor system;parallel program;program bug;test generation framework;Coherence;Computer bugs;Hardware;Measurement;Pipelines;Protocols;Throughput},
    doi={10.1109/HPCA.2016.7446099},
}

@inproceedings{Rambo:2011,
    author={E. Rambo and O. Henschel and L.C.V. dos Santos},
    booktitle={IEEE Int. Conf. on Electronics, Circuits and Systems (ICECS)},
    title={Automatic generation of memory consistency tests for chip multiprocessing},
    year={2011},
    pages={542--545},
    keywords={formal verification;instruction sets;memory architecture;microprocessor chips;mobile handsets;multi-threading;random sequences;shared memory systems;CMP;MCM checking;automatic generation;chip multiprocessing;computer architecture;memory consistency model;memory consistency tests;multi-threading;personal mobile devices;random instruction sequences;shared memory system;Coherence;Complexity theory;Generators;Instruction sets;Memory management},
}

@inproceedings{Andrade:2016a, 
    author={Gabriel A. G. Andrade and Marleson Graf and Luiz C V dos Santos},
    booktitle={34th IEEE International Conference on Computer Design (ICCD)}, 
    title={{C}hain-{B}ased {P}seudorandom {T}ests for {P}re-{S}ilicon {V}erification of {CMP} {M}emory {S}ystems},
    year={2016}, 
    pages={552--559},
}

@inproceedings{Andrade:2016b, 
    author={Gabriel A. G. Andrade and Marleson Graf and Luiz C V dos Santos},
    booktitle={{\color{red}Ver tese}},
    year={2016},
}

@misc{Gem5:2012,
    title={The Gem5 Simulator},
    titleaddon={A modular platform for computer system architecture research},
    url={www.m5sim.org},
    urlaccessdate={Julho 2012},
}

@inproceedings{Freitas:2013,
    author = {Freitas, Leandro S. and Rambo, Eberle A. and dos Santos, Luiz C. V.},
    title = {On-the-fly Verification of Memory Consistency with Concurrent Relaxed Scoreboards},
    booktitle = {Design, Automation, and Test in Europe (DATE)},
    year = {2013},
    isbn = {978-1-4503-2153-2},
    location = {Grenoble, France},
    pages = {631--636},
    numpages = {6},
}