diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 0000000..03ea6ff --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1,13 @@ +# These are supported funding model platforms + +github: # Replace with up to 4 GitHub Sponsors-enabled usernames e.g., [user1, user2] +patreon: # Replace with a single Patreon username +open_collective: # Replace with a single Open Collective username +ko_fi: # Replace with a single Ko-fi username +tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel +community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry +liberapay: # Replace with a single Liberapay username +issuehunt: # Replace with a single IssueHunt username +otechie: # Replace with a single Otechie username +lfx_crowdfunding: # Replace with a single LFX Crowdfunding project-name e.g., cloud-foundry +custom: ['https://www.paypal.com/donate/?business=BPBZSGK6CK8P8&no_recurring=1¤cy_code=USD'] # Replace with up to 4 custom sponsorship URLs e.g., ['link1', 'link2'] diff --git a/.github/ISSUE_TEMPLATE/bug-report---not-working.md b/.github/ISSUE_TEMPLATE/bug-report---not-working.md new file mode 100644 index 0000000..82c4e0f --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug-report---not-working.md @@ -0,0 +1,35 @@ +--- +name: Bug Report / Not Working +about: Use this if you cannot get the ROM to work. +title: '' +labels: '' +assignees: '' + +--- + +**FIRST** Have you tried with the included scripts? Can you do regular vfio passthrough? Is there a clearly printed error? + +Have you Looked at https://github.com/RotatingFans/i915ovmfPkg/wiki/Having-Problems%3F + +### Description + +### System Info + +- Host OS(Distro/Version) +- CPU +- Any other GPUs +- Guest OS +- GVT-G or GVT-D +- Display connections +- i915ovmfPkg Release version or Commit + +### Qemu command +*If you used one of the included scripts, just note that* + +### Logs + +**Full Log of VM**(From the time you run the qemu command until it exits) + +**Anything in dmesg/syslog** + +**Anything else you have found** diff --git a/.gitignore b/.gitignore index baba4b7..431b31d 100755 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,6 @@ /disk *.o *.rom +i915Install +config +config diff --git a/Notes b/Notes new file mode 100644 index 0000000..d21f103 --- /dev/null +++ b/Notes @@ -0,0 +1,270 @@ +Linux kernel EDID COde: https://github.com/torvalds/linux/blob/faa392181a0bd42c5478175cef601adeecdc91b6/drivers/gpu/drm/drm_edid.c +EDID Wikipedia(Table of values):https://en.wikipedia.org/wiki/Extended_Display_Identification_Data +GMBUS: https://wiki.osdev.org/Intel_HD_Graphics +Intel PRMS https://01.org/linuxgraphics/documentation/hardware-specification-prms + -- Need Volume: Display +Another EFI Software that implements intel graphics: https://www.coreboot.org/developers.html +Display Port Information: https://www.quantumdata.com/assets/displayport_protocols_webinar.pdf +Display Port Training: https://odr.chalmers.se/bitstream/20.500.12380/249904/1/249904.pdf +More Display Port Info: https://www.quantumdata.com/assets/displayport_linklayer_compliance_webinar.pdf + +eDP Power Sequence info: https://books.google.com/books?id=CO2cBAAAQBAJ&pg=PA101&lpg=PA101&dq=edp+t10&source=bl&ots=f-xk9DqpXG&sig=ACfU3U2DYh6su56pJJR9is_zOAqjR2dJhg&hl=en&sa=X&ved=2ahUKEwjBqMyRgcHqAhVxYjUKHWR3CwUQ6AEwBXoECAoQAQ#v=onepage&q=edp%20t10&f=false + +eDP Power Sequence: +Set PP_DIVISOR, PP_ON_DELAYS, PP_OFF_DELAYS to appropriate values(Read Linux kenrel and above rsc for info) Read VOl 2c-2 pg 620(pdf 645) +Trigger Panel On with PP_CONTROL +Read Panel Status with PP_STATUS + + + + +LInux Kernel Method + - COmpute the rate + - If using rate_select, selects from pre-defined rates + - If using Link_rate, rate = rate / 27000 + -Write the LinkConfig to the DP AUX CHannel + + /* Write the link configuration data */ + link_config[0] = link_bw; + link_config[1] = intel_dp->lane_count; + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); + if (!link_bw) + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, + &rate_select, 1); + + - Set DOWNSPREADCTRL link_config[0] = 0; + link_config[1] = DP_SET_ANSI_8B10B; + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); + + --Write the Training Pattern over AUX +buf[0] = dp_train_pat; + if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == + DP_TRAINING_PATTERN_DISABLE) { + /* don't write DP_TRAINING_LANEx_SET on disable */ + len = 1; + } else { + /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ + memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); + len = intel_dp->lane_count + 1; + } + + ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, + buf, len); + + + -Begin Training + Loop + - Dealy set amount: drm_dp_link_train_clock_recovery_delay + - Retrieve Link Status + /* + * Fetch AUX CH registers 0x202 - 0x207 which contain + * link status information + */ +bool +intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]) +{ + return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, + DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; +} +bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count) +{ + int lane; + u8 lane_status; + + for (lane = 0; lane < lane_count; lane++) { + lane_status = dp_get_lane_status(link_status, lane); + if ((lane_status & DP_LANE_CR_DONE) == 0) + return false; + } + return true; +} +EXPORT_SYMBOL(drm_dp_clock_recovery_ok); +/* Helpers for DP link training */ +static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) +{ + return link_status[r - DP_LANE0_1_STATUS]; +} + +static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_LANE0_1_STATUS + (lane >> 1); + int s = (lane & 1) * 4; + u8 l = dp_link_status(link_status, i); + return (l >> s) & 0xf; +} +If failed, try new: +void intel_dp_get_adjust_train(struct intel_dp *intel_dp, + const u8 link_status[DP_LINK_STATUS_SIZE]) +{ + u8 v = 0; + u8 p = 0; + int lane; + u8 voltage_max; + u8 preemph_max; + + for (lane = 0; lane < intel_dp->lane_count; lane++) { + u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); + u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); + + if (this_v > v) + v = this_v; + if (this_p > p) + p = this_p; + } + + voltage_max = intel_dp_voltage_max(intel_dp); + if (v >= voltage_max) + v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; + + preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); + if (p >= preemph_max) + p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; + + for (lane = 0; lane < 4; lane++) + intel_dp->train_set[lane] = v | p; +} +static bool +intel_dp_update_link_train(struct intel_dp *intel_dp) +{ + int ret; + + intel_dp_set_signal_levels(intel_dp); + + ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, + intel_dp->train_set, intel_dp->lane_count); + + return ret == intel_dp->lane_count; +} + + + + + +Display Port Initialization: + DP_TP_CTL_A 64040h + B 64140 + C64240 + D64340 + E64440 + ENable 1 <<31 + ModeSST 0 << 27 + ModeMST 1 << 27 + ForceACT 1 << 25 + SSTENchancedFraming 1 << 18 + DPTrainPattern1 000 to bits 10:8 + DPTrainPat2 001 + DPTrainIDle 010 + DPTRainNorm 011 + DPTrainPat3 100 + AlternateSREnable 1 << 6 + Pre-Program DDI_BUF_TRANS + Refer to table on vol 12 pg 181(pdf 195) for values + DDI_BUF_TRANS_A_* 64E00h-64E4fh + B 64E60h-64EAfh + C 64EC0h-64F0fh + D 64F20h-64F6fh + E 64F80h-64FCfh + Configure DDI-BUF_CTL + DDI_BUF_CTL_A 64000h + DDI_BUF_CTL_b 64100h + DDI_BUF_CTL_c 64200h + DDI_BUF_CTL_d 64300h + DDI_BUF_CTL_e 64400h + DDI_BUF_ENABLE 1 << 31 + DDI_BUF_TRANS_* 000b-1000b bits 27:24 + DDI_BUF_TRANS_9 1001b bits 27:24 + DDI_PORT_LANE_REVERSAL 1 << 16 + DDIA_LANE_CAP 1 << 4 + DDI_PORT_WIDTH bits 3:1 + 000b x1 + 001b x2 + 011b x4 + Wait >518 us + Begin Training Sequence: + Clock Recovery + Start with lowest swing/emph + Send Test pattern + Check AUX for clock recovery + If no recovery try with next highest swing/emph + Repeat 5 times, then lower Lane speed + Repeat until success or max swing/emph on lowest speed + Channel Eq + Start with Prev settings + Send Test and wait delay + Check AUx for success + Use suggested Swing/emph + Repeat until success or 5 times + Lower link speed and Repeat + Fail if lowest bit rate + Set DP_TP_CTL to Normal Pattern +ENable Planes/Pipes for DP + Similar to HDMI + +Panel power: + intel_dp_enable_port(intel_dp, pipe_config); + + edp_panel_vdd_on(intel_dp); + edp_panel_on(intel_dp); + edp_panel_vdd_off(intel_dp, true); + + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u32 pp; + i915_reg_t pp_ctrl_reg; + + lockdep_assert_held(&dev_priv->pps_mutex); + + if (!intel_dp_is_edp(intel_dp)) + return; + + drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n", + dp_to_dig_port(intel_dp)->base.base.base.id, + dp_to_dig_port(intel_dp)->base.base.name); + + if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp), + "[ENCODER:%d:%s] panel power already on\n", + dp_to_dig_port(intel_dp)->base.base.base.id, + dp_to_dig_port(intel_dp)->base.base.name)) + return; + + wait_panel_power_cycle(intel_dp); + + pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + pp = ilk_get_pp_control(intel_dp); + if (IS_GEN(dev_priv, 5)) { + /* ILK workaround: disable reset around power sequence */ + pp &= ~PANEL_POWER_RESET; + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); + } + + pp |= PANEL_POWER_ON; + if (!IS_GEN(dev_priv, 5)) + pp |= PANEL_POWER_RESET; + + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); + + wait_panel_on(intel_dp); + intel_dp->last_power_on = jiffies; + + if (IS_GEN(dev_priv, 5)) { + pp |= PANEL_POWER_RESET; /* restore panel reset bit */ + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); + } + intel_dp_pps_init + + + + + + + + panel->backlight.setup = cnp_setup_backlight; + panel->backlight.enable = cnp_enable_backlight; + panel->backlight.disable = cnp_disable_backlight; + panel->backlight.set = bxt_set_backlight; + panel->backlight.get = bxt_get_backlight; + panel->backlight.hz_to_pwm = cnp_hz_to_pwm; \ No newline at end of file diff --git a/QemuFwCfgLib.c b/QemuFwCfgLib.c index 64d2aca..fee9f80 100755 --- a/QemuFwCfgLib.c +++ b/QemuFwCfgLib.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include "i915_debug.h" #include #include #include @@ -25,7 +25,6 @@ #include "QemuFwCfgLibInternal.h" - /** Selects a firmware configuration item for reading. @@ -36,13 +35,15 @@ **/ VOID -EFIAPI -QemuFwCfgSelectItem ( - IN FIRMWARE_CONFIG_ITEM QemuFwCfgItem - ) + EFIAPI + QemuFwCfgSelectItem( + IN + FIRMWARE_CONFIG_ITEM QemuFwCfgItem) { - DEBUG ((EFI_D_INFO, "Select Item: 0x%x\n", (UINT16)(UINTN) QemuFwCfgItem)); - IoWrite16 (FW_CFG_IO_SELECTOR, (UINT16)(UINTN) QemuFwCfgItem); + DEBUG((EFI_D_INFO, + "Select Item: 0x%x\n", (UINT16)(UINTN)QemuFwCfgItem)); + IoWrite16(FW_CFG_IO_SELECTOR, (UINT16)(UINTN) + QemuFwCfgItem); } /** @@ -53,19 +54,27 @@ QemuFwCfgSelectItem ( **/ VOID -EFIAPI -InternalQemuFwCfgReadBytes ( - IN UINTN Size, - IN VOID *Buffer OPTIONAL - ) + EFIAPI + InternalQemuFwCfgReadBytes( + IN + UINTN Size, + IN + VOID *Buffer + OPTIONAL) { - if (InternalQemuFwCfgDmaIsAvailable () && Size <= MAX_UINT32) { - InternalQemuFwCfgDmaBytes ((UINT32)Size, Buffer, FW_CFG_DMA_CTL_READ); - return; - } - IoReadFifo8 (FW_CFG_IO_DATA, Size, Buffer); -} + if ( + + InternalQemuFwCfgDmaIsAvailable() + && Size <= MAX_UINT32) + { + InternalQemuFwCfgDmaBytes((UINT32) + Size, + Buffer, FW_CFG_DMA_CTL_READ); + return; + } + IoReadFifo8(FW_CFG_IO_DATA, Size, Buffer); +} /** Reads firmware configuration bytes into a buffer @@ -79,17 +88,25 @@ InternalQemuFwCfgReadBytes ( **/ VOID -EFIAPI -QemuFwCfgReadBytes ( - IN UINTN Size, - IN VOID *Buffer - ) + EFIAPI + QemuFwCfgReadBytes( + IN + UINTN Size, + IN + VOID *Buffer) { - if (InternalQemuFwCfgIsAvailable ()) { - InternalQemuFwCfgReadBytes (Size, Buffer); - } else { - ZeroMem (Buffer, Size); - } + if ( + + InternalQemuFwCfgIsAvailable() + + ) + { + InternalQemuFwCfgReadBytes(Size, Buffer); + } + else + { + ZeroMem(Buffer, Size); + } } /** @@ -104,22 +121,34 @@ QemuFwCfgReadBytes ( **/ VOID -EFIAPI -QemuFwCfgWriteBytes ( - IN UINTN Size, - IN VOID *Buffer - ) + EFIAPI + QemuFwCfgWriteBytes( + IN + UINTN Size, + IN + VOID *Buffer) { - if (InternalQemuFwCfgIsAvailable ()) { - if (InternalQemuFwCfgDmaIsAvailable () && Size <= MAX_UINT32) { - InternalQemuFwCfgDmaBytes ((UINT32)Size, Buffer, FW_CFG_DMA_CTL_WRITE); - return; + if ( + + InternalQemuFwCfgIsAvailable() + + ) + { + if ( + + InternalQemuFwCfgDmaIsAvailable() + + && Size <= MAX_UINT32) + { + InternalQemuFwCfgDmaBytes((UINT32) + Size, + Buffer, FW_CFG_DMA_CTL_WRITE); + return; + } + IoWriteFifo8(FW_CFG_IO_DATA, Size, Buffer); } - IoWriteFifo8 (FW_CFG_IO_DATA, Size, Buffer); - } } - /** Skip bytes in the firmware configuration item. @@ -130,39 +159,52 @@ QemuFwCfgWriteBytes ( @param[in] Size Number of bytes to skip. **/ VOID -EFIAPI -QemuFwCfgSkipBytes ( - IN UINTN Size - ) + EFIAPI + QemuFwCfgSkipBytes( + IN + UINTN Size) { - UINTN ChunkSize; - UINT8 SkipBuffer[256]; - - if (!InternalQemuFwCfgIsAvailable ()) { - return; - } - - if (InternalQemuFwCfgDmaIsAvailable () && Size <= MAX_UINT32) { - InternalQemuFwCfgDmaBytes ((UINT32)Size, NULL, FW_CFG_DMA_CTL_SKIP); - return; - } - - // - // Emulate the skip by reading data in chunks, and throwing it away. The - // implementation below is suitable even for phases where RAM or dynamic - // allocation is not available or appropriate. It also doesn't affect the - // static data footprint for client modules. Large skips are not expected, - // therefore this fallback is not performance critical. The size of - // SkipBuffer is thought not to exert a large pressure on the stack in any - // phase. - // - while (Size > 0) { - ChunkSize = MIN (Size, sizeof SkipBuffer); - IoReadFifo8 (FW_CFG_IO_DATA, ChunkSize, SkipBuffer); - Size -= ChunkSize; - } -} + UINTN ChunkSize; + UINT8 SkipBuffer[256]; + if (! + + InternalQemuFwCfgIsAvailable() + + ) + { + return; + } + + if ( + + InternalQemuFwCfgDmaIsAvailable() + + && Size <= MAX_UINT32) + { + InternalQemuFwCfgDmaBytes((UINT32) + Size, + NULL, FW_CFG_DMA_CTL_SKIP); + return; + } + + // + // Emulate the skip by reading data in chunks, and throwing it away. The + // implementation below is suitable even for phases where RAM or dynamic + // allocation is not available or appropriate. It also doesn't affect the + // static data footprint for client modules. Large skips are not expected, + // therefore this fallback is not performance critical. The size of + // SkipBuffer is thought not to exert a large pressure on the stack in any + // phase. + // + while (Size > 0) + { + ChunkSize = MIN(Size, sizeof SkipBuffer); + IoReadFifo8(FW_CFG_IO_DATA, ChunkSize, SkipBuffer); + Size -= + ChunkSize; + } +} /** Reads a UINT8 firmware configuration value @@ -172,18 +214,16 @@ QemuFwCfgSkipBytes ( **/ UINT8 EFIAPI -QemuFwCfgRead8 ( - VOID - ) +QemuFwCfgRead8( + VOID) { - UINT8 Result; + UINT8 Result; - QemuFwCfgReadBytes (sizeof (Result), &Result); + QemuFwCfgReadBytes(sizeof(Result), &Result); - return Result; + return Result; } - /** Reads a UINT16 firmware configuration value @@ -192,18 +232,16 @@ QemuFwCfgRead8 ( **/ UINT16 EFIAPI -QemuFwCfgRead16 ( - VOID - ) +QemuFwCfgRead16( + VOID) { - UINT16 Result; + UINT16 Result; - QemuFwCfgReadBytes (sizeof (Result), &Result); + QemuFwCfgReadBytes(sizeof(Result), &Result); - return Result; + return Result; } - /** Reads a UINT32 firmware configuration value @@ -212,18 +250,16 @@ QemuFwCfgRead16 ( **/ UINT32 EFIAPI -QemuFwCfgRead32 ( - VOID - ) +QemuFwCfgRead32( + VOID) { - UINT32 Result; + UINT32 Result; - QemuFwCfgReadBytes (sizeof (Result), &Result); + QemuFwCfgReadBytes(sizeof(Result), &Result); - return Result; + return Result; } - /** Reads a UINT64 firmware configuration value @@ -232,18 +268,16 @@ QemuFwCfgRead32 ( **/ UINT64 EFIAPI -QemuFwCfgRead64 ( - VOID - ) +QemuFwCfgRead64( + VOID) { - UINT64 Result; + UINT64 Result; - QemuFwCfgReadBytes (sizeof (Result), &Result); + QemuFwCfgReadBytes(sizeof(Result), &Result); - return Result; + return Result; } - /** Find the configuration item corresponding to the firmware configuration file. @@ -259,40 +293,55 @@ QemuFwCfgRead64 ( **/ RETURN_STATUS EFIAPI -QemuFwCfgFindFile ( - IN CONST CHAR8 *Name, - OUT FIRMWARE_CONFIG_ITEM *Item, - OUT UINTN *Size - ) +QemuFwCfgFindFile( + IN + CONST CHAR8 + *Name, + OUT FIRMWARE_CONFIG_ITEM + *Item, + OUT UINTN + *Size) { - UINT32 Count; - UINT32 Idx; - - if (!InternalQemuFwCfgIsAvailable ()) { - return RETURN_UNSUPPORTED; - } - - QemuFwCfgSelectItem (QemuFwCfgItemFileDir); - Count = SwapBytes32 (QemuFwCfgRead32 ()); - - for (Idx = 0; Idx < Count; ++Idx) { - UINT32 FileSize; - UINT16 FileSelect; - UINT16 FileReserved; - CHAR8 FName[QEMU_FW_CFG_FNAME_SIZE]; - - FileSize = QemuFwCfgRead32 (); - FileSelect = QemuFwCfgRead16 (); - FileReserved = QemuFwCfgRead16 (); - (VOID) FileReserved; /* Force a do-nothing reference. */ - InternalQemuFwCfgReadBytes (sizeof (FName), FName); - - if (AsciiStrCmp (Name, FName) == 0) { - *Item = SwapBytes16 (FileSelect); - *Size = SwapBytes32 (FileSize); - return RETURN_SUCCESS; + UINT32 Count; + UINT32 Idx; + + if (! + + InternalQemuFwCfgIsAvailable() + + ) + { + return RETURN_UNSUPPORTED; + } + + QemuFwCfgSelectItem(QemuFwCfgItemFileDir); + Count = SwapBytes32(QemuFwCfgRead32()); + + for ( + Idx = 0; + Idx < Count; + ++Idx) + { + UINT32 FileSize; + UINT16 FileSelect; + UINT16 FileReserved; + CHAR8 FName[QEMU_FW_CFG_FNAME_SIZE]; + + FileSize = QemuFwCfgRead32(); + FileSelect = QemuFwCfgRead16(); + FileReserved = QemuFwCfgRead16(); + (VOID) + FileReserved; /* Force a do-nothing reference. */ + InternalQemuFwCfgReadBytes(sizeof(FName), FName); + + if ( + AsciiStrCmp(Name, FName) == 0) + { + *Item = SwapBytes16(FileSelect); + *Size = SwapBytes32(FileSize); + return RETURN_SUCCESS; + } } - } - return RETURN_NOT_FOUND; + return RETURN_NOT_FOUND; } diff --git a/QemuFwCfgLib.h b/QemuFwCfgLib.h index f6fbede..532ff6c 100755 --- a/QemuFwCfgLib.h +++ b/QemuFwCfgLib.h @@ -20,10 +20,10 @@ #include RETURN_STATUS -EFIAPI + EFIAPI QemuFwCfgInitialize ( - VOID - ); + VOID +); /** Returns a boolean indicating if the firmware configuration interface @@ -36,10 +36,10 @@ QemuFwCfgInitialize ( **/ BOOLEAN -EFIAPI + EFIAPI QemuFwCfgIsAvailable ( - VOID - ); + VOID +); /** @@ -52,10 +52,11 @@ QemuFwCfgIsAvailable ( **/ VOID -EFIAPI + EFIAPI QemuFwCfgSelectItem ( - IN FIRMWARE_CONFIG_ITEM QemuFwCfgItem - ); + IN +FIRMWARE_CONFIG_ITEM QemuFwCfgItem +); /** @@ -70,11 +71,14 @@ QemuFwCfgSelectItem ( **/ VOID -EFIAPI + EFIAPI QemuFwCfgReadBytes ( - IN UINTN Size, - IN VOID *Buffer OPTIONAL - ); + IN +UINTN Size, + IN +VOID *Buffer +OPTIONAL +); /** @@ -89,11 +93,13 @@ QemuFwCfgReadBytes ( **/ VOID -EFIAPI + EFIAPI QemuFwCfgWriteBytes ( - IN UINTN Size, - IN VOID *Buffer - ); + IN +UINTN Size, + IN +VOID *Buffer +); /** @@ -106,10 +112,11 @@ QemuFwCfgWriteBytes ( @param[in] Size Number of bytes to skip. **/ VOID -EFIAPI + EFIAPI QemuFwCfgSkipBytes ( - IN UINTN Size - ); + IN +UINTN Size +); /** @@ -119,10 +126,10 @@ QemuFwCfgSkipBytes ( **/ UINT8 -EFIAPI + EFIAPI QemuFwCfgRead8 ( - VOID - ); + VOID +); /** @@ -132,10 +139,10 @@ QemuFwCfgRead8 ( **/ UINT16 -EFIAPI + EFIAPI QemuFwCfgRead16 ( - VOID - ); + VOID +); /** @@ -145,10 +152,10 @@ QemuFwCfgRead16 ( **/ UINT32 -EFIAPI + EFIAPI QemuFwCfgRead32 ( - VOID - ); + VOID +); /** @@ -158,10 +165,10 @@ QemuFwCfgRead32 ( **/ UINT64 -EFIAPI + EFIAPI QemuFwCfgRead64 ( - VOID - ); + VOID +); /** @@ -178,12 +185,16 @@ QemuFwCfgRead64 ( **/ RETURN_STATUS -EFIAPI + EFIAPI QemuFwCfgFindFile ( - IN CONST CHAR8 *Name, - OUT FIRMWARE_CONFIG_ITEM *Item, - OUT UINTN *Size - ); + IN +CONST CHAR8 +*Name, +OUT FIRMWARE_CONFIG_ITEM +*Item, +OUT UINTN +*Size +); #endif diff --git a/QemuFwCfgLibInternal.h b/QemuFwCfgLibInternal.h index 2ee48c6..23f38e8 100755 --- a/QemuFwCfgLibInternal.h +++ b/QemuFwCfgLibInternal.h @@ -27,9 +27,9 @@ @retval FALSE The interface is not available internally. **/ BOOLEAN -InternalQemuFwCfgIsAvailable ( - VOID - ); + InternalQemuFwCfgIsAvailable( + VOID +); /** @@ -40,9 +40,9 @@ InternalQemuFwCfgIsAvailable ( @retval FALSE The DMA-like access method is unavailable. **/ BOOLEAN -InternalQemuFwCfgDmaIsAvailable ( - VOID - ); + InternalQemuFwCfgDmaIsAvailable( + VOID +); /** Transfer an array of bytes, or skip a number of bytes, using the DMA @@ -60,10 +60,10 @@ InternalQemuFwCfgDmaIsAvailable ( FW_CFG_DMA_CTL_SKIP - skip bytes in fw_cfg. **/ VOID -InternalQemuFwCfgDmaBytes ( - IN UINT32 Size, - IN OUT VOID *Buffer OPTIONAL, - IN UINT32 Control - ); +InternalQemuFwCfgDmaBytes( + IN UINT32 Size, + IN OUT VOID *Buffer OPTIONAL, + IN UINT32 Control +); #endif diff --git a/QemuFwCfgPei.c b/QemuFwCfgPei.c index 462a1c7..5362c09 100755 --- a/QemuFwCfgPei.c +++ b/QemuFwCfgPei.c @@ -17,15 +17,16 @@ #include #include -#include +#include "i915_debug.h" #include #include #include "QemuFwCfgLibInternal.h" -STATIC BOOLEAN mQemuFwCfgSupported = FALSE; -STATIC BOOLEAN mQemuFwCfgDmaSupported; - +STATIC BOOLEAN + mQemuFwCfgSupported = FALSE; +STATIC BOOLEAN + mQemuFwCfgDmaSupported; /** Returns a boolean indicating if the firmware configuration interface @@ -39,65 +40,64 @@ STATIC BOOLEAN mQemuFwCfgDmaSupported; **/ BOOLEAN EFIAPI -QemuFwCfgIsAvailable ( - VOID - ) +QemuFwCfgIsAvailable( + VOID) { - return InternalQemuFwCfgIsAvailable (); + return InternalQemuFwCfgIsAvailable(); } - RETURN_STATUS EFIAPI -QemuFwCfgInitialize ( - VOID - ) +QemuFwCfgInitialize( + VOID) { - UINT32 Signature; - UINT32 Revision; - - // - // Enable the access routines while probing to see if it is supported. - // For probing we always use the IO Port (IoReadFifo8()) access method. - // - mQemuFwCfgSupported = TRUE; - mQemuFwCfgDmaSupported = FALSE; - - QemuFwCfgSelectItem (QemuFwCfgItemSignature); - Signature = QemuFwCfgRead32 (); - DEBUG ((EFI_D_INFO, "FW CFG Signature: 0x%x\n", Signature)); - QemuFwCfgSelectItem (QemuFwCfgItemInterfaceVersion); - Revision = QemuFwCfgRead32 (); - DEBUG ((EFI_D_INFO, "FW CFG Revision: 0x%x\n", Revision)); - if ((Signature != SIGNATURE_32 ('Q', 'E', 'M', 'U')) || - (Revision < 1) - ) { - DEBUG ((EFI_D_INFO, "QemuFwCfg interface not supported.\n")); - mQemuFwCfgSupported = FALSE; - return RETURN_SUCCESS; - } - - if ((Revision & FW_CFG_F_DMA) == 0) { - DEBUG ((DEBUG_INFO, "QemuFwCfg interface (IO Port) is supported.\n")); - } else { - //// - //// If SEV is enabled then we do not support DMA operations in PEI phase. - //// This is mainly because DMA in SEV guest requires using bounce buffer - //// (which need to allocate dynamic memory and allocating a PAGE size'd - //// buffer can be challenge in PEI phase) - //// - //if (MemEncryptSevIsEnabled ()) { - // DEBUG ((DEBUG_INFO, "SEV: QemuFwCfg fallback to IO Port interface.\n")); - //} else { - // mQemuFwCfgDmaSupported = TRUE; - // DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n")); - //} - mQemuFwCfgDmaSupported = TRUE; - } - return RETURN_SUCCESS; + UINT32 Signature; + UINT32 Revision; + + // + // Enable the access routines while probing to see if it is supported. + // For probing we always use the IO Port (IoReadFifo8()) access method. + // + mQemuFwCfgSupported = TRUE; + mQemuFwCfgDmaSupported = FALSE; + + QemuFwCfgSelectItem(QemuFwCfgItemSignature); + Signature = QemuFwCfgRead32(); + DEBUG((EFI_D_INFO, "FW CFG Signature: 0x%x\n", Signature)); + QemuFwCfgSelectItem(QemuFwCfgItemInterfaceVersion); + Revision = QemuFwCfgRead32(); + DEBUG((EFI_D_INFO, "FW CFG Revision: 0x%x\n", Revision)); + if ((Signature != SIGNATURE_32('Q', 'E', 'M', 'U')) || + (Revision < 1)) + { + DEBUG((EFI_D_INFO, "QemuFwCfg interface not supported.\n")); + mQemuFwCfgSupported = FALSE; + return RETURN_SUCCESS; + } + + if ((Revision & FW_CFG_F_DMA) == 0) + { + DEBUG((DEBUG_INFO, "QemuFwCfg interface (IO Port) is supported.\n")); + } + else + { + //// + //// If SEV is enabled then we do not support DMA operations in PEI phase. + //// This is mainly because DMA in SEV guest requires using bounce buffer + //// (which need to allocate dynamic memory and allocating a PAGE size'd + //// buffer can be challenge in PEI phase) + //// + //if (MemEncryptSevIsEnabled ()) { + // DEBUG ((DEBUG_INFO, "SEV: QemuFwCfg fallback to IO Port interface.\n")); + //} else { + // mQemuFwCfgDmaSupported = TRUE; + // DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n")); + //} + mQemuFwCfgDmaSupported = TRUE; + } + return RETURN_SUCCESS; } - /** Returns a boolean indicating if the firmware configuration interface is available for library-internal purposes. @@ -108,11 +108,10 @@ QemuFwCfgInitialize ( @retval FALSE The interface is not available internally. **/ BOOLEAN -InternalQemuFwCfgIsAvailable ( - VOID - ) +InternalQemuFwCfgIsAvailable( + VOID) { - return mQemuFwCfgSupported; + return mQemuFwCfgSupported; } /** @@ -123,11 +122,10 @@ InternalQemuFwCfgIsAvailable ( @retval FALSE The DMA-like access method is unavailable. **/ BOOLEAN -InternalQemuFwCfgDmaIsAvailable ( - VOID - ) +InternalQemuFwCfgDmaIsAvailable( + VOID) { - return mQemuFwCfgDmaSupported; + return mQemuFwCfgDmaSupported; } /** @@ -145,64 +143,64 @@ InternalQemuFwCfgDmaIsAvailable ( FW_CFG_DMA_CTL_READ - read from fw_cfg into Buffer. FW_CFG_DMA_CTL_SKIP - skip bytes in fw_cfg. **/ -VOID -InternalQemuFwCfgDmaBytes ( - IN UINT32 Size, - IN OUT VOID *Buffer OPTIONAL, - IN UINT32 Control - ) +VOID InternalQemuFwCfgDmaBytes( + IN UINT32 Size, + IN OUT VOID *Buffer OPTIONAL, + IN UINT32 Control) { - volatile FW_CFG_DMA_ACCESS Access; - UINT32 AccessHigh, AccessLow; - UINT32 Status; - - ASSERT (Control == FW_CFG_DMA_CTL_WRITE || Control == FW_CFG_DMA_CTL_READ || - Control == FW_CFG_DMA_CTL_SKIP); - - if (Size == 0) { - return; - } - - // - // SEV does not support DMA operations in PEI stage, we should - // not have reached here. - // - ASSERT (!MemEncryptSevIsEnabled ()); - - Access.Control = SwapBytes32 (Control); - Access.Length = SwapBytes32 (Size); - Access.Address = SwapBytes64 ((UINTN)Buffer); - - // - // Delimit the transfer from (a) modifications to Access, (b) in case of a - // write, from writes to Buffer by the caller. - // - MemoryFence (); - - // - // Start the transfer. - // - AccessHigh = (UINT32)RShiftU64 ((UINTN)&Access, 32); - AccessLow = (UINT32)(UINTN)&Access; - IoWrite32 (FW_CFG_IO_DMA_ADDRESS, SwapBytes32 (AccessHigh)); - IoWrite32 (FW_CFG_IO_DMA_ADDRESS + 4, SwapBytes32 (AccessLow)); - - // - // Don't look at Access.Control before starting the transfer. - // - MemoryFence (); - - // - // Wait for the transfer to complete. - // - do { - Status = SwapBytes32 (Access.Control); - ASSERT ((Status & FW_CFG_DMA_CTL_ERROR) == 0); - } while (Status != 0); - - // - // After a read, the caller will want to use Buffer. - // - MemoryFence (); + volatile FW_CFG_DMA_ACCESS Access; + UINT32 AccessHigh, AccessLow; + UINT32 Status; + + ASSERT(Control == FW_CFG_DMA_CTL_WRITE || Control == FW_CFG_DMA_CTL_READ || + Control == FW_CFG_DMA_CTL_SKIP); + + if (Size == 0) + { + return; + } + + // + // SEV does not support DMA operations in PEI stage, we should + // not have reached here. + // + ASSERT(!MemEncryptSevIsEnabled()); + + Access.Control = SwapBytes32(Control); + Access.Length = SwapBytes32(Size); + Access.Address = SwapBytes64((UINTN)Buffer); + + // + // Delimit the transfer from (a) modifications to Access, (b) in case of a + // write, from writes to Buffer by the caller. + // + MemoryFence(); + + // + // Start the transfer. + // + AccessHigh = (UINT32) + RShiftU64((UINTN)&Access, 32); + AccessLow = (UINT32)(UINTN)&Access; + IoWrite32(FW_CFG_IO_DMA_ADDRESS, SwapBytes32(AccessHigh)); + IoWrite32(FW_CFG_IO_DMA_ADDRESS + 4, SwapBytes32(AccessLow)); + + // + // Don't look at Access.Control before starting the transfer. + // + MemoryFence(); + + // + // Wait for the transfer to complete. + // + do + { + Status = SwapBytes32(Access.Control); + ASSERT((Status & FW_CFG_DMA_CTL_ERROR) == 0); + } while (Status != 0); + + // + // After a read, the caller will want to use Buffer. + // + MemoryFence(); } - diff --git a/README.md b/README.md index d0d9d69..3f08365 100755 --- a/README.md +++ b/README.md @@ -1,34 +1,58 @@ +# Archival Notice +As of November 1, 2023 this project is officially archived and I will not be responsible for any past or future support, maintenance, bug fixes, or compatibility troubleshooting. Great wishes to all those who were able to get this working for their needs and thank you to everyone who helped support people to get it working. + +Despite the archival, the code still works for many people. If you try to use it and require assistance or support, please check out the discord server: + +chat on Discord + # VBIOS for Intel GPU Passthrough +This project attempts to create a UEFI driver for the intel integrated GPUS so that they can be used in VFIO Passthrough. Prior to this driver, there was no easy or reliable solution to both virtualized and direct passthrough(GVT-G/D). This driver adds an opRegion for the iGPU to utilize during the Boot Process, allowing for access to the UEFI menus and any other interfaces that are created before an operating system level driver is initialized. As a bonus, this allows for MacOS to boot in this virtual environment. + +## Notice + +*This Software deals directly with the graphics hardware and interfaces. I assume no responsibility should it cause any damage to your GPUs, Cables, Displays, Other hardware, or persons. It has been tested on my personal machine, but **you are using this software at your own risk.*** + Disclaimer: When used in direct passthrough, this VBIOS could produce bad pixel clock that can potentially damage your monitor! Make sure your monitor has protections against that. I'm not responsible for any monitor damage. -## What is this +## Current Feature Support -This is an independent Video BIOS for Intel integrated GPUs. It provides a boot display and sets up an OpRegion so that Windows guests can produce monitor output. +* Boot a virtual intel GPU(GVT-G) +* Passthrough the entire Intel GPU (GVT-D) + * Display Port interfaces + * eDP interfaces, including Laptop Screens + * HDMI interfaces +* Theoretically compatible with any 14nm chip(Skylake, Kaby lake, Coffee Lake, Amber Lake, Whiskey Lake, Comet Lake). +* Auto detect Outputs and types(**NEW**) -The OpRegion code comes from IgdAssignmentDxe and should work everywhere. The boot display works for GVT-g and can safely replace ramfb. For direct passthrough, the boot display only works with the exact combination of an HDMI monitor and an Intel Skylake processor. +## Possible Features to come -## How to build +* Allow for generation Specific Quirks +* Allow for other it to work with other intel CPU Generations. -First, download EDK II and put it in `~/edk2`. Then check out this project to `~/i915ovmfPkg`. Then do some preparation: +## Known Issues -``` -# Create symlink in edk2 -cd -ln -s `pwd`/i915ovmfPkg ../edk2/ -# Create an empty FAT disk image -dd if=/dev/zero of=disk bs=128M count=1 -sudo mkfs.vfat disk -``` +* May have issues with thunderbolt eGPUs. If you encounter problems, try with it unplugged +* GVT-G may struggle with external displays(even if through an eGPU or other GPU) +* May cause random kernel panics with MacOS due to a low default DVMT Pre-allocated memory amount. See [here](https://github.com/patmagauran/i915ovmfPkg/wiki/DVMT-Pre-Alloc---Stolen-Memory-Issues) for more info -Then run `./t` to build and test. Due to GVT-g and EFI shenanigans, the testing process needs root. +## What is this + +This is an independent Video BIOS for Intel integrated GPUs. It provides a boot display and sets up an OpRegion so that Windows guests can produce monitor output. -If you just want to use it for your VM, grab the rom file in Releases. +The OpRegion code comes from IgdAssignmentDxe and should work everywhere. The boot display works for GVT-g and can safely replace ramfb. For direct passthrough, the boot display Works on intel 14nm based CPUS and HDMI/DP/eDP displays(Inlcuding laptop Screens!). + +## Usage + +Please see the Wiki for more information regarding compiling, usage, or further information. ## License I have no idea what this should be licensed in, but the code came from: + - managarm OS: https://github.com/managarm/managarm/ - IgdAssignmentDxe: non-upstreamed Intel patch to OVMF - EDK II: https://github.com/tianocore/edk2 - The Linux kernel +- Intel-gpu-tools: https://cgit.freedesktop.org/xorg/app/intel-gpu-tools/tree/tools diff --git a/Release/iommu.sh b/Release/iommu.sh new file mode 100755 index 0000000..e3559fb --- /dev/null +++ b/Release/iommu.sh @@ -0,0 +1,8 @@ +#!/bin/bash +shopt -s nullglob +for g in /sys/kernel/iommu_groups/*; do + echo "IOMMU Group ${g##*/}:" + for d in $g/devices/*; do + echo -e "\t$(lspci -nns ${d##*/})" + done; +done; \ No newline at end of file diff --git a/Release/test-gvt-d.sh b/Release/test-gvt-d.sh new file mode 100755 index 0000000..d3fd656 --- /dev/null +++ b/Release/test-gvt-d.sh @@ -0,0 +1,22 @@ +#!/bin/bash +export WORKSPACE=/home/patrick/i915dev/Release +export PCILOC=0000:00:02.0 +export PCIID=8086:9bca + +cd $WORKSPACE + +cd ./i915_simple + +# Create an UEFI disk that immediately shuts down the VM when booted +mkdir -p tmpfat +mount disk tmpfat +mkdir -p tmpfat/EFI/BOOT +umount tmpfat +rmdir tmpfat +systemctl stop display-manager.service + echo $PCIID > /sys/bus/pci/drivers/vfio-pci/new_id + echo $PCILOC> /sys/bus/pci/devices/$PCILOC/driver/unbind + echo $PCILOC > /sys/bus/pci/drivers/vfio-pci/bind +#qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -nographic -vga none -serial stdio -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios $WORKSPACE/OVMF_CODE.fd -device vfio-pci,host=$PCILOC,romfile=`pwd`/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk -usb +timeout --foreground -k 1 8 qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -nographic -vga none -chardev stdio,id=char0,logfile=serial.log,signal=off \ + -serial chardev:char0 -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios $WORKSPACE/OVMF_CODE.fd -device vfio-pci,host=$PCILOC,romfile=`pwd`/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk -usb diff --git a/Release/test-gvt-g.sh b/Release/test-gvt-g.sh new file mode 100755 index 0000000..9aa58cd --- /dev/null +++ b/Release/test-gvt-g.sh @@ -0,0 +1,48 @@ +#!/bin/bash +export WORKSPACE=/home/patrick/development +export PCILOC=00:02.0 +export PCIID=8086:9bca +export GVTMODE=i915-GVTg_V5_4 + + +cd ./i915_simple + +if [ -e /sys/bus/pci/devices/0000:$PCILOC/2aee154e-7d0d-11e8-88b8-6f45320c7162 ] +then + true +else + modprobe kvmgt || exit + #sudo dd if=/sys/class/drm/card0-HDMI-A-1/edid of=/sys/class/drm/card0/gvt_edid bs=128 count=1 + echo 2aee154e-7d0d-11e8-88b8-6f45320c7162 > /sys/bus/pci/devices/0000:$PCILOC/mdev_supported_types/$GVTMODE/create || exit +fi + +# Create an UEFI disk that immediately shuts down the VM when booted +mkdir -p tmpfat +mount disk tmpfat +mkdir -p tmpfat/EFI/BOOT +umount tmpfat +rmdir tmpfat + +qemu-system-x86_64 \ + -k en-us \ + -name uefitest,debug-threads=on \ + -serial stdio \ + -m 2048 \ + -M pc \ + -cpu host \ + -global PIIX4_PM.disable_s3=1 \ + -global PIIX4_PM.disable_s4=1 \ + -machine kernel_irqchip=on \ + -nodefaults \ + -rtc base=localtime,driftfix=slew \ + -no-hpet \ + -global kvm-pit.lost_tick_policy=discard \ + -enable-kvm \ + -bios $WORKSPACE/OVMF.fd \ + -display gtk,gl=on,grab-on-hover=on \ + -full-screen \ + -vga none \ + -device vfio-pci,sysfsdev=/sys/bus/pci/devices/0000:$PCILOC/2aee154e-7d0d-11e8-88b8-6f45320c7162,addr=02.0,display=on,x-igd-opregion=on,romfile=`pwd`/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 \ + -device usb-kbd \ + -device usb-tablet \ + -drive format=raw,file=disk diff --git a/bdsmSize.bin b/bdsmSize.bin new file mode 100644 index 0000000..57d9941 Binary files /dev/null and b/bdsmSize.bin differ diff --git a/bind.sh b/bind.sh new file mode 100755 index 0000000..6be0d0f --- /dev/null +++ b/bind.sh @@ -0,0 +1,5 @@ +#!/bin/bash +source ./config + echo $PCILOC > /sys/bus/pci/devices/$PCILOC/driver/unbind + echo $PCILOC > /sys/bus/pci/drivers/i915/bind +systemctl start display-manager.service diff --git a/bindtoi915 b/bindtoi915 new file mode 100644 index 0000000..15e4ac0 --- /dev/null +++ b/bindtoi915 @@ -0,0 +1,5 @@ +#!/bin/bash +source ./config +echo $PCIID >/sys/bus/pci/drivers/i915/new_id +echo $PCILOC >/sys/bus/pci/devices/0000:$PCILOC/driver/unbind +echo $PCILOC >/sys/bus/pci/drivers/i915/bind diff --git a/build.sh b/build.sh new file mode 100755 index 0000000..053a190 --- /dev/null +++ b/build.sh @@ -0,0 +1,11 @@ +#!/bin/bash +source ./config + +export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms + +cd $WORKSPACE +. edk2/edksetup.sh +if [ ! -f "$WORKSPACE/edk2/BaseTools/Source/C/bin" ]; then + make -C edk2/BaseTools +fi +build -v -b DEBUG -p i915ovmfPkg/i915ovmf.dsc || exit diff --git a/clean.sh b/clean.sh new file mode 100755 index 0000000..644268a --- /dev/null +++ b/clean.sh @@ -0,0 +1,7 @@ +#!/bin/bash +source ./config + +export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms + +cd $WORKSPACE +rm -rf Build \ No newline at end of file diff --git a/config b/config new file mode 100644 index 0000000..45fffd7 --- /dev/null +++ b/config @@ -0,0 +1,4 @@ +export WORKSPACE=/change/me +export PCILOC=chan:ge:me.01 +export PCIID=chan:geme +export DefaultGVTMODE=1 \ No newline at end of file diff --git a/i915_controller.h b/i915_controller.h new file mode 100644 index 0000000..4cc91e9 --- /dev/null +++ b/i915_controller.h @@ -0,0 +1,457 @@ +#include +#include +#include +#include "i915_reg.h" +#ifndef INTEL_CONTROLLERH +#define INTEL_CONTROLLERH + +struct opregion_header +{ + UINT8 signature[16]; + UINT32 size; + struct + { + UINT8 rsvd; + UINT8 revision; + UINT8 minor; + UINT8 major; + } __packed over; + UINT8 bios_ver[32]; + UINT8 vbios_ver[16]; + UINT8 driver_ver[16]; + UINT32 mboxes; + UINT32 driver_model; + UINT32 pcon; + UINT8 dver[32]; + UINT8 rsvd[124]; +} __packed; + +/* OpRegion mailbox #1: public ACPI methods */ +struct opregion_acpi +{ + UINT32 drdy; /* driver readiness */ + UINT32 csts; /* notification status */ + UINT32 cevt; /* current event */ + UINT8 rsvd1[20]; + UINT32 didl[8]; /* supported display devices ID list */ + UINT32 cpdl[8]; /* currently presented display list */ + UINT32 cadl[8]; /* currently active display list */ + UINT32 nadl[8]; /* next active devices list */ + UINT32 aslp; /* ASL sleep time-out */ + UINT32 tidx; /* toggle table index */ + UINT32 chpd; /* current hotplug enable indicator */ + UINT32 clid; /* current lid state*/ + UINT32 cdck; /* current docking state */ + UINT32 sxsw; /* Sx state resume */ + UINT32 evts; /* ASL supported events */ + UINT32 cnot; /* current OS notification */ + UINT32 nrdy; /* driver status */ + UINT32 did2[7]; /* extended supported display devices ID list */ + UINT32 cpd2[7]; /* extended attached display devices list */ + UINT8 rsvd2[4]; +} __packed; + +/* OpRegion mailbox #2: SWSCI */ +struct opregion_swsci +{ + UINT32 scic; /* SWSCI command|status|data */ + UINT32 parm; /* command parameters */ + UINT32 dslp; /* driver sleep time-out */ + UINT8 rsvd[244]; +} __packed; + +/* OpRegion mailbox #3: ASLE */ +struct opregion_asle +{ + UINT32 ardy; /* driver readiness */ + UINT32 aslc; /* ASLE interrupt command */ + UINT32 tche; /* technology enabled indicator */ + UINT32 alsi; /* current ALS illuminance reading */ + UINT32 bclp; /* backlight brightness to set */ + UINT32 pfit; /* panel fitting state */ + UINT32 cblv; /* current brightness level */ + UINT16 bclm[20]; /* backlight level duty cycle mapping table */ + UINT32 cpfm; /* current panel fitting mode */ + UINT32 epfm; /* enabled panel fitting modes */ + UINT8 plut[74]; /* panel LUT and identifier */ + UINT32 pfmb; /* PWM freq and min brightness */ + UINT32 cddv; /* color correction default values */ + UINT32 pcft; /* power conservation features */ + UINT32 srot; /* supported rotation angles */ + UINT32 iuer; /* IUER events */ + UINT64 fdss; + UINT32 fdsp; + UINT32 stat; + UINT64 rvda; /* Physical (2.0) or relative from opregion (2.1+) + * address of raw VBT data. */ + UINT32 rvds; /* Size of raw vbt data */ + UINT8 rsvd[58]; +} __packed; + +/* OpRegion mailbox #5: ASLE ext */ +struct opregion_asle_ext +{ + UINT32 phed; /* Panel Header */ + UINT8 bddc[256]; /* Panel EDID */ + UINT8 rsvd[764]; +} __packed; +/** + * struct vbt_header - VBT Header structure + * @signature: VBT signature, always starts with "$VBT" + * @version: Version of this structure + * @header_size: Size of this structure + * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) + * @vbt_checksum: Checksum + * @reserved0: Reserved + * @bdb_offset: Offset of &struct bdb_header from beginning of VBT + * @aim_offset: Offsets of add-in data blocks from beginning of VBT + */ +struct vbt_header +{ + UINT8 signature[20]; + UINT16 version; + UINT16 header_size; + UINT16 vbt_size; + UINT8 vbt_checksum; + UINT8 reserved0; + UINT32 bdb_offset; + UINT32 aim_offset[4]; +} __packed; + +/** + * struct bdb_header - BDB Header structure + * @signature: BDB signature "BIOS_DATA_BLOCK" + * @version: Version of the data block definitions + * @header_size: Size of this structure + * @bdb_size: Size of BDB (BDB Header and data blocks) + */ +struct bdb_header +{ + UINT8 signature[16]; + UINT16 version; + UINT16 header_size; + UINT16 bdb_size; +} __packed; +struct intel_opregion +{ + struct opregion_header *header; + struct opregion_acpi *acpi; + struct opregion_swsci *swsci; + struct opregion_asle *asle; + struct vbt_header *vbt; + struct bdb_header *bdb; + struct opregion_asle_ext *asle_ext; + struct child_device_config *children; + UINT8 numChildren; +}; + +#pragma pack(1) +typedef struct +{ + UINT8 magic[8]; + UINT16 vendorId; + UINT16 productId; + UINT32 serialNumber; + UINT8 manufactureWeek; + UINT8 manufactureYear; + UINT8 structVersion; + UINT8 structRevision; + UINT8 inputParameters; + UINT8 screenWidth; + UINT8 screenHeight; + UINT8 gamma; + UINT8 features; + UINT8 colorCoordinates[10]; + UINT8 estTimings1; + UINT8 estTimings2; + UINT8 vendorTimings; + struct + { + UINT8 resolution; + UINT8 frequency; + } standardTimings[8]; + struct + { + UINT16 pixelClock; + UINT8 horzActive; + UINT8 horzBlank; + UINT8 horzActiveBlankMsb; + UINT8 vertActive; + UINT8 vertBlank; + UINT8 vertActiveBlankMsb; + UINT8 horzSyncOffset; + UINT8 horzSyncPulse; + UINT8 vertSync; + UINT8 syncMsb; + UINT8 dimensionWidth; + UINT8 dimensionHeight; + UINT8 dimensionMsb; + UINT8 horzBorder; + UINT8 vertBorder; + UINT8 features; + } detailTimings[4]; + UINT8 numExtensions; + UINT8 checksum; +} EDID; +#pragma pack() +/* + * The child device config, aka the display device data structure, provides a + * description of a port and its configuration on the platform. + * + * The child device config size has been increased, and fields have been added + * and their meaning has changed over time. Care must be taken when accessing + * basically any of the fields to ensure the correct interpretation for the BDB + * version in question. + * + * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve + * space for the full structure below, and initialize the tail not actually + * present in VBT to zeros. Accessing those fields is fine, as long as the + * default zero is taken into account, again according to the BDB version. + * + * BDB versions 155 and below are considered legacy, and version 155 seems to be + * a baseline for some of the VBT documentation. When adding new fields, please + * include the BDB version when the field was added, if it's above that. + */ +struct child_device_config +{ + UINT16 handle; + UINT16 device_type; /* See DEVICE_TYPE_* above */ + + union + { + UINT8 device_id[10]; /* ascii string */ + struct + { + UINT8 i2c_speed; + UINT8 dp_onboard_redriver; /* 158 */ + UINT8 dp_ondock_redriver; /* 158 */ + UINT8 hdmi_level_shifter_value : 5; /* 169 */ + UINT8 hdmi_max_data_rate : 3; /* 204 */ + UINT16 dtd_buf_ptr; /* 161 */ + UINT8 edidless_efp : 1; /* 161 */ + UINT8 compression_enable : 1; /* 198 */ + UINT8 compression_method : 1; /* 198 */ + UINT8 ganged_edp : 1; /* 202 */ + UINT8 reserved0 : 4; + UINT8 compression_structure_index : 4; /* 198 */ + UINT8 reserved1 : 4; + UINT8 slave_port; /* 202 */ + UINT8 reserved2; + } __packed; + } __packed; + + UINT16 addin_offset; + UINT8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ + UINT8 i2c_pin; + UINT8 slave_addr; + UINT8 ddc_pin; + UINT16 edid_ptr; + UINT8 dvo_cfg; /* See DEVICE_CFG_* above */ + + union + { + struct + { + UINT8 dvo2_port; + UINT8 i2c2_pin; + UINT8 slave2_addr; + UINT8 ddc2_pin; + } __packed; + struct + { + UINT8 efp_routed : 1; /* 158 */ + UINT8 lane_reversal : 1; /* 184 */ + UINT8 lspcon : 1; /* 192 */ + UINT8 iboost : 1; /* 196 */ + UINT8 hpd_invert : 1; /* 196 */ + UINT8 use_vbt_vswing : 1; /* 218 */ + UINT8 flag_reserved : 2; + UINT8 hdmi_support : 1; /* 158 */ + UINT8 dp_support : 1; /* 158 */ + UINT8 tmds_support : 1; /* 158 */ + UINT8 support_reserved : 5; + UINT8 aux_channel; + UINT8 dongle_detect; + } __packed; + } __packed; + + UINT8 pipe_cap : 2; + UINT8 sdvo_stall : 1; /* 158 */ + UINT8 hpd_status : 2; + UINT8 integrated_encoder : 1; + UINT8 capabilities_reserved : 2; + UINT8 dvo_wiring; /* See DEVICE_WIRE_* above */ + + union + { + UINT8 dvo2_wiring; + UINT8 mipi_bridge_type; /* 171 */ + } __packed; + + UINT16 extended_type; + UINT8 dvo_function; + UINT8 dp_usb_type_c : 1; /* 195 */ + UINT8 tbt : 1; /* 209 */ + UINT8 flags2_reserved : 2; /* 195 */ + UINT8 dp_port_trace_length : 4; /* 209 */ + UINT8 dp_gpio_index; /* 195 */ + UINT16 dp_gpio_pin_num; /* 195 */ + UINT8 dp_iboost_level : 4; /* 196 */ + UINT8 hdmi_iboost_level : 4; /* 196 */ + UINT8 dp_max_link_rate : 2; /* 216 CNL+ */ + UINT8 dp_max_link_rate_reserved : 6; /* 216 */ +} __packed; + +struct ddi_vbt_port_info +{ + /* Non-NULL if port present. */ + const struct child_device_config *child; + + int max_tmds_clock; + + /* This is an index in the HDMI/DVI DDI buffer translation table. */ + u8 hdmi_level_shift; + u8 hdmi_level_shift_set : 1; + + u8 supports_dvi : 1; + u8 supports_hdmi : 1; + u8 supports_dp : 1; + u8 supports_edp : 1; + u8 supports_typec_usb : 1; + u8 supports_tbt : 1; + + u8 alternate_aux_channel; + u8 alternate_ddc_pin; + + u8 dp_boost_level; + u8 hdmi_boost_level; + int dp_max_link_rate; /* 0 for not limited by VBT */ + enum port port; +}; +struct edp_power_seq +{ + u16 t1_t3; + u16 t8; + u16 t9; + u16 t10; + u16 t11_t12; +} __packed; +struct intel_vbt_data +{ + //struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ + //struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ + + /* Feature bits */ + unsigned int int_tv_support : 1; + unsigned int lvds_dither : 1; + unsigned int int_crt_support : 1; + unsigned int lvds_use_ssc : 1; + unsigned int int_lvds_support : 1; + unsigned int display_clock_mode : 1; + unsigned int fdi_rx_polarity_inverted : 1; + unsigned int panel_type : 4; + int lvds_ssc_freq; + unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ + //enum drm_panel_orientation orientation; + + // enum drrs_support_type drrs_type; + + struct + { + int rate; + int lanes; + int preemphasis; + int vswing; + bool low_vswing; + bool initialized; + int bpp; + struct edp_power_seq pps; + bool hobl; + } edp; + + // struct { + // bool enable; + // bool full_link; + // bool require_aux_wakeup; + // int idle_frames; + // enum psr_lines_to_wait lines_to_wait; + // int tp1_wakeup_time_us; + // int tp2_tp3_wakeup_time_us; + // int psr2_tp2_tp3_wakeup_time_us; + // } psr; + + // struct { + // u16 pwm_freq_hz; + // bool present; + // bool active_low_pwm; + // u8 min_brightness; /* min_brightness/255 of max */ + // u8 controller; /* brightness controller number */ + // enum intel_backlight_type type; + // } backlight; + + // /* MIPI DSI */ + // struct { + // u16 panel_id; + // struct mipi_config *config; + // struct mipi_pps_data *pps; + // u16 bl_ports; + // u16 cabc_ports; + // u8 seq_version; + // u32 size; + // u8 *data; + // const u8 *sequence[MIPI_SEQ_MAX]; + // u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ + // enum drm_panel_orientation orientation; + // } dsi; + + // int crt_ddc_pin; + + //struct list_head display_devices; + + struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; + //struct sdvo_device_mapping sdvo_mappings[2]; +}; +typedef enum ConnectorTypes +{ + HDMI, + DVI, + VGA, + eDP, + DPSST, + DPMST +} ConnectorType; +typedef struct +{ + UINT64 Signature; + EFI_HANDLE Handle; + EFI_PCI_IO_PROTOCOL *PciIo; + EFI_GRAPHICS_OUTPUT_PROTOCOL GraphicsOutput; + EFI_DEVICE_PATH_PROTOCOL *GopDevicePath; + EDID edid; + EFI_PHYSICAL_ADDRESS FbBase; + UINT32 stride; + UINT32 gmadr; + UINT32 is_gvt; + UINT8 generation; + UINTN fbsize; + void (*write32)(UINT64 reg, UINT32 data); + UINT32 rawclk_freq; + UINT32(*read32) + (UINT64 reg); + + UINT64(*read64) + (UINT64 reg); + struct + { + UINT32 Port; + UINT32 AuxCh; + ConnectorType ConType; + UINT8 DPLL; + UINT32 LinkRate; + UINT8 LaneCount; + } OutputPath; + struct intel_opregion *opRegion; + struct intel_vbt_data vbt; + struct intel_dp *intel_dp; +} i915_CONTROLLER; +#endif \ No newline at end of file diff --git a/i915_ddi.c b/i915_ddi.c new file mode 100644 index 0000000..e69de29 diff --git a/i915_ddi.h b/i915_ddi.h new file mode 100644 index 0000000..e69de29 diff --git a/i915_debug.h b/i915_debug.h new file mode 100644 index 0000000..f4c122c --- /dev/null +++ b/i915_debug.h @@ -0,0 +1,24 @@ +#include + +#ifndef DEBUG_LINE_NUMBER +#define DEBUG_LINE_NUMBER __LINE__ +#endif + +#ifndef PRINT_DEBUG +#ifndef MDEPKG_NDEBUG +//%a is used instead of %s due to specific implementations in edk2. Mainly ASCII vs unicode. +#define PRINT_DEBUG(ERR_LEVEL, ...) \ + do \ + { \ + DebugPrint(ERR_LEVEL, "i915 Message: %a(%d)", __func__, DEBUG_LINE_NUMBER); \ + DebugPrint(ERR_LEVEL, __VA_ARGS__); \ + } while (0) +#else +#define PRINT_DEBUG(ERR_LEVEL, ...) \ + do \ + { \ + DebugPrint(ERR_LEVEL, "i915 Message: "); \ + DebugPrint(ERR_LEVEL, __VA_ARGS__); \ + } while (0) +#endif +#endif \ No newline at end of file diff --git a/i915_display.c b/i915_display.c new file mode 100644 index 0000000..feb7a50 --- /dev/null +++ b/i915_display.c @@ -0,0 +1,812 @@ +#include +#include + +#include "i915_display.h" +#include "intel_opregion.h" +static i915_CONTROLLER *controller; +STATIC UINT8 edid_fallback[] = { + // generic 1280x720 + 0, 255, 255, 255, 255, 255, 255, 0, 34, 240, 84, 41, 1, 0, 0, + 0, 4, 23, 1, 4, 165, 52, 32, 120, 35, 252, 129, 164, 85, 77, + 157, 37, 18, 80, 84, 33, 8, 0, 209, 192, 129, 192, 129, 64, 129, + 128, 149, 0, 169, 64, 179, 0, 1, 1, 26, 29, 0, 128, 81, 208, + 28, 32, 64, 128, 53, 0, 77, 187, 16, 0, 0, 30, 0, 0, 0, + 254, 0, 55, 50, 48, 112, 32, 32, 32, 32, 32, 32, 32, 32, 10, + 0, 0, 0, 253, 0, 24, 60, 24, 80, 17, 0, 10, 32, 32, 32, + 32, 32, 32, 0, 0, 0, 252, 0, 72, 80, 32, 90, 82, 95, 55, + 50, 48, 112, 10, 32, 32, 0, 161 + // the test monitor + // 0,255,255,255,255,255,255,0,6,179,192,39,141,30,0,0,49,26,1,3,128,60,34,120,42,83,165,167,86,82,156,38,17,80,84,191,239,0,209,192,179,0,149,0,129,128,129,64,129,192,113,79,1,1,2,58,128,24,113,56,45,64,88,44,69,0,86,80,33,0,0,30,0,0,0,255,0,71,67,76,77,84,74,48,48,55,56,50,49,10,0,0,0,253,0,50,75,24,83,17,0,10,32,32,32,32,32,32,0,0,0,252,0,65,83,85,83,32,86,90,50,55,57,10,32,32,1,153,2,3,34,113,79,1,2,3,17,18,19,4,20,5,14,15,29,30,31,144,35,9,23,7,131,1,0,0,101,3,12,0,32,0,140,10,208,138,32,224,45,16,16,62,150,0,86,80,33,0,0,24,1,29,0,114,81,208,30,32,110,40,85,0,86,80,33,0,0,30,1,29,0,188,82,208,30,32,184,40,85,64,86,80,33,0,0,30,140,10,208,144,32,64,49,32,12,64,85,0,86,80,33,0,0,24,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,237 +}; + +STATIC INTN g_already_set = 0; + +EFI_STATUS SetupClocks() +{ + EFI_STATUS status; + switch (controller->OutputPath.ConType) + { + case HDMI: + status = SetupClockHDMI(controller); + break; + case eDP: + status = SetupClockeDP(controller); + + break; + case DPSST: + status = SetupClockeDP(controller); + + break; + default: + status = EFI_NOT_FOUND; + break; + } + return status; +} + +EFI_STATUS SetupDDIBuffer() +{ + // intel_prepare_hdmi_ddi_buffers(encoder, level); + // the driver doesn't seem to do this for port A + UINT32 port = controller->OutputPath.Port; + EFI_STATUS status = EFI_NOT_FOUND; + switch (controller->OutputPath.ConType) + { + case HDMI: + + controller->write32(DDI_BUF_TRANS_LO(port, 9), 0x80003015u); + controller->write32(DDI_BUF_TRANS_HI(port, 9), 0xcdu); + + status = EFI_SUCCESS; + + break; + case eDP: + status = SetupDDIBufferDP(controller); + + break; + case DPSST: + status = SetupDDIBufferDP(controller); + + break; + default: + status = EFI_NOT_FOUND; + break; + } + + return status; +} +EFI_STATUS SetupIBoost() +{ + UINT32 port = controller->OutputPath.Port; + + // if (IS_GEN9_BC(dev_priv)) + // skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); + if (controller->OutputPath.ConType == HDMI) + { + UINT32 tmp; + + tmp = controller->read32(DISPIO_CR_TX_BMU_CR0); + tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); + // tmp |= 1 << 24; // temp + tmp |= 1 << BALANCE_LEG_SHIFT(port); + controller->write32(DISPIO_CR_TX_BMU_CR0, tmp); + } + + return EFI_SUCCESS; +} +EFI_STATUS MapTranscoderDDI() +{ + UINT32 port = controller->OutputPath.Port; + if (controller->OutputPath.ConType != eDP) + { + // intel_ddi_enable_pipe_clock(crtc_state); + controller->write32(_TRANS_CLK_SEL_A, TRANS_CLK_SEL_PORT(port)); + PRINT_DEBUG(EFI_D_ERROR, + "i915: progressed to line %d, TRANS_CLK_SEL_PORT(port) is %08x\n", + __LINE__, TRANS_CLK_SEL_PORT(port)); + } + return EFI_SUCCESS; +} +EFI_STATUS SetupTranscoderAndPipe() +{ + PRINT_DEBUG(EFI_D_ERROR, "before TranscoderPipe %u \n", + controller->OutputPath.ConType); + + switch (controller->OutputPath.ConType) + { + case HDMI: + SetupTranscoderAndPipeHDMI(controller); + break; + case DPSST: + SetupTranscoderAndPipeDP(controller); + break; + case DPMST: + SetupTranscoderAndPipeDP(controller); + break; + case eDP: + SetupTranscoderAndPipeEDP(controller); + break; + + default: + break; + } + PRINT_DEBUG(EFI_D_ERROR, "after TranscoderPipe\n"); + + return EFI_SUCCESS; +} +EFI_STATUS ConfigurePipeGamma() +{ + PRINT_DEBUG(EFI_D_ERROR, "before gamma\n"); + for (UINT32 i = 0; i < 256; i++) + { + UINT32 word = (i << 16) | (i << 8) | i; + controller->write32(_LGC_PALETTE_A + i * 4, word); + } + PRINT_DEBUG(EFI_D_ERROR, "before pipe gamma\n"); + + UINT64 reg = _PIPEACONF; + if (controller->OutputPath.ConType == eDP) + { + reg = _PIPEEDPCONF; + } + PRINT_DEBUG(EFI_D_ERROR, "REGISTER %x \n", reg); + controller->write32(reg, PIPECONF_PROGRESSIVE | + PIPECONF_GAMMA_MODE_8BIT); + PRINT_DEBUG(EFI_D_ERROR, "Setting _SKL_BOTTOM_COLOR_A to 0\n"); + + controller->write32(_SKL_BOTTOM_COLOR_A, 0); + PRINT_DEBUG(EFI_D_ERROR, "Setting _GAMMA_MODE_A to %x\n", GAMMA_MODE_MODE_8BIT); + + controller->write32(_GAMMA_MODE_A, GAMMA_MODE_MODE_8BIT); + PRINT_DEBUG(EFI_D_ERROR, "Finished Pipe Gamma\n"); + + return EFI_SUCCESS; +} +EFI_STATUS ConfigureTransMSAMISC() +{ + UINT64 reg = _TRANSA_MSA_MISC; + if (controller->OutputPath.ConType == eDP) + { + reg = _TRANS_EDP_MSA_MISC; + } + controller->write32(reg, TRANS_MSA_SYNC_CLK | + TRANS_MSA_8_BPC); // Sets MSA MISC FIelds for DP + return EFI_SUCCESS; +} +EFI_STATUS ConfigureTransDDI() +{ + UINT32 port = controller->OutputPath.Port; + PRINT_DEBUG(EFI_D_ERROR, "DDI Port: %u \n", port); + switch (controller->OutputPath.ConType) + { + case HDMI: + controller->write32(_TRANS_DDI_FUNC_CTL_A, + (TRANS_DDI_FUNC_ENABLE | TRANS_DDI_SELECT_PORT(port) | + TRANS_DDI_PHSYNC | TRANS_DDI_PVSYNC | TRANS_DDI_BPC_8 | + TRANS_DDI_MODE_SELECT_HDMI)); + break; + case eDP: + controller->write32(_TRANS_DDI_FUNC_CTL_EDP, + (TRANS_DDI_FUNC_ENABLE | TRANS_DDI_SELECT_PORT(port) | + TRANS_DDI_BPC_8 | + TRANS_DDI_MODE_SELECT_DP_SST | ((controller->OutputPath.LaneCount - 1) << 1))); + break; + default: + controller->write32(_TRANS_DDI_FUNC_CTL_A, + (TRANS_DDI_FUNC_ENABLE | TRANS_DDI_SELECT_PORT(port) | + TRANS_DDI_PHSYNC | TRANS_DDI_PVSYNC | TRANS_DDI_BPC_8 | + TRANS_DDI_MODE_SELECT_DP_SST)); + break; + } + PRINT_DEBUG(EFI_D_ERROR, "REG TransDDI: %08x\n", controller->read32(_TRANS_DDI_FUNC_CTL_EDP)); + return EFI_SUCCESS; +} +EFI_STATUS EnablePipe() +{ + UINT64 reg = _PIPEACONF; + if (controller->OutputPath.ConType == eDP) + { + reg = _PIPEEDPCONF; + } + controller->write32(reg, PIPECONF_ENABLE | PIPECONF_PROGRESSIVE | + PIPECONF_GAMMA_MODE_8BIT); + return EFI_SUCCESS; +} +EFI_STATUS EnableDDI() +{ + UINT32 port = controller->OutputPath.Port; + + /* Display WA #1143: skl,kbl,cfl */ + PRINT_DEBUG(EFI_D_ERROR, "DDI_BUF_CTL(port) = %08x\n", + controller->read32(DDI_BUF_CTL(port))); + UINT32 saved_port_bits = + controller->read32(DDI_BUF_CTL(port)) & + (DDI_BUF_PORT_REVERSAL | + DDI_A_4_LANES | (15 << 24)); // FOR HDMI, only port reversal and Lane count matter + if (controller->OutputPath.ConType == HDMI) + { + /* + * For some reason these chicken bits have been + * stuffed into a transcoder register, event though + * the bits affect a specific DDI port rather than + * a specific transcoder. + */ + + // Workaround to get the HSWING to take effect on HDMI Ports. See + // https://patchwork.freedesktop.org/patch/199817/ + UINT32 reg = CHICKEN_TRANS_A; + if (port == PORT_B) + { + reg = CHICKEN_TRANS_A; + } + if (port == PORT_C) + { + reg = CHICKEN_TRANS_B; + } + if (port == PORT_D) + { + reg = CHICKEN_TRANS_C; + } + // if(port==PORT_E){reg = CHICKEN_TRANS_A;} + UINT32 val; + + val = controller->read32(reg); + + if (port == PORT_E) + val |= DDIE_TRAINING_OVERRIDE_ENABLE | DDIE_TRAINING_OVERRIDE_VALUE; + else + val |= DDI_TRAINING_OVERRIDE_ENABLE | DDI_TRAINING_OVERRIDE_VALUE; + + controller->write32(reg, val); + controller->read32(reg); + gBS->Stall(1); + //... don't have timer + + // udelay(1); + + if (port == PORT_E) + val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | DDIE_TRAINING_OVERRIDE_VALUE); + else + val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | DDI_TRAINING_OVERRIDE_VALUE); + + controller->write32(reg, val); + } + + /* In HDMI/DVI mode, the port width, and swing/emphasis values + * are ignored so nothing special needs to be done besides + * enabling the port. + */ + PRINT_DEBUG(EFI_D_ERROR, "SAVED BTIS %08x \n", saved_port_bits); + if (controller->OutputPath.ConType == eDP) + { + saved_port_bits |= ((controller->OutputPath.LaneCount - 1) << 1); + } + controller->write32(DDI_BUF_CTL(port), saved_port_bits | DDI_BUF_CTL_ENABLE); + PRINT_DEBUG(EFI_D_ERROR, "DDI_BUF_CTL(port) = %08x\n", + controller->read32(DDI_BUF_CTL(port))); + + return EFI_SUCCESS; +} +EFI_STATUS SetupAndEnablePlane() +{ + UINT32 horz_active = + controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActive | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION] + .horzActiveBlankMsb >> + 4) + << 8); + UINT32 vert_active = + controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActive | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActiveBlankMsb >> 4) << 8); + // plane + UINT32 stride = (horz_active * 4 + 63) & -64; + controller->stride = stride; + controller->write32(_DSPAOFFSET, 0); + controller->write32(_DSPAPOS, 0); + controller->write32(_DSPASTRIDE, stride >> 6); + controller->write32(_DSPASIZE, (horz_active - 1) | ((vert_active - 1) << 16)); + controller->write32(_DSPACNTR, DISPLAY_PLANE_ENABLE | + PLANE_CTL_FORMAT_XRGB_8888 | + PLANE_CTL_PLANE_GAMMA_DISABLE); + // controller->write32(_DSPACNTR, 0xC4042400); + + controller->write32(_DSPASURF, controller->gmadr); + controller->fbsize = stride * vert_active; + // controller->write32(_DSPAADDR,0); + // word=controller->read32(_DSPACNTR); + // controller->write32(_DSPACNTR,(word&~PLANE_CTL_FORMAT_MASK)|DISPLAY_PLANE_ENABLE|PLANE_CTL_FORMAT_XRGB_8888); + //|PLANE_CTL_ORDER_RGBX + + PRINT_DEBUG(EFI_D_ERROR, "plane enabled, dspcntr: %08x, FbBase: %p\n", + controller->read32(_DSPACNTR), controller->FbBase); + return EFI_SUCCESS; +} +static BOOLEAN isCurrentPortPresent(enum port port, UINT32 found) +{ + switch (port) + { + case PORT_A: + + return controller->read32(DDI_BUF_CTL(PORT_A)) && DDI_INIT_DISPLAY_DETECTED; + case PORT_B: + return found & SFUSE_STRAP_DDIB_DETECTED; + case PORT_C: + return found & SFUSE_STRAP_DDIC_DETECTED; + case PORT_D: + return found & SFUSE_STRAP_DDID_DETECTED; + default: + return false; + } +} +static EFI_STATUS setOutputPath(i915_CONTROLLER *controller, UINT32 found) +{ + EFI_STATUS Status = EFI_SUCCESS; + + if (controller->is_gvt) + { + PRINT_DEBUG(EFI_D_ERROR, "Gvt-g Detected. Trying HDMI with all GMBUS Pins\n"); + + EDID *result; + controller->OutputPath.ConType = HDMI; + controller->OutputPath.DPLL = 1; + + controller->OutputPath.Port = PORT_B; + for (int i = 1; i <= 6; i++) + { + Status = ReadEDIDHDMI(result, controller, i); + if (!Status) + { + controller->edid = *result; + return Status; + } + else + { + Status = ConvertFallbackEDIDToHDMIEDID(result, controller, edid_fallback); + if (!Status) + { + controller->edid = *result; + return Status; + } + } + } + return EFI_NOT_FOUND; + } + for (int i = 0; i < controller->opRegion->numChildren; i++) + { + EDID *result; + + struct ddi_vbt_port_info ddi_port_info = controller->vbt.ddi_port_info[i]; + + PRINT_DEBUG(EFI_D_ERROR, + "Port %c VBT info: DVI:%d HDMI:%d DP:%d eDP:%d\n", + port_name(ddi_port_info.port), ddi_port_info.supports_dvi, + ddi_port_info.supports_hdmi, ddi_port_info.supports_dp, ddi_port_info.supports_edp); + // UINT32* port = &controller->OutputPath.Port; + if (!isCurrentPortPresent(ddi_port_info.port, found)) + { + PRINT_DEBUG(EFI_D_ERROR, "Port not connected\n"); + continue; + } + PRINT_DEBUG(EFI_D_ERROR, "Port Is Connected!\n"); + + if (ddi_port_info.supports_dp || ddi_port_info.supports_edp) + { + struct intel_dp intel_dp = {}; + intel_dp.controller = controller; + controller->intel_dp = &intel_dp; + if (ddi_port_info.supports_edp) + { + Status = SetupPPS(controller); + } + + enum aux_ch portAux = intel_bios_port_aux_ch(controller, ddi_port_info.port); + PRINT_DEBUG(EFI_D_ERROR, "Port is DP/EdP. Aux_ch is %d \n", portAux); + + Status = ReadEDIDDP(result, controller, portAux); + PRINT_DEBUG(EFI_D_ERROR, "ReadEDIDDP returned %d \n", Status); + + if (!Status) + { + + controller->OutputPath.ConType = ddi_port_info.port == PORT_A ? eDP : DPSST; + controller->OutputPath.DPLL = 1; + controller->edid = *result; + controller->OutputPath.Port = ddi_port_info.port; + PRINT_DEBUG(EFI_D_ERROR, "DUsing Connector Mode: %d, On Port %d", controller->OutputPath.ConType, controller->OutputPath.Port); + + return Status; + } + } + if (ddi_port_info.supports_dvi || ddi_port_info.supports_hdmi) + { + PRINT_DEBUG(EFI_D_ERROR, "Port is HDMI. GMBUS Pin is %d \n", ddi_port_info.alternate_ddc_pin); + + Status = ReadEDIDHDMI(result, controller, ddi_port_info.alternate_ddc_pin); + PRINT_DEBUG(EFI_D_ERROR, "ReadEDIDHDMI returned %d \n", Status); + + if (!Status) + { + controller->OutputPath.ConType = HDMI; + controller->OutputPath.DPLL = 1; + controller->edid = *result; + + controller->OutputPath.Port = ddi_port_info.port; + PRINT_DEBUG(EFI_D_ERROR, "HUsing Connector Mode: %d, On Port %d", controller->OutputPath.ConType, controller->OutputPath.Port); + + return Status; + } + } + } + /* + DDI_BUF_CTL_A bit 0 detects presence of DP for DDIA/eDP + SFUSE_STRAP FOR REST + + */ + //TODO: Dynamicly get these + /* controller->OutputPath.ConType = HDMI; + controller->OutputPath.DPLL = 1; + + controller->OutputPath.Port = PORT_B; */ + + return Status; +} + +static void PrintReg(UINT64 reg, const char *name) +{ + PRINT_DEBUG(EFI_D_ERROR, "Reg %a(%08x), val: %08x\n", name, reg, controller->read32(reg)); +} +static void PrintAllRegs() +{ + UINT32 port = controller->OutputPath.Port; + + PrintReg(PP_CONTROL, "PP_CONTROL"); + PrintReg(_BXT_BLC_PWM_FREQ1, "_BXT_BLC_PWM_FREQ1"); + PrintReg(_BXT_BLC_PWM_DUTY1, "_BXT_BLC_PWM_DUTY1"); + PrintReg(PP_STATUS, "PP_STATUS"); + PrintReg(DP_TP_CTL(controller->OutputPath.Port), "DP_TP_CTL"); + PrintReg(_PIPEEDPCONF, "_PIPEEDPCONF"); + PrintReg(_PIPEACONF, "_PIPEACONF"); + PrintReg(_DSPAOFFSET, "_DSPAOFFSET"); + PrintReg(_DSPAPOS, "_DSPAPOS"); + + PrintReg(_DSPASTRIDE, "_DSPASTRIDE"); + PrintReg(_DSPASIZE, "_DSPASIZE"); + PrintReg(_DSPACNTR, "_DSPACNTR"); + PrintReg(_DSPASURF, "_DSPASURF"); + PrintReg(DDI_BUF_CTL(port), "DDI_BUF_CTL"); + PrintReg(_TRANS_DDI_FUNC_CTL_EDP, "_TRANS_DDI_FUNC_CTL_EDP"); + PrintReg(_TRANS_EDP_MSA_MISC, "_TRANS_EDP_MSA_MISC"); + PrintReg(_SKL_BOTTOM_COLOR_A, "_SKL_BOTTOM_COLOR_A"); + PrintReg(_GAMMA_MODE_A, "_GAMMA_MODE_A"); + PrintReg(_LGC_PALETTE_A, "_LGC_PALETTE_A"); + PrintReg(DISPIO_CR_TX_BMU_CR0, "DISPIO_CR_TX_BMU_CR0"); + PrintReg(PP_ON, "PP_ON"); + PrintReg(PP_OFF, "PP_OFF"); + PrintReg(PP_DIVISOR, "PP_DIVISOR"); + PrintReg(DPLL_CTRL1, "DPLL_CTRL1"); + PrintReg(LCPLL2_CTL, "LCPLL2_CTL"); + PrintReg(LCPLL1_CTL, "LCPLL1_CTL"); + PrintReg(DPLL_CTRL2, "DPLL_CTRL2"); + PRINT_DEBUG(EFI_D_ERROR, "Controller: LR: %u, LC: %u, Port: %u, ContType: %u, DPLL: %u\n", + controller->OutputPath.LinkRate, controller->OutputPath.LaneCount, + controller->OutputPath.Port, controller->OutputPath.ConType, controller->OutputPath.DPLL); +} +EFI_STATUS setDisplayGraphicsMode(UINT32 ModeNumber) +{ + EFI_STATUS status; + PRINT_DEBUG(EFI_D_ERROR, "set mode %u\n", ModeNumber); + if (g_already_set > 1) + { + PRINT_DEBUG(EFI_D_ERROR, "mode already set\n"); + goto error; + } + + controller->write32(_PIPEACONF, 0); + controller->write32(_PIPEEDPCONF, 0); + + status = SetupClocks(); + + CHECK_STATUS_ERROR(status); + + status = SetupDDIBuffer(); + + CHECK_STATUS_ERROR(status); + + // intel_hdmi_prepare(encoder, pipe_config);set + // hdmi_reg=DDI_BUF_CTL(port) + + // it's Type C + // icl_enable_phy_clock_gating(dig_port); + // Train Displayport + + if (controller->OutputPath.ConType == eDP || controller->OutputPath.ConType == DPSST) + { + PRINT_DEBUG(EFI_D_ERROR, "PP_CTL: %08x, PP_STAT %08x \n", controller->read32(PP_CONTROL), controller->read32(PP_STATUS)); + + status = TrainDisplayPort(controller); + PRINT_DEBUG(EFI_D_ERROR, "progressed to line %d, status is %u\n", + __LINE__, status); + if (status != EFI_SUCCESS) + { + goto error; + } + } + // status = SetupClocks(); + + status = SetupIBoost(); + + CHECK_STATUS_ERROR(status); + + status = MapTranscoderDDI(); + + CHECK_STATUS_ERROR(status); + + // we got here + + // intel_dig_port->set_infoframes(encoder, + // crtc_state->has_infoframe, + // crtc_state, conn_state); + + // if (intel_crtc_has_dp_encoder(pipe_config)) + // intel_dp_set_m_n(pipe_config, M1_N1); + + // program PIPE_A + status = SetupTranscoderAndPipe(); + + CHECK_STATUS_ERROR(status); + + status = ConfigurePipeGamma(); + + CHECK_STATUS_ERROR(status); + + // bad setup causes hanging when enabling trans / pipe, but what is it? + // we got here + // ddi + PRINT_DEBUG(EFI_D_ERROR, "before DDI\n"); + status = ConfigureTransMSAMISC(); + + CHECK_STATUS_ERROR(status); + status = ConfigureTransDDI(); + + if (status != EFI_SUCCESS) + { + goto error; + } + PRINT_DEBUG(EFI_D_ERROR, "after DDI\n"); + //g_SystemTable->RuntimeServices->ResetSystem(EfiResetShutdown,0,0,NULL); + //return EFI_UNSUPPORTED; + + //test: could be Windows hanging, it's not + //g_SystemTable->RuntimeServices->ResetSystem(EfiResetShutdown,0,0,NULL); + //we failed here + //return EFI_UNSUPPORTED; + + status = EnablePipe(); + + if (status != EFI_SUCCESS) + { + goto error; + } + UINTN TimeOut = 0; + UINT64 reg = _PIPEACONF; + if (controller->OutputPath.ConType == eDP) + { + reg = _PIPEEDPCONF; + } + for (TimeOut = 0; TimeOut <= 100; TimeOut++) + { + + if (controller->read32(reg) & I965_PIPECONF_ACTIVE) + { + PRINT_DEBUG(EFI_D_ERROR, "pipe enabled\n"); + break; + } + gBS->Stall(1000); + } + if (TimeOut > 100) + { + PRINT_DEBUG(EFI_D_ERROR, "failed to enable PIPE\n"); + } + status = EnableDDI(); + PRINT_DEBUG(EFI_D_ERROR, "progressed to line %d, status is%u\n", + __LINE__, status); + if (status != EFI_SUCCESS) + { + goto error; + } + + status = SetupAndEnablePlane(); + + if (status != EFI_SUCCESS) + { + goto error; + } + status = i915GraphicsFramebufferConfigure(controller); + + if (status != EFI_SUCCESS) + { + goto error; + } + status = RETURN_ABORTED; + + controller->write32(PP_CONTROL, 7); + PrintAllRegs(); + + g_already_set++; + return EFI_SUCCESS; + +error: + PRINT_DEBUG(EFI_D_ERROR, "exiting with error"); + return status; +} + +EFI_STATUS DisplayInit(i915_CONTROLLER *iController) +{ + EFI_STATUS Status; + UINTN TimeOut = 0; + controller = iController; + /* 1. Enable PCH reset handshake. */ + // intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + controller->write32(HSW_NDE_RSTWRN_OPT, + controller->read32(HSW_NDE_RSTWRN_OPT) | + RESET_PCH_HANDSHAKE_ENABLE); + + // DOESN'T APPLY + ///* 2-3. */ + // icl_combo_phys_init(dev_priv); + + // if (resume && dev_priv->csr.dmc_payload) + // intel_csr_load_program(dev_priv); + + // power well enable, we are requesting these to be enabled + //#define SKL_PW_CTL_IDX_PW_2 15 + //#define SKL_PW_CTL_IDX_PW_1 14 + //#define SKL_PW_CTL_IDX_DDI_D 4 + //#define SKL_PW_CTL_IDX_DDI_C 3 + //#define SKL_PW_CTL_IDX_DDI_B 2 + //#define SKL_PW_CTL_IDX_DDI_A_E 1 + //#define SKL_PW_CTL_IDX_MISC_IO 0 + controller->write32(HSW_PWR_WELL_CTL1, + controller->read32(HSW_PWR_WELL_CTL1) | 0xA00002AAu); + UINT32 stat; + for (TimeOut = 0; TimeOut <= 5; TimeOut++) + { + UINT32 stat = controller->read32(HSW_PWR_WELL_CTL1); + if (stat & 0x50000155u) + { + PRINT_DEBUG(EFI_D_ERROR, "power well enabled %08x\n", stat); + break; + } + gBS->Stall(1); + } + if (TimeOut > 5) + { + PRINT_DEBUG(EFI_D_ERROR, "power well enabling timed out %08x\n", + stat); + } + + // SetupPPS(); + // //Turn panel on/off to ensure it is properly reset and ready to recieve data. + // PRINT_DEBUG(EFI_D_ERROR, "PP_CTL: %08x, PP_STAT %08x \n", controller->read32(PP_CONTROL), controller->read32(PP_STATUS)); + + // controller->write32(PP_CONTROL, 8); + // controller->write32(PP_CONTROL, 0); + // controller->write32(PP_CONTROL, 8); + // controller->write32(PP_CONTROL, 0); + // controller->write32(PP_CONTROL, 67); + // PRINT_DEBUG(EFI_D_ERROR, "PP_CTL: %08x, PP_STAT %08x \n", controller->read32(PP_CONTROL), controller->read32(PP_STATUS)); + + // gBS->Stall(500000); + // PRINT_DEBUG(EFI_D_ERROR, "PP_CTL: %08x, PP_STAT %08x \n", controller->read32(PP_CONTROL), controller->read32(PP_STATUS)); + //controller->write32(PP_CONTROL, 103); + // disable VGA + UINT32 vgaword = controller->read32(VGACNTRL); + controller->write32(VGACNTRL, (vgaword & ~VGA_2X_MODE) | VGA_DISP_DISABLE); + + ///* 5. Enable CDCLK. */ + // icl_init_cdclk(dev_priv); + // 080002a1 on test machine + PRINT_DEBUG(EFI_D_ERROR, "CDCLK = %08x\n", controller->read32(CDCLK_CTL)); //there seems no need to do so + + ///* 6. Enable DBUF. */ + // icl_dbuf_enable(dev_priv); + controller->write32(DBUF_CTL_S1, + controller->read32(DBUF_CTL_S1) | DBUF_POWER_REQUEST); + controller->write32(DBUF_CTL_S2, + controller->read32(DBUF_CTL_S2) | DBUF_POWER_REQUEST); + controller->read32(DBUF_CTL_S2); + for (UINT32 counter = 0;; counter++) + { + if (counter > 2) + { + PRINT_DEBUG(EFI_D_ERROR, "DBUF timeout\n"); + break; + } + if (controller->read32(DBUF_CTL_S1) & controller->read32(DBUF_CTL_S2) & + DBUF_POWER_STATE) + { + PRINT_DEBUG(EFI_D_ERROR, "DBUF good\n"); + break; + } + gBS->Stall(10); + } + + ///* 7. Setup MBUS. */ + // icl_mbus_init(dev_priv); + controller->write32(MBUS_ABOX_CTL, MBUS_ABOX_BT_CREDIT_POOL1(16) | + MBUS_ABOX_BT_CREDIT_POOL2(16) | + MBUS_ABOX_B_CREDIT(1) | + MBUS_ABOX_BW_CREDIT(1)); + + // set up display buffer + // the value is from host + PRINT_DEBUG(EFI_D_ERROR, "_PLANE_BUF_CFG_1_A = %08x\n", + controller->read32(_PLANE_BUF_CFG_1_A)); + controller->write32(_PLANE_BUF_CFG_1_A, 0x035b0000); + PRINT_DEBUG(EFI_D_ERROR, "_PLANE_BUF_CFG_1_A = %08x (after)\n", + controller->read32(_PLANE_BUF_CFG_1_A)); + + // initialize output + // need workaround: always initialize DDI + // intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); + // intel_ddi_init(PORT_A); + UINT32 found = controller->read32(SFUSE_STRAP); + PRINT_DEBUG(EFI_D_ERROR, "SFUSE_STRAP = %08x\n", found); + Status = setOutputPath(controller, found); + if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR, "failed to Set OutputPath\n"); + return Status; + } + // UINT32* port = &controller->OutputPath.Port; + /* UINT32* port = &(controller->OutputPath.Port); + + *port = PORT_A; + if (found & SFUSE_STRAP_DDIB_DETECTED) + { + *port = PORT_B; //intel_ddi_init(PORT_B); + } + else if (found & SFUSE_STRAP_DDIC_DETECTED) + { + *port = PORT_C; //intel_ddi_init(PORT_C); + } + else if (found & SFUSE_STRAP_DDID_DETECTED) + { + *port = PORT_D; //intel_ddi_init(PORT_D); + } */ + // if (found & SFUSE_STRAP_DDIF_DETECTED) + // intel_ddi_init(dev_priv, PORT_F); + + // reset GMBUS + // intel_i2c_reset(dev_priv); + controller->write32(GMBUS0, 0); + controller->write32(GMBUS4, 0); + + // query EDID and initialize the mode + // it somehow fails on real hardware + // Verified functional on i7-10710U + // Status = ReadEDID(&controller->edid); + if (*(UINT64 *)controller->edid.magic != 0x00FFFFFFFFFFFF00uLL) + { + for (UINT32 i = 0; i < 128; i++) + { + ((UINT8 *)&controller->edid)[i] = edid_fallback[i]; + } + } + /* if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR,"failed to read EDID\n"); + + } */ + PRINT_DEBUG(EFI_D_ERROR, "got EDID:\n"); + for (UINT32 i = 0; i < 16; i++) + { + for (UINT32 j = 0; j < 8; j++) + { + DebugPrint(EFI_D_ERROR, "%02x ", + ((UINT8 *)(&controller->edid))[i * 8 + j]); + } + DebugPrint(EFI_D_ERROR, "\n"); + } + return EFI_SUCCESS; +} diff --git a/i915_display.h b/i915_display.h new file mode 100644 index 0000000..4d9137e --- /dev/null +++ b/i915_display.h @@ -0,0 +1,404 @@ +#pragma once +#ifndef i915_DISPLAYH +#define i915_DISPLAYH +#include +#include "i915_controller.h" +#include "i915_debug.h" +#include "i915_gmbus.h" +#include "i915_ddi.h" +#include "i915_dp.h" +#include "i915_hdmi.h" +#include "i915_reg.h" +#include "i915_gop.h" + +#define VGACNTRL (0x71400) +#define VGA_DISP_DISABLE (1 << 31) +#define VGA_2X_MODE (1 << 30) + +#define _PIPEACONF 0x70008 +#define _PIPEBCONF 0x71008 +#define _PIPEEDPCONF 0x7f008 +#define PIPECONF_ENABLE (1 << 31) +#define PIPECONF_DISABLE 0 +#define PIPECONF_DOUBLE_WIDE (1 << 30) +#define I965_PIPECONF_ACTIVE (1 << 30) +#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */ +#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) +#define PIPECONF_SINGLE_WIDE 0 +#define PIPECONF_PIPE_UNLOCKED 0 +#define PIPECONF_PIPE_LOCKED (1 << 25) +#define PIPECONF_FORCE_BORDER (1 << 25) +#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */ +#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */ +#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */ +#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */ +#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */ +#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */ +#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */ +#define PIPECONF_GAMMA_MODE_SHIFT 24 +#define PIPECONF_INTERLACE_MASK (7 << 21) +#define PIPECONF_INTERLACE_MASK_HSW (3 << 21) +/* Note that pre-gen3 does not support interlaced display directly. Panel + * fitting must be disabled on pre-ilk for interlaced. */ +#define PIPECONF_PROGRESSIVE (0 << 21) +#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ +/* Ironlake and later have a complete new set of values for interlaced. PFIT + * means panel fitter required, PF means progressive fetch, DBL means power + * saving pixel doubling. */ +#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) +#define PIPECONF_INTERLACED_ILK (3 << 21) +#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ +#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ +#define PIPECONF_INTERLACE_MODE_MASK (7 << 21) +#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) +#define PIPECONF_CXSR_DOWNCLOCK (1 << 16) +#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) +#define PIPECONF_COLOR_RANGE_SELECT (1 << 13) +#define PIPECONF_BPC_MASK (0x7 << 5) +#define PIPECONF_8BPC (0 << 5) +#define PIPECONF_10BPC (1 << 5) +#define PIPECONF_6BPC (2 << 5) +#define PIPECONF_12BPC (3 << 5) +#define PIPECONF_DITHER_EN (1 << 4) +#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) +#define PIPECONF_DITHER_TYPE_SP (0 << 2) +#define PIPECONF_DITHER_TYPE_ST1 (1 << 2) +#define PIPECONF_DITHER_TYPE_ST2 (2 << 2) +#define PIPECONF_DITHER_TYPE_TEMP (3 << 2) +#define _PIPEASTAT 0x70024 +#define _PIPEBSTAT 0x71024 +#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) +#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) +#define PIPE_CRC_ERROR_ENABLE (1UL << 29) +#define PIPE_CRC_DONE_ENABLE (1UL << 28) +#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) +#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) +#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) +#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) +#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) +#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) +#define PIPE_DPST_EVENT_ENABLE (1UL << 23) +#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) +#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) +#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) +#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) +#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) +#define PERF_COUNTER_INTERRUPT_EN (1UL << 19) +#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ +#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) +#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) +#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) +#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) +#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) +#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) +#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) +#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) +#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) +#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) +#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) +#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) +#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) +#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) +#define PIPE_DPST_EVENT_STATUS (1UL << 7) +#define PIPE_A_PSR_STATUS_VLV (1UL << 6) +#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) +#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) +#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) +#define PIPE_B_PSR_STATUS_VLV (1UL << 3) +#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) +#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ +#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) +#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) +#define PIPE_HBLANK_INT_STATUS (1UL << 0) +#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) + +#define _DSPACNTR 0x70180 +#define DISPLAY_PLANE_ENABLE (1 << 31) +#define DISPLAY_PLANE_DISABLE 0 +#define PLANE_CTL_FORMAT_MASK (0xf << 24) +#define PLANE_CTL_FORMAT_YUV422 (0 << 24) +#define PLANE_CTL_FORMAT_NV12 (1 << 24) +#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) +#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) +#define PLANE_CTL_ORDER_BGRX (0 << 20) +#define PLANE_CTL_ORDER_RGBX (1 << 20) +#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ +#define PLANE_CTL_ALPHA_DISABLE (0 << 4) +#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4) +#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4) +#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) +#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */ + +#define DISPPLANE_PIXFORMAT_MASK (0xf << 26) +#define DISPPLANE_YUV422 (0x0 << 26) +#define DISPPLANE_8BPP (0x2 << 26) +#define DISPPLANE_BGRA555 (0x3 << 26) +#define DISPPLANE_BGRX555 (0x4 << 26) +#define DISPPLANE_BGRX565 (0x5 << 26) +#define DISPPLANE_BGRX888 (0x6 << 26) +#define DISPPLANE_BGRA888 (0x7 << 26) +#define DISPPLANE_RGBX101010 (0x8 << 26) +#define DISPPLANE_RGBA101010 (0x9 << 26) +#define DISPPLANE_BGRX101010 (0xa << 26) +#define DISPPLANE_RGBX161616 (0xc << 26) +#define DISPPLANE_RGBX888 (0xe << 26) +#define DISPPLANE_RGBA888 (0xf << 26) + +#define _DSPAADDR 0x70184 +#define _DSPASTRIDE 0x70188 +#define _DSPAPOS 0x7018C /* reserved */ +#define _DSPASIZE 0x70190 +#define _DSPASURF 0x7019C /* 965+ only */ +#define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define _DSPAOFFSET 0x701A4 /* HSW */ +#define _DSPASURFLIVE 0x701AC + +#define _TRANSA_MSA_MISC 0x60410 +#define _TRANSB_MSA_MISC 0x61410 +#define _TRANSC_MSA_MISC 0x62410 +#define _TRANS_EDP_MSA_MISC 0x6f410 + +#define TRANS_MSA_SYNC_CLK (1 << 0) +#define TRANS_MSA_SAMPLING_444 (2 << 1) +#define TRANS_MSA_CLRSP_YCBCR (2 << 3) +#define TRANS_MSA_6_BPC (0 << 5) +#define TRANS_MSA_8_BPC (1 << 5) +#define TRANS_MSA_10_BPC (2 << 5) +#define TRANS_MSA_12_BPC (3 << 5) +#define TRANS_MSA_16_BPC (4 << 5) +#define TRANS_MSA_CEA_RANGE (1 << 3) + +#define _TRANS_DDI_FUNC_CTL_A 0x60400 +#define _TRANS_DDI_FUNC_CTL_B 0x61400 +#define _TRANS_DDI_FUNC_CTL_C 0x62400 +#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 +#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 +#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 + +#define TRANS_DDI_FUNC_ENABLE (1 << 31) +/* Those bits are ignored by pipe EDP since it can only connect to DDI A */ +#define TRANS_DDI_PORT_MASK (7 << 28) +#define TRANS_DDI_PORT_SHIFT 28 +#define TRANS_DDI_SELECT_PORT(x) ((x) << 28) +#define TRANS_DDI_PORT_NONE (0 << 28) +#define TRANS_DDI_MODE_SELECT_MASK (7 << 24) +#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) +#define TRANS_DDI_MODE_SELECT_DVI (1 << 24) +#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) +#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) +#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) +#define TRANS_DDI_BPC_MASK (7 << 20) +#define TRANS_DDI_BPC_8 (0 << 20) +#define TRANS_DDI_BPC_10 (1 << 20) +#define TRANS_DDI_BPC_6 (2 << 20) +#define TRANS_DDI_BPC_12 (3 << 20) +#define TRANS_DDI_PVSYNC (1 << 17) +#define TRANS_DDI_PHSYNC (1 << 16) +#define TRANS_DDI_EDP_INPUT_MASK (7 << 12) +#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) +#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) +#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) +#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) +#define TRANS_DDI_HDCP_SIGNALLING (1 << 9) +#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) +#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) +#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) +#define TRANS_DDI_BFI_ENABLE (1 << 4) +#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) +#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) +#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ | TRANS_DDI_HDMI_SCRAMBLING) + +#define _TRANS_DDI_FUNC_CTL2_A 0x60404 +#define _TRANS_DDI_FUNC_CTL2_B 0x61404 +#define _TRANS_DDI_FUNC_CTL2_C 0x62404 +#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 +#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 +#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 +#define PORT_SYNC_MODE_ENABLE (1 << 4) +#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0) +#define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0) +#define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0 + +#define PORT_A 0 +#define PORT_B 1 +#define PORT_C 2 +#define PORT_D 3 +#define PORT_E 4 + +#define _FPA0 (PCH_DISPLAY_BASE + 0x6040) +#define _FPA1 (PCH_DISPLAY_BASE + 0x6044) +#define _FPB0 (PCH_DISPLAY_BASE + 0x6048) +#define _FPB1 (PCH_DISPLAY_BASE + 0x604c) +#define FP_N_DIV_MASK 0x003f0000 +#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 +#define FP_N_DIV_SHIFT 16 +#define FP_M1_DIV_MASK 0x00003f00 +#define FP_M1_DIV_SHIFT 8 +#define FP_M2_DIV_MASK 0x0000003f +#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff +#define FP_M2_DIV_SHIFT 0 + +#define _DPLL_A (PCH_DISPLAY_BASE + 0x6014) +#define _DPLL_B (PCH_DISPLAY_BASE + 0x6018) +#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_SDVO_HIGH_SPEED (1 << 30) +#define DPLL_DVO_2X_MODE (1 << 30) +#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) +#define DPLL_SYNCLOCK_ENABLE (1 << 29) +#define DPLL_REF_CLK_ENABLE_VLV (1 << 29) +#define DPLL_VGA_MODE_DIS (1 << 28) +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +#define DPLL_MODE_MASK (3 << 26) +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ +#define DPLL_LOCK_VLV (1 << 15) +#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) +#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) +#define DPLL_SSC_REF_CLK_CHV (1 << 13) +#define DPLL_PORTC_READY_MASK (0xf << 4) +#define DPLL_PORTB_READY_MASK (0xf) + +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 + +#define PLL_P2_DIVIDE_BY_4 (1 << 23) +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +#define PLL_REF_INPUT_DREFCLK (0 << 13) +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +#define PLL_REF_INPUT_MASK (3 << 13) +#define PLL_LOAD_PULSE_PHASE_SHIFT 9 +/* Ironlake */ + +#define DISPIO_CR_TX_BMU_CR0 (0x6C00C) +/* I_boost values */ +#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) +#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) +/* Balance leg disable bits */ +#define BALANCE_LEG_DISABLE_SHIFT 23 +#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) + +#define _TRANS_CLK_SEL_A 0x46140 +#define _TRANS_CLK_SEL_B 0x46144 +/* For each transcoder, we need to select the corresponding port clock */ +#define TRANS_CLK_SEL_DISABLED (0x0 << 29) +#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) + +#define _LGC_PALETTE_A 0x4a000 +#define _LGC_PALETTE_B 0x4a800 + +#define _SKL_BOTTOM_COLOR_A 0x70034 +#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31) +#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30) + +#define _GAMMA_MODE_A 0x4a480 +#define _GAMMA_MODE_B 0x4ac80 +#define PRE_CSC_GAMMA_ENABLE (1 << 31) +#define POST_CSC_GAMMA_ENABLE (1 << 30) +#define GAMMA_MODE_MODE_8BIT (0 << 0) +#define GAMMA_MODE_MODE_10BIT (1 << 0) +#define GAMMA_MODE_MODE_12BIT (2 << 0) +#define GAMMA_MODE_MODE_SPLIT (3 << 0) + +#define SFUSE_STRAP_FUSE_LOCK (1 << 13) +#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) +#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) +#define SFUSE_STRAP_CRT_DISABLED (1 << 6) +#define SFUSE_STRAP_DDIF_DETECTED (1 << 3) +#define SFUSE_STRAP_DDIB_DETECTED (1 << 2) +#define SFUSE_STRAP_DDIC_DETECTED (1 << 1) +#define SFUSE_STRAP_DDID_DETECTED (1 << 0) + +#define CHICKEN_TRANS_A (0x420c0) +#define CHICKEN_TRANS_B (0x420c4) +#define CHICKEN_TRANS_C (0x420c8) +#define CHICKEN_TRANS_EDP (0x420cc) +#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ +#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) +#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) +#define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */ +#define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */ +#define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15) +#define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12) + +#define HSW_NDE_RSTWRN_OPT (0x46408) +#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) + +#define CDCLK_CTL (0x46000) +#define CDCLK_FREQ_SEL_MASK (3 << 26) +#define CDCLK_FREQ_450_432 (0 << 26) +#define CDCLK_FREQ_540 (1 << 26) +#define CDCLK_FREQ_337_308 (2 << 26) +#define CDCLK_FREQ_675_617 (3 << 26) +#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) +#define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) +#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) +#define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) +#define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) +#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) +#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) +#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) +#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) +#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) +#define CDCLK_FREQ_DECIMAL_MASK (0x7ff) + +#define DBUF_CTL (0x45008) +#define DBUF_CTL_S1 (0x45008) +#define DBUF_CTL_S2 (0x44FE8) +#define DBUF_POWER_REQUEST (1 << 31) +#define DBUF_POWER_STATE (1 << 30) + +#define MBUS_ABOX_CTL (0x45038) +#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) +#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) +#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) +#define MBUS_ABOX_B_CREDIT(x) ((x) << 16) +#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) +#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) +#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) +#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) + +#define _PLANE_BUF_CFG_1_A 0x7027c +#define HSW_PWR_WELL_CTL1 (0x45400) +#define HSW_PWR_WELL_CTL2 (0x45404) +#define HSW_PWR_WELL_CTL3 (0x45408) +#define HSW_PWR_WELL_CTL4 (0x4540C) + +#define CHECK_STATUS_ERROR(status) \ + if (status != EFI_SUCCESS) \ + goto error; + +//intel_limits_i9xx_sdvo +//static const struct intel_limit g_limits = { +// .dot = { .min = 20000, .max = 400000 }, +// .vco = { .min = 1400000, .max = 2800000 }, +// .n = { .min = 1, .max = 6 }, +// .m = { .min = 70, .max = 120 }, +// .m1 = { .min = 8, .max = 18 }, +// .m2 = { .min = 3, .max = 7 }, +// .p = { .min = 5, .max = 80 }, +// .p1 = { .min = 1, .max = 8 }, +// .p2 = { .dot_limit = 200000, +// .p2_slow = 10, .p2_fast = 5 }, +//}; + +/* DPLL cfg */ + +EFI_STATUS DisplayInit(i915_CONTROLLER *iController); + +EFI_STATUS setDisplayGraphicsMode( + UINT32 ModeNumber); +EFI_STATUS TrainDisplayPort(i915_CONTROLLER *controller); +#endif \ No newline at end of file diff --git a/i915_dmesg.log b/i915_dmesg.log new file mode 100644 index 0000000..cf3999e --- /dev/null +++ b/i915_dmesg.log @@ -0,0 +1,2054 @@ +[ 0.000000] Command line: BOOT_IMAGE=(hd0,gpt4)/vmlinuz-5.11.12-300.fc34.x86_64 root=/dev/mapper/linux_install-00 ro resume=/dev/mapper/linux_install-swap rd.lvm.lv=linux_install/00 rd.lvm.lv=linux_install/swap rhgb quiet intel_iommu=on i915.enable_gvt=1 i915.enable_guc=0 iommu=pt drm.debug=0x1e log_buf_len=1M +[ 0.105198] Kernel command line: BOOT_IMAGE=(hd0,gpt4)/vmlinuz-5.11.12-300.fc34.x86_64 root=/dev/mapper/linux_install-00 ro resume=/dev/mapper/linux_install-swap rd.lvm.lv=linux_install/00 rd.lvm.lv=linux_install/swap rhgb quiet intel_iommu=on i915.enable_gvt=1 i915.enable_guc=0 iommu=pt drm.debug=0x1e log_buf_len=1M +[ 2.639240] i915 0000:00:02.0: enabling device (0006 -> 0007) +[ 2.639380] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] WOPCM: 1024K +[ 2.639445] i915 0000:00:02.0: [drm:intel_uc_init_early [i915]] enable_guc=0 (guc:no submission:no huc:no) +[ 2.639517] i915 0000:00:02.0: [drm:i915_gem_init_early [i915]] fake context support initialized +[ 2.639586] i915 0000:00:02.0: [drm:intel_pch_type [i915]] Found Comet Lake PCH (CMP) +[ 2.639640] i915 0000:00:02.0: [drm:intel_power_domains_init [i915]] Allowed DC state mask 02 +[ 2.639745] i915 0000:00:02.0: [drm:intel_uncore_init_mmio [i915]] unclaimed mmio detected on uncore init, clearing +[ 2.640085] i915 0000:00:02.0: [drm:intel_device_info_runtime_init [i915]] rawclk rate: 24000 kHz +[ 2.640139] i915 0000:00:02.0: [drm:intel_device_info_runtime_init [i915]] CS timestamp wraparound in 178241ms +[ 2.640209] i915 0000:00:02.0: [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M +[ 2.640269] i915 0000:00:02.0: [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M +[ 2.640325] i915 0000:00:02.0: [drm:i915_ggtt_probe_hw [i915]] DSM size = 64M +[ 2.640380] i915 0000:00:02.0: [drm] VT-d active for gfx access +[ 2.640419] i915 0000:00:02.0: vgaarb: deactivate vga console +[ 2.640451] i915 0000:00:02.0: [drm:init_stolen [i915]] GEN6_STOLEN_RESERVED = 7f700047 +[ 2.640569] i915 0000:00:02.0: [drm:init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K +[ 2.640676] [drm:i915_driver_probe [i915]] Initialized 4 GT workarounds on global +[ 2.640959] i915 0000:00:02.0: Direct firmware load for i915/gvt/vid_0x8086_did_0x9bca_rid_0x04.golden_hw_state failed with error -2 +[ 2.660833] i915 0000:00:02.0: [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79880018 +[ 2.660980] i915 0000:00:02.0: [drm:intel_opregion_setup [i915]] ACPI OpRegion version 2.0.0 +[ 2.661076] i915 0000:00:02.0: [drm:intel_opregion_setup [i915]] Public ACPI methods supported +[ 2.661167] i915 0000:00:02.0: [drm:intel_opregion_setup [i915]] SWSCI supported +[ 2.661882] i915 0000:00:02.0: [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300583 +[ 2.661961] i915 0000:00:02.0: [drm:intel_opregion_setup [i915]] ASLE supported +[ 2.662038] i915 0000:00:02.0: [drm:intel_opregion_setup [i915]] ASLE extension supported +[ 2.662116] i915 0000:00:02.0: [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4) +[ 2.662202] i915 0000:00:02.0: [drm:intel_dram_detect [i915]] DRAM type: LPDDR3 +[ 2.662274] i915 0000:00:02.0: [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM L size: 64 Gb, width: X16, ranks: 2, 16Gb DIMMs: no +[ 2.662342] i915 0000:00:02.0: [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM S size: 0 Gb, width: X0, ranks: 0, 16Gb DIMMs: no +[ 2.662395] i915 0000:00:02.0: [drm:skl_dram_get_channel_info [i915]] CH0 ranks: 2, 16Gb DIMMs: no +[ 2.662459] i915 0000:00:02.0: [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM L size: 64 Gb, width: X16, ranks: 2, 16Gb DIMMs: no +[ 2.662524] i915 0000:00:02.0: [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM S size: 0 Gb, width: X0, ranks: 0, 16Gb DIMMs: no +[ 2.662574] i915 0000:00:02.0: [drm:skl_dram_get_channel_info [i915]] CH1 ranks: 2, 16Gb DIMMs: no +[ 2.662637] i915 0000:00:02.0: [drm:intel_dram_detect [i915]] Memory configuration is symmetric? yes +[ 2.662700] i915 0000:00:02.0: [drm:intel_dram_detect [i915]] DRAM bandwidth: 34133344 kBps, channels: 2 +[ 2.662750] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] DRAM ranks: 2, 16Gb DIMMs: no +[ 2.662955] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz +[ 2.663037] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE ", BDB version 228 +[ 2.663119] i915 0000:00:02.0: [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 +[ 2.663205] i915 0000:00:02.0: [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 +[ 2.663282] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Found VBT child device with type 0x1806 +[ 2.663360] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 +[ 2.663435] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Found VBT child device with type 0x68c6 +[ 2.663829] i915 0000:00:02.0: [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0) +[ 2.663915] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Panel type: 2 (VBT) +[ 2.663999] i915 0000:00:02.0: [drm:intel_bios_init [i915]] DRRS supported mode is static +[ 2.664078] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT legacy lfp table: +[ 2.664200] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT initial LVDS value 300 +[ 2.664277] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 990 Hz, active high, min brightness 3, level 63, controller 0 +[ 2.664357] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Skipping SDVO device mapping +[ 2.664432] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Port A VBT info: CRT:0 DVI:0 HDMI:0 DP:1 eDP:1 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 +[ 2.664510] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0 +[ 2.664585] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT DP max link rate for port A: 810000 +[ 2.664661] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 +[ 2.664737] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 0 +[ 2.664812] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT DP max link rate for port B: 810000 +[ 2.664886] i915 0000:00:02.0: [drm:intel_bios_init [i915]] Port C VBT info: CRT:0 DVI:0 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 +[ 2.664962] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 0 +[ 2.665039] i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT DP max link rate for port C: 810000 +[ 2.665116] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 +[ 2.665204] i915 0000:00:02.0: [drm:intel_power_domains_init_hw [i915]] enabling power well 1 +[ 2.665287] i915 0000:00:02.0: [drm:intel_power_domains_init_hw [i915]] enabling MISC IO power well +[ 2.665370] [drm:intel_cdclk_init_hw [i915]] Current CDCLK 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0 +[ 2.665452] i915 0000:00:02.0: [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz +[ 2.665530] i915 0000:00:02.0: [drm:intel_power_domains_init_hw [i915]] Max dotclock rate: 675000 kHz +[ 2.665610] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x1 +[ 2.665700] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling always-on +[ 2.665776] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 2.665872] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 +[ 2.665992] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling power well 2 +[ 2.666077] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=mem +[ 2.666081] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DDI A/E IO power well +[ 2.666167] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DDI B IO power well +[ 2.666335] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DDI C IO power well +[ 2.666445] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DDI D IO power well +[ 2.666564] i915 0000:00:02.0: [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_04.bin +[ 2.667909] i915 0000:00:02.0: [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1 +[ 2.668455] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec) +[ 2.668561] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_04.bin (v1.4) +[ 2.668544] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec) +[ 2.668600] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec) +[ 2.668654] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec) +[ 2.668707] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec) +[ 2.668760] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec) +[ 2.668812] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec) +[ 2.668864] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec) +[ 2.670865] i915 0000:00:02.0: [drm:intel_modeset_init_nogem [i915]] 3 display pipes available. +[ 2.670979] [drm:intel_dump_cdclk_config [i915]] Current CDCLK 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0 +[ 2.671354] i915 0000:00:02.0: [drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT) +[ 2.671426] i915 0000:00:02.0: [drm:intel_dp_init_connector [i915]] Adding eDP connector on [ENCODER:94:DDI A/PHY A] +[ 2.671573] [drm:intel_dp_init_panel_power_sequencer [i915]] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 6000 +[ 2.671644] [drm:intel_dp_init_panel_power_sequencer [i915]] vbt t1_t3 2000 t8 10 t9 2600 t10 500 t11_t12 6000 +[ 2.671713] i915 0000:00:02.0: [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 600 +[ 2.671798] i915 0000:00:02.0: [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 260 +[ 2.672029] i915 0000:00:02.0: [drm:intel_dp_init_connector [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60 +[ 2.672145] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD on +[ 2.672374] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f +[ 2.673710] i915 0000:00:02.0: [drm:intel_dp_init_connector [i915]] eDP DPCD: 02 8b 03 +[ 2.674126] i915 0000:00:02.0: [drm:intel_psr_init_dpcd [i915]] eDP panel supports PSR version 1 +[ 2.678326] i915 0000:00:02.0: [drm:intel_panel_edid_fixed_mode [i915]] [CONNECTOR:95:eDP-1] using preferred mode from EDID: +[ 2.678416] i915 0000:00:02.0: [drm:intel_dp_init_connector [i915]] VBT doesn't support DRRS +[ 2.678485] i915 0000:00:02.0: [drm:intel_dp_aux_init_backlight_funcs [i915]] AUX Backlight Control Supported! +[ 2.678552] i915 0000:00:02.0: [drm] Panel advertises DPCD backlight support, but VBT disagrees. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=1. If your machine needs this, please file a _new_ bug report on drm/i915, see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details. +[ 2.678642] i915 0000:00:02.0: [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, enabled, brightness 5989/24242 +[ 2.678784] i915 0000:00:02.0: [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (VBT) +[ 2.678860] i915 0000:00:02.0: [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:102:DDI B/PHY B] +[ 2.678946] i915 0000:00:02.0: [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:102:DDI B/PHY B] +[ 2.679019] i915 0000:00:02.0: [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port B (VBT) +[ 2.679097] i915 0000:00:02.0: [drm:intel_bios_port_aux_ch [i915]] using AUX C for port C (VBT) +[ 2.679172] i915 0000:00:02.0: [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:118:DDI C/PHY C] +[ 2.679293] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CRTC:51:pipe A] hw state readout: enabled +[ 2.679406] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CRTC:72:pipe B] hw state readout: disabled +[ 2.679507] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CRTC:93:pipe C] hw state readout: disabled +[ 2.679611] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] hw state readout: enabled, pipe A +[ 2.679716] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] hw state readout: disabled, pipe A +[ 2.679821] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] hw state readout: disabled, pipe A +[ 2.679924] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] hw state readout: disabled, pipe B +[ 2.680029] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] hw state readout: disabled, pipe B +[ 2.680133] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] hw state readout: disabled, pipe B +[ 2.680274] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] hw state readout: disabled, pipe C +[ 2.680371] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] hw state readout: disabled, pipe C +[ 2.680469] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] hw state readout: disabled, pipe C +[ 2.680567] i915 0000:00:02.0: [drm:intel_dpll_readout_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1 +[ 2.680684] i915 0000:00:02.0: [drm:intel_dpll_readout_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000001, on 1 +[ 2.680779] i915 0000:00:02.0: [drm:intel_dpll_readout_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0 +[ 2.680875] i915 0000:00:02.0: [drm:intel_dpll_readout_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0 +[ 2.680991] i915 0000:00:02.0: [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp +[ 2.681089] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:94:DDI A/PHY A] hw state readout: enabled, pipe A +[ 2.681189] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:102:DDI B/PHY B] hw state readout: disabled, pipe A +[ 2.681284] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:104:DP-MST A] hw state readout: disabled, pipe A +[ 2.681378] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:105:DP-MST B] hw state readout: disabled, pipe B +[ 2.681471] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:106:DP-MST C] hw state readout: disabled, pipe C +[ 2.681564] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:118:DDI C/PHY C] hw state readout: disabled, pipe A +[ 2.681655] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:120:DP-MST A] hw state readout: disabled, pipe A +[ 2.681747] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:121:DP-MST B] hw state readout: disabled, pipe B +[ 2.681838] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:122:DP-MST C] hw state readout: disabled, pipe C +[ 2.681933] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:95:eDP-1] hw state readout: enabled +[ 2.682025] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:103:DP-1] hw state readout: disabled +[ 2.682118] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:113:HDMI-A-1] hw state readout: disabled +[ 2.682214] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:119:DP-2] hw state readout: disabled +[ 2.682307] i915 0000:00:02.0: [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for [CRTC:51:pipe A] state 0000000086a044d5 +[ 2.682336] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] min_cdclk 153221 kHz +[ 2.682430] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] min_cdclk 0 kHz +[ 2.682523] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] min_cdclk 0 kHz +[ 2.682616] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] pipe A data rate 612884 num active planes 1 +[ 2.682750] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] min_cdclk 0 kHz +[ 2.682850] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] min_cdclk 0 kHz +[ 2.682948] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] min_cdclk 0 kHz +[ 2.683047] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] pipe B data rate 0 num active planes 0 +[ 2.683145] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] min_cdclk 0 kHz +[ 2.683247] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] min_cdclk 0 kHz +[ 2.683345] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] min_cdclk 0 kHz +[ 2.683444] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] pipe C data rate 0 num active planes 0 +[ 2.685619] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [setup_hw_state] +[ 2.685698] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB +[ 2.685774] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 +[ 2.685846] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: +[ 2.685935] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: , slave transcoder bitmask = 0x0 +[ 2.686003] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no +[ 2.686072] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 7140667, gmch_n: 8388608, link_m: 297527, link_n: 524288, tu: 64 +[ 2.686140] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0 +[ 2.686214] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode: +[ 2.686339] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode: +[ 2.686491] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 153221 1920 2000 2060 2250 1080 1086 1094 1132, type: 0x40 flags: 0xa +[ 2.686597] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode: +[ 2.686730] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 153221 1920 2000 2060 2250 1080 1086 1094 1132, type: 0x40 flags: 0xa +[ 2.686831] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 153221 +[ 2.686953] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 118, ips linetime: 0 +[ 2.687056] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 +[ 2.687159] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no +[ 2.687265] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 +[ 2.687363] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x13, cfgcr1: 0x0, cfgcr2: 0x0 +[ 2.687465] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 +[ 2.687568] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries +[ 2.687666] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: no [setup_hw_state] +[ 2.687769] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:93:pipe C] enable: no [setup_hw_state] +[ 2.687890] i915 0000:00:02.0: [drm:intel_dpll_sanitize_state [i915]] DPLL 0 enabled but not in use, disabling +[ 2.688028] i915 0000:00:02.0: [drm:skl_get_initial_plane_config [i915]] pipe A/plane 1A with fb: size=1920x1080@32, offset=0, pitch 7680, size 0x7e9000 +[ 2.688134] i915 0000:00:02.0: [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0x0000000000000000, size=0x00000000007e9000 +[ 2.688264] i915 0000:00:02.0: [drm:i915_init_ggtt [i915]] Reserved GGTT:[7e9000, 7ea000] for use by error capture +[ 2.688360] i915 0000:00:02.0: [drm:i915_init_ggtt [i915]] clearing unused GTT space: [7ea000, 100000000] +[ 2.690647] [drm:intel_engines_init [i915]] Initialized 5 engine workarounds on rcs'0 +[ 2.690719] [drm:intel_engines_init [i915]] Initialized 5 whitelist workarounds on rcs'0 +[ 2.690784] [drm:intel_engines_init [i915]] Initialized 14 context workarounds on rcs'0 +[ 2.690918] [drm:intel_engines_init [i915]] Initialized 1 whitelist workarounds on bcs'0 +[ 2.690991] [drm:intel_engines_init [i915]] Initialized 1 whitelist workarounds on vcs'0 +[ 2.691062] [drm:intel_engines_init [i915]] Initialized 1 whitelist workarounds on vecs'0 +[ 2.692048] i915 0000:00:02.0: [drm:intel_dp_initial_fastset_check [i915]] Forcing full modeset to compute PSR state +[ 2.692497] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 +[ 2.692599] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 152840KHz +[ 2.692685] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0 +[ 2.692760] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 24 +[ 2.692834] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 458520 available 540000 +[ 2.692951] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 +[ 2.693022] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:94:DDI A/PHY A] [CRTC:51:pipe A] +[ 2.693117] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in infoframes.enable (expected 0x00000000, found 0x00000004) +[ 2.693203] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 1, on 1, ms 1 +[ 2.693308] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000f407152d to 0000000047e9f5f2 +[ 2.693415] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [CRTC:51:pipe A] dbuf slices 0x1, ddb (0 - 892), active pipes 0x1 +[ 2.693548] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003ab5c11c to 0000000047e9f5f2 +[ 2.693707] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 0) -> ( 0 - 860), size 0 -> 860 +[ 2.693805] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 0 - 0) -> ( 860 - 892), size 0 -> 32 +[ 2.693897] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm +[ 2.694046] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 2, 2, 3, 5, 6, 6, 7, 0, 0 +[ 2.694155] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 5, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 4, 25, 34, 41, 78, 94, 98, 114, 0, 0 +[ 2.694247] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 5, 26, 35, 42, 79, 95, 99, 115, 0, 0 +[ 2.694337] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 2.694428] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 2.694514] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 2.694601] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 2.694686] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 2.694770] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 2.694872] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 2.694962] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 2.695056] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000005ffb9272 state 00000000b67020fb to 0000000047e9f5f2 +[ 2.695178] i915 0000:00:02.0: [drm:intel_find_shared_dpll [i915]] [CRTC:51:pipe A] allocated DPLL 0 +[ 2.695292] i915 0000:00:02.0: [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A +[ 2.695404] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [modeset] +[ 2.695517] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB +[ 2.695626] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 +[ 2.695743] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: +[ 2.695849] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: , slave transcoder bitmask = 0x0 +[ 2.695956] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no +[ 2.696062] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 7122860, gmch_n: 8388608, link_m: 296785, link_n: 524288, tu: 64 +[ 2.696170] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4 +[ 2.696276] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0 +[ 2.696279] i915 0000:00:02.0: pixelformat: RGB +[ 2.696280] i915 0000:00:02.0: colorimetry: sRGB +[ 2.696281] i915 0000:00:02.0: bpc: 0 +[ 2.696283] i915 0000:00:02.0: dynamic range: VESA range +[ 2.696284] i915 0000:00:02.0: content type: Not defined +[ 2.696285] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode: +[ 2.696427] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode: +[ 2.696572] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 152840 1920 2000 2060 2250 1080 1086 1094 1132, type: 0x48 flags: 0xa +[ 2.696682] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode: +[ 2.696822] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 152840 1920 2000 2060 2250 1080 1086 1094 1132, type: 0x40 flags: 0xa +[ 2.696931] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 152840 +[ 2.697060] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 118, ips linetime: 0 +[ 2.697167] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 +[ 2.697278] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no +[ 2.697384] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 +[ 2.697490] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0 +[ 2.697597] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 +[ 2.697703] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries +[ 2.697812] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:126] 1920x1080 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes +[ 2.697921] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 +[ 2.698026] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0 +[ 2.698134] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no +[ 2.698242] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor A] fb: [NOFB], visible: no +[ 2.698945] i915 0000:00:02.0: [drm:intel_edp_backlight_off [i915]] +[ 2.961290] i915 0000:00:02.0: [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 +[ 2.961694] i915 0000:00:02.0: [drm:intel_disable_pipe [i915]] disabling pipe A +[ 2.970565] i915 0000:00:02.0: [drm:edp_panel_off [i915]] Turn [ENCODER:94:DDI A/PHY A] panel power off +[ 2.970901] i915 0000:00:02.0: [drm:edp_panel_off [i915]] Wait for panel power off time +[ 2.971262] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 +[ 3.024342] i915 0000:00:02.0: [drm:edp_panel_off [i915]] Wait complete +[ 3.024718] i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 51 +[ 3.025054] i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 +[ 3.025405] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:94:DDI A/PHY A] +[ 3.025721] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:102:DDI B/PHY B] +[ 3.026027] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:104:DP-MST A] +[ 3.026342] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:105:DP-MST B] +[ 3.026643] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:106:DP-MST C] +[ 3.026939] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:118:DDI C/PHY C] +[ 3.027246] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:120:DP-MST A] +[ 3.027540] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:121:DP-MST B] +[ 3.027835] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:122:DP-MST C] +[ 3.028128] i915 0000:00:02.0: [drm:verify_single_dpll_state [i915]] DPLL 0 +[ 3.028439] i915 0000:00:02.0: [drm:verify_single_dpll_state [i915]] DPLL 1 +[ 3.028736] i915 0000:00:02.0: [drm:verify_single_dpll_state [i915]] DPLL 2 +[ 3.029032] i915 0000:00:02.0: [drm:verify_single_dpll_state [i915]] DPLL 3 +[ 3.029339] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 51 +[ 3.029651] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0 +[ 3.029960] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Turn [ENCODER:94:DDI A/PHY A] panel power on +[ 3.030311] i915 0000:00:02.0: [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle +[ 3.641469] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 +[ 3.641861] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Wait complete +[ 3.642278] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Wait for panel power on +[ 3.642701] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 +[ 3.851276] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Wait complete +[ 3.851676] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD on +[ 3.852124] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b +[ 3.854281] i915 0000:00:02.0: [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a +[ 3.855042] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0, pre-emphasis level 0, at DPRX +[ 3.855374] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000 +[ 3.855679] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 +[ 3.856827] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] clock recovery OK +[ 3.857122] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 +[ 3.858616] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] Channel EQ done. DP Training successful +[ 3.858905] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:95:eDP-1] Link Training passed at link rate = 270000, lane count = 2, at DPRX +[ 3.859428] i915 0000:00:02.0: [drm:intel_enable_pipe [i915]] enabling pipe A +[ 3.859750] i915 0000:00:02.0: [drm:intel_edp_backlight_on [i915]] +[ 3.860045] i915 0000:00:02.0: [drm:intel_panel_enable_backlight [i915]] pipe A +[ 3.860395] i915 0000:00:02.0: [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 5989 +[ 3.860852] i915 0000:00:02.0: [drm:intel_psr_enable_locked [i915]] Enabling PSR1 +[ 3.862198] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 +[ 3.862500] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A +[ 3.876652] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1] +[ 3.877024] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A] +[ 3.877425] i915 0000:00:02.0: [drm:verify_single_dpll_state [i915]] DPLL 0 +[ 3.877750] i915 0000:00:02.0: [drm:intel_sagv_post_plane_update [i915]] Enabling SAGV +[ 3.878019] i915 0000:00:02.0: [drm:intel_uncore_arm_unclaimed_mmio_detection [i915]] Unclaimed register detected, enabling oneshot unclaimed register reporting. Please use i915.mmio_debug=N for more information. +[ 3.878504] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] found possible fb from plane A +[ 3.878832] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping +[ 3.879140] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping +[ 3.879449] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] checking plane A for BIOS fb +[ 3.879743] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] pipe A area: 1920x1080, bpp: 32, size: 8294400 +[ 3.880037] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] fb big enough for plane A (8294400 >= 8294400) +[ 3.880342] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] pipe B not active, skipping +[ 3.880631] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] pipe C not active, skipping +[ 3.880919] i915 0000:00:02.0: [drm:intel_fbdev_init [i915]] using BIOS fb for initial console +[ 3.881518] [drm:intel_engines_driver_register [i915]] renamed rcs'0 to rcs0 +[ 3.881797] [drm:intel_engines_driver_register [i915]] renamed bcs'0 to bcs0 +[ 3.882060] [drm:intel_engines_driver_register [i915]] renamed vcs'0 to vcs0 +[ 3.882329] [drm:intel_engines_driver_register [i915]] renamed vecs'0 to vecs0 +[ 3.883924] i915 0000:00:02.0: [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered +[ 3.884283] i915 0000:00:02.0: [drm:intel_dp_connector_register [i915]] registering AUX A/DDI A/PHY A bus for card0-eDP-1 +[ 3.884837] i915 0000:00:02.0: [drm:intel_dp_connector_register [i915]] registering AUX B/DDI B/PHY B bus for card0-DP-1 +[ 3.886026] i915 0000:00:02.0: [drm:intel_dp_connector_register [i915]] registering AUX C/DDI C/PHY C bus for card0-DP-2 +[ 3.886587] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0 +[ 3.886963] i915 0000:00:02.0: [drm:intel_opregion_resume [i915]] 4 outputs detected +[ 3.895391] i915 0000:00:02.0: [drm:intel_audio_init [i915]] init value of AUD_FREQ_CNTRL of 0x10 +[ 3.895696] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DDI D IO power well +[ 3.895900] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:95:eDP-1] +[ 3.896120] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DDI C IO power well +[ 3.896497] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DDI B IO power well +[ 3.896813] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling power well 2 +[ 3.897244] [drm:intel_dsm_detect.isra.0 [i915]] no _DSM method for intel device +[ 3.897573] i915 device info: pciid=0x9bca rev=0x04 platform=COMETLAKE (subplatform=0x1) gen=9 +[ 3.897584] i915 device info: gen: 9 +[ 3.897589] i915 device info: gt: 2 +[ 3.897598] i915 device info: iommu: enabled +[ 3.897603] i915 device info: memory-regions: 5 +[ 3.897607] i915 device info: page-sizes: 11000 +[ 3.897612] i915 device info: platform: COMETLAKE +[ 3.897616] i915 device info: ppgtt-size: 48 +[ 3.897620] i915 device info: ppgtt-type: 2 +[ 3.897624] i915 device info: dma_mask_size: 39 +[ 3.897628] i915 device info: is_mobile: no +[ 3.897633] i915 device info: is_lp: no +[ 3.897638] i915 device info: require_force_probe: no +[ 3.897642] i915 device info: is_dgfx: no +[ 3.897647] i915 device info: has_64bit_reloc: yes +[ 3.897651] i915 device info: gpu_reset_clobbers_display: no +[ 3.897656] i915 device info: has_reset_engine: yes +[ 3.897660] i915 device info: has_fpga_dbg: yes +[ 3.897664] i915 device info: has_global_mocs: no +[ 3.897668] i915 device info: has_gt_uc: yes +[ 3.897672] i915 device info: has_l3_dpf: no +[ 3.897677] i915 device info: has_llc: yes +[ 3.897681] i915 device info: has_logical_ring_contexts: yes +[ 3.897685] i915 device info: has_logical_ring_elsq: no +[ 3.897689] i915 device info: has_logical_ring_preemption: yes +[ 3.897693] i915 device info: has_master_unit_irq: no +[ 3.897698] i915 device info: has_pooled_eu: no +[ 3.897702] i915 device info: has_rc6: yes +[ 3.897706] i915 device info: has_rc6p: no +[ 3.897710] i915 device info: has_rps: yes +[ 3.897714] i915 device info: has_runtime_pm: yes +[ 3.897718] i915 device info: has_snoop: no +[ 3.897722] i915 device info: has_coherent_ggtt: yes +[ 3.897726] i915 device info: unfenced_needs_alignment: no +[ 3.897730] i915 device info: hws_needs_physical: no +[ 3.897734] i915 device info: cursor_needs_physical: no +[ 3.897738] i915 device info: has_csr: yes +[ 3.897742] i915 device info: has_ddi: yes +[ 3.897551] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [ENCODER:94:DDI A/PHY A] MST support: port: no, sink: no, modparam: yes +[ 3.897746] i915 device info: has_dp_mst: yes +[ 3.897750] i915 device info: has_dsb: no +[ 3.897754] i915 device info: has_dsc: no +[ 3.897758] i915 device info: has_fbc: yes +[ 3.897761] i915 device info: has_gmch: no +[ 3.897765] i915 device info: has_hdcp: yes +[ 3.897769] i915 device info: has_hotplug: yes +[ 3.897773] i915 device info: has_hti: no +[ 3.897777] i915 device info: has_ipc: yes +[ 3.897780] i915 device info: has_modular_fia: no +[ 3.897784] i915 device info: has_overlay: no +[ 3.897788] i915 device info: has_psr: yes +[ 3.897792] i915 device info: has_psr_hw_tracking: yes +[ 3.897796] i915 device info: overlay_needs_physical: no +[ 3.897800] i915 device info: supports_tv: no +[ 3.897804] i915 device info: rawclk rate: 24000 kHz +[ 3.897809] i915 device info: CS timestamp frequency: 12000000 Hz +[ 3.897814] i915 device info: available engines: 47 +[ 3.897818] i915 device info: slice total: 1, mask=0001 +[ 3.897824] i915 device info: subslice total: 3 +[ 3.897828] i915 device info: slice0: 3 subslices, mask=00000007 +[ 3.897834] i915 device info: slice1: 0 subslices, mask=00000000 +[ 3.897839] i915 device info: slice2: 0 subslices, mask=00000000 +[ 3.897845] i915 device info: EU total: 24 +[ 3.897849] i915 device info: EU per subslice: 8 +[ 3.897852] i915 device info: has slice power gating: no +[ 3.897856] i915 device info: has subslice power gating: no +[ 3.897860] i915 device info: has EU power gating: yes +[ 3.897949] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 +[ 3.898280] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 +[ 3.898542] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 +[ 3.898803] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] DFP max bpc 0, max dotclock 0, TMDS clock 0-0 +[ 3.899062] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] YCbCr 4:2:0 allowed? no, YCbCr 4:4:4->4:2:0 conversion? no +[ 3.900701] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:103:DP-1] +[ 3.901099] i915 0000:00:02.0: [drm:intel_hdmi_detect [i915]] [CONNECTOR:113:HDMI-A-1] +[ 3.901824] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 3.902091] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 3.902740] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 3.903047] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 3.903115] i915 0000:00:02.0: [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging +[ 3.903386] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 +[ 3.911073] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 3.911140] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 +[ 3.911842] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 3.912099] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 3.912690] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 3.913105] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:119:DP-2] +[ 3.914001] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane +[ 3.914036] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 1 primary plane +[ 3.914066] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 2 primary plane +[ 3.914095] i915 0000:00:02.0: [drm:intelfb_create [i915]] re-using BIOS fb +[ 3.914369] i915 0000:00:02.0: [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00000000 +[ 3.914738] fbcon: i915drmfb (fb0) is primary device +[ 3.914745] i915 0000:00:02.0: [drm] fb0: i915drmfb frame buffer device +[ 3.923347] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] +[ 3.923580] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:95:eDP-1] +[ 3.924221] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [ENCODER:94:DDI A/PHY A] MST support: port: no, sink: no, modparam: yes +[ 3.924498] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 +[ 3.924760] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 +[ 3.925006] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 +[ 3.925269] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] DFP max bpc 0, max dotclock 0, TMDS clock 0-0 +[ 3.925520] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] YCbCr 4:2:0 allowed? no, YCbCr 4:4:4->4:2:0 conversion? no +[ 3.927686] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:103:DP-1] +[ 3.927967] i915 0000:00:02.0: [drm:intel_hdmi_detect [i915]] [CONNECTOR:113:HDMI-A-1] +[ 3.928599] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 3.928765] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 3.929336] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 3.929549] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 3.929610] i915 0000:00:02.0: [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging +[ 3.929766] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 +[ 3.937328] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 3.937410] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 +[ 3.937982] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 3.938105] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 3.938632] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 3.938870] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:119:DP-2] +[ 3.939519] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:95:eDP-1] +[ 3.939677] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000c6b3e689 +[ 3.939783] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002ca29006 +[ 3.939940] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000054499c48 +[ 3.940044] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000357b2629 +[ 3.940028] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [ENCODER:94:DDI A/PHY A] MST support: port: no, sink: no, modparam: yes +[ 3.940170] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000007b4164b7 +[ 3.940156] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 +[ 3.940263] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000cf289d76 +[ 3.940307] i915 0000:00:02.0: [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for [CRTC:51:pipe A] state 000000009337cd77 +[ 3.940291] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 +[ 3.940348] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:126] for [PLANE:31:plane 1A] state 000000003dd65d81 +[ 3.940410] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 +[ 3.940528] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] DFP max bpc 0, max dotclock 0, TMDS clock 0-0 +[ 3.940644] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] YCbCr 4:2:0 allowed? no, YCbCr 4:4:4->4:2:0 conversion? no +[ 3.941927] i915 0000:00:02.0: [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:95:eDP-1] state 000000000abe2dc1 to [NOCRTC] +[ 3.941995] i915 0000:00:02.0: [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:95:eDP-1] state 000000000abe2dc1 to [CRTC:51:pipe A] +[ 3.942105] i915 0000:00:02.0: [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:72:pipe B] state 00000000d153d018 +[ 3.942146] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:52:plane 1B] state 0000000032d289d6 +[ 3.942302] i915 0000:00:02.0: [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000074d85c22 +[ 3.942343] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000919da1db +[ 3.942708] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 +[ 3.942815] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 152840KHz +[ 3.942914] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0 +[ 3.943006] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 24 +[ 3.943097] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 458520 available 540000 +[ 3.943204] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 +[ 3.943300] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:94:DDI A/PHY A] [CRTC:51:pipe A] +[ 3.943399] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 3.943498] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000002038d223 to 00000000be046348 +[ 3.943599] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000092bf9d9f to 00000000be046348 +[ 3.943694] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm +[ 3.943762] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 2, 2, 3, 5, 6, 6, 7, 0, 0 -> 0, 2, 3, 3, 5, 6, 6, 7, 0, 0 +[ 3.943832] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 4, 25, 34, 41, 78, 94, 98, 114, 0, 0 -> 9, 30, 41, 45, 82, 98, 98, 114, 0, 0 +[ 3.943900] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 5, 26, 35, 42, 79, 95, 99, 115, 0, 0 -> 10, 31, 42, 46, 83, 99, 99, 115, 0, 0 +[ 3.943968] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 3.944034] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944102] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944169] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944244] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 3.944310] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944378] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944444] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944511] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 3.944576] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944644] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944710] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944777] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 3.944843] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944910] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.944977] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.945044] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 3.945109] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.945183] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.945255] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.945321] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 3.945400] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.945438] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.945475] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 3.945515] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [fastset] +[ 3.945568] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB +[ 3.945621] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 +[ 3.945672] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: +[ 3.945723] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: , slave transcoder bitmask = 0x0 +[ 3.945773] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no +[ 3.945824] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 7122860, gmch_n: 8388608, link_m: 296785, link_n: 524288, tu: 64 +[ 3.945875] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4 +[ 3.945926] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0 +[ 3.945928] i915 0000:00:02.0: pixelformat: RGB +[ 3.945928] i915 0000:00:02.0: colorimetry: sRGB +[ 3.945929] i915 0000:00:02.0: bpc: 0 +[ 3.945930] i915 0000:00:02.0: dynamic range: VESA range +[ 3.945931] i915 0000:00:02.0: content type: Not defined +[ 3.945931] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode: +[ 3.946003] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode: +[ 3.946073] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 152840 1920 2000 2060 2250 1080 1086 1094 1132, type: 0x48 flags: 0xa +[ 3.946125] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode: +[ 3.946198] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 152840 1920 2000 2060 2250 1080 1086 1094 1132, type: 0x40 flags: 0xa +[ 3.946249] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 152840 +[ 3.946300] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 118, ips linetime: 0 +[ 3.946351] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 +[ 3.946401] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no +[ 3.946452] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 +[ 3.946503] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0 +[ 3.946553] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 +[ 3.946604] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries +[ 3.946655] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:126] 1920x1080 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes +[ 3.946706] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 +[ 3.946757] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0 +[ 3.946808] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no +[ 3.946858] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor A] fb: [NOFB], visible: no +[ 3.959842] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1] +[ 3.959928] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A] +[ 3.960020] i915 0000:00:02.0: [drm:verify_single_dpll_state [i915]] DPLL 0 +[ 3.960174] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] +[ 3.960159] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:103:DP-1] +[ 3.960276] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:95:eDP-1] +[ 3.960678] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [ENCODER:94:DDI A/PHY A] MST support: port: no, sink: no, modparam: yes +[ 3.960734] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 +[ 3.960786] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 +[ 3.960837] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 +[ 3.960888] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] DFP max bpc 0, max dotclock 0, TMDS clock 0-0 +[ 3.960939] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] YCbCr 4:2:0 allowed? no, YCbCr 4:4:4->4:2:0 conversion? no +[ 3.961837] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:103:DP-1] +[ 3.961933] i915 0000:00:02.0: [drm:intel_hdmi_detect [i915]] [CONNECTOR:113:HDMI-A-1] +[ 3.962420] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 3.962474] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 3.962917] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 3.963014] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 3.963034] i915 0000:00:02.0: [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging +[ 3.963084] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 +[ 3.970475] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 3.970496] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 +[ 3.970991] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 3.971042] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 3.971481] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 3.971610] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:119:DP-2] +[ 3.971880] i915 0000:00:02.0: [drm:intel_hdmi_detect [i915]] [CONNECTOR:113:HDMI-A-1] +[ 3.971960] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000000b00c08c +[ 3.971998] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e1e0a00b +[ 3.972054] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000052ec4f54 +[ 3.972091] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009d92edc7 +[ 3.972147] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000be4a1495 +[ 3.972189] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000005bde48df +[ 3.972207] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:126] for [PLANE:31:plane 1A] state 00000000d4061228 +[ 3.972404] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 3.972485] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 3.972957] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 3.973054] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 3.973075] i915 0000:00:02.0: [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging +[ 3.973132] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 +[ 3.980602] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 3.980625] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 +[ 3.981085] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 3.981132] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 3.981557] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 3.981689] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:119:DP-2] +[ 3.981876] i915 0000:00:02.0: [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:95:eDP-1] state 00000000b1a08f11 to [NOCRTC] +[ 3.981895] i915 0000:00:02.0: [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:95:eDP-1] state 00000000b1a08f11 to [CRTC:51:pipe A] +[ 3.981935] i915 0000:00:02.0: [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:72:pipe B] state 00000000880597ca +[ 3.981953] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:52:plane 1B] state 00000000e862e30a +[ 3.982008] i915 0000:00:02.0: [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000054ba4941 +[ 3.982025] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f922db23 +[ 3.982147] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 3.982214] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000075c05827 to 00000000be046348 +[ 3.982270] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000092bf9d9f to 00000000be046348 +[ 4.020290] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000922b3845 to 00000000e586ff7e +[ 4.020355] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000b3c8209d to 00000000e586ff7e +[ 4.026671] i915 0000:00:02.0: [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for [CRTC:51:pipe A] state 000000003833a2e2 +[ 4.026692] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000bb8c0961 +[ 4.026752] i915 0000:00:02.0: [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:95:eDP-1] state 000000007b82cfad to [NOCRTC] +[ 4.026771] i915 0000:00:02.0: [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:95:eDP-1] state 000000007b82cfad to [CRTC:51:pipe A] +[ 4.026882] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 4.026952] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000b37559fe to 00000000e586ff7e +[ 4.027013] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000b3c8209d to 00000000e586ff7e +[ 4.046841] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:95:eDP-1] +[ 4.047246] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [ENCODER:94:DDI A/PHY A] MST support: port: no, sink: no, modparam: yes +[ 4.047306] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 +[ 4.047359] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 +[ 4.047411] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 +[ 4.047463] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] DFP max bpc 0, max dotclock 0, TMDS clock 0-0 +[ 4.047514] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] YCbCr 4:2:0 allowed? no, YCbCr 4:4:4->4:2:0 conversion? no +[ 4.048420] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:103:DP-1] +[ 4.048519] i915 0000:00:02.0: [drm:intel_hdmi_detect [i915]] [CONNECTOR:113:HDMI-A-1] +[ 4.048946] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 4.048998] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 4.049433] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 4.049527] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 4.049546] i915 0000:00:02.0: [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging +[ 4.049595] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 +[ 4.056582] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 4.056602] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 +[ 4.057061] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 4.057110] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 4.057580] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 4.057704] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:119:DP-2] +[ 5.224787] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=5772/24242 +[ 5.224857] i915 0000:00:02.0: [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 5989 +[ 5.812654] i915 0000:00:02.0: [drm:i915_hdcp_component_bind [i915]] I915 HDCP comp bind +[ 5.812754] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915]) +[ 6.042736] sof-audio-pci 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) +[ 6.042823] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling power well 2 +[ 6.042915] i915 0000:00:02.0: [drm:i915_audio_component_get_power [i915]] restored AUD_FREQ_CNTRL to 0x10 +[ 6.237898] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling power well 2 +[ 6.285359] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling power well 2 +[ 6.285466] i915 0000:00:02.0: [drm:i915_audio_component_get_power [i915]] restored AUD_FREQ_CNTRL to 0x10 +[ 6.291783] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port B +[ 6.291843] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port B +[ 6.291889] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port B +[ 6.291934] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port C +[ 6.291979] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port C +[ 6.292024] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port C +[ 6.292069] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port D +[ 6.292114] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port D +[ 6.292159] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port D +[ 6.292224] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling power well 2 +[ 6.292908] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling power well 2 +[ 6.292970] i915 0000:00:02.0: [drm:i915_audio_component_get_power [i915]] restored AUD_FREQ_CNTRL to 0x10 +[ 6.298093] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling power well 2 +[ 7.097245] i915 0000:00:02.0: [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD off +[ 7.097437] i915 0000:00:02.0: [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067 +[ 7.097489] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 7.097543] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 7.097593] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 14.000134] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:95:eDP-1] +[ 14.000213] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 14.000269] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 14.000351] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD on +[ 14.000544] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f +[ 14.000941] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [ENCODER:94:DDI A/PHY A] MST support: port: no, sink: no, modparam: yes +[ 14.000991] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 +[ 14.001039] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 +[ 14.001087] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 +[ 14.001135] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] DFP max bpc 0, max dotclock 0, TMDS clock 0-0 +[ 14.001188] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:95:eDP-1] YCbCr 4:2:0 allowed? no, YCbCr 4:4:4->4:2:0 conversion? no +[ 14.002145] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:103:DP-1] +[ 14.002271] i915 0000:00:02.0: [drm:intel_hdmi_detect [i915]] [CONNECTOR:113:HDMI-A-1] +[ 14.002750] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 14.002801] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 14.003224] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) +[ 14.003323] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 14.003341] i915 0000:00:02.0: [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging +[ 14.003389] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 +[ 14.010858] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb +[ 14.010880] i915 0000:00:02.0: [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 +[ 14.011379] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 14.011432] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry +[ 14.011844] i915 0000:00:02.0: [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) +[ 14.012018] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:119:DP-2] +[ 14.220801] i915 0000:00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 1 created +[ 14.220894] i915 0000:00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 2 created +[ 14.227971] i915 0000:00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 3 created +[ 14.228065] i915 0000:00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 4 created +[ 14.228998] i915 0000:00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 3 created +[ 14.229054] i915 0000:00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 4 created +[ 15.496312] i915 0000:00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 1 created +[ 15.496420] i915 0000:00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 2 created +[ 15.525251] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling power well 2 +[ 15.525334] i915 0000:00:02.0: [drm:i915_audio_component_get_power [i915]] restored AUD_FREQ_CNTRL to 0x10 +[ 15.658976] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port B +[ 15.659050] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port B +[ 15.659098] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port B +[ 15.659151] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port C +[ 15.659197] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port C +[ 15.659242] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port C +[ 15.659287] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port D +[ 15.659332] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port D +[ 15.659377] i915 0000:00:02.0: [drm:i915_audio_component_get_eld [i915]] Not valid for port D +[ 16.102544] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:130] for [PLANE:31:plane 1A] state 00000000ee63da82 +[ 16.102585] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c99e9cb +[ 16.102621] i915 0000:00:02.0: [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000179dddda to [CRTC:51:pipe A] +[ 16.102639] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:127] for [PLANE:47:cursor A] state 00000000179dddda +[ 16.102658] i915 0000:00:02.0: [drm:drm_atomic_set_mode_prop_for_crtc [drm]] Set [MODE:1920x1080] for [CRTC:51:pipe A] state 000000002457e00b +[ 16.102694] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:52:plane 1B] state 0000000001a604ff +[ 16.102730] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001b15d36b +[ 16.102765] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008c684412 +[ 16.102800] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b6fef018 +[ 16.102836] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000d7bbb9ce +[ 16.102871] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000480d059c +[ 16.103117] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.103207] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 +[ 16.103265] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000004ae0026c to 00000000461702a2 +[ 16.103322] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000072849a6d to 00000000461702a2 +[ 16.103374] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm +[ 16.103410] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 2, 3, 3, 5, 6, 6, 7, 0, 0 -> 0, 3, 4, 4, 6, 7, 7, 9, 0, 0 +[ 16.103446] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 9, 30, 41, 45, 82, 98, 98, 114, 0, 0 -> 27, 47, 59, 62, 92, 107, 107, 137, 0, 0 +[ 16.103482] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 10, 31, 42, 46, 83, 99, 99, 115, 0, 0 -> 28, 48, 60, 63, 93, 108, 108, 138, 0, 0 +[ 16.103518] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm +[ 16.103553] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 2, 3, 3, 5, 6, 6, 7, 0, 0 +[ 16.103589] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 9, 9, 11, 11, 17, 20, 20, 23, 0, 0 +[ 16.103624] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 12, 12, 18, 21, 21, 24, 0, 0 +[ 16.105615] i915 0000:00:02.0: [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A +[ 16.105671] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 +[ 16.105722] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A +[ 16.149201] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 00000000a713a431 +[ 16.149277] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.149380] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000eafe531b to 000000009e1819ed +[ 16.149471] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000012c7c51b to 000000009e1819ed +[ 16.313671] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:130] for [PLANE:31:plane 1A] state 00000000b0339917 +[ 16.313752] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.313862] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005fbfb7bd to 000000004a4d9af0 +[ 16.313955] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000022814f53 to 000000004a4d9af0 +[ 16.348773] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 00000000a834e895 +[ 16.348822] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.348904] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000c9aa3744 to 00000000bee1e434 +[ 16.348966] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000cdc3373b to 00000000bee1e434 +[ 16.361963] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005581ce6d +[ 16.362046] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.362120] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000004492e756 to 00000000aba500ca +[ 16.362195] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000cbf11c91 to 00000000aba500ca +[ 16.378470] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 000000004fc0f44f +[ 16.378512] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.378574] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000f9ca01d3 to 000000005c6129fe +[ 16.378632] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000011ed57d8 to 000000005c6129fe +[ 16.395681] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000043fa0d6f +[ 16.395738] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.395827] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008ab0c8af to 000000003fcc7543 +[ 16.395901] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004977495f to 000000003fcc7543 +[ 16.412620] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 000000004f5f9012 +[ 16.412704] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.412842] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000011bd5259 to 000000008947f836 +[ 16.412949] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000015dedc94 to 000000008947f836 +[ 16.429649] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000425daaf2 +[ 16.429795] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.430053] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000040a243bf to 00000000ff2589cf +[ 16.430358] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005f8289b7 to 00000000ff2589cf +[ 16.446646] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 000000009c4b6cea +[ 16.446825] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.447110] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000cc6ac58d to 000000006d2f16fe +[ 16.447392] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000686fbce6 to 000000006d2f16fe +[ 16.463683] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000061100816 +[ 16.463884] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.464248] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dcb4cd85 to 00000000461702a2 +[ 16.464506] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005f7cb68a to 00000000461702a2 +[ 16.480214] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 00000000118ea634 +[ 16.480417] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.480745] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000bb49759e to 00000000461702a2 +[ 16.481011] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002953731f to 00000000461702a2 +[ 16.497120] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000fec27e9e +[ 16.497366] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.497699] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001c7ced4b to 000000006d2f16fe +[ 16.497964] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005cdc8d91 to 000000006d2f16fe +[ 16.513472] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 00000000bc104187 +[ 16.513672] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.514006] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000c7c5f4c1 to 00000000ff2589cf +[ 16.514295] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000067a4008c to 00000000ff2589cf +[ 16.530246] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e05694e8 +[ 16.530454] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.530782] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005590dce5 to 000000008947f836 +[ 16.531053] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000e9b2b873 to 000000008947f836 +[ 16.546860] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 000000000865c71a +[ 16.547063] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.547417] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000600f8d4f to 000000003fcc7543 +[ 16.547691] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000041d8c9b3 to 000000003fcc7543 +[ 16.562648] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000a2b5c38d +[ 16.562842] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.563138] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000056d37a59 to 000000005c6129fe +[ 16.563456] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000f1169ac to 000000005c6129fe +[ 16.626740] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:129] for [PLANE:31:plane 1A] state 00000000118ea634 +[ 16.626864] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.627043] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000503df9fa to 00000000aba500ca +[ 16.627225] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007dbb39c4 to 00000000aba500ca +[ 16.652190] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000a2b5c38d +[ 16.652239] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.652318] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000040a243bf to 00000000aba500ca +[ 16.652378] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007c238806 to 00000000aba500ca +[ 16.662014] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d194ea6c +[ 16.662064] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.662139] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000cc6ac58d to 000000005c6129fe +[ 16.662213] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000bbff093d to 000000005c6129fe +[ 16.678998] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000bc104187 +[ 16.679049] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.679129] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000011bd5259 to 000000003fcc7543 +[ 16.679236] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001e742f88 to 000000003fcc7543 +[ 16.695655] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000425daaf2 +[ 16.695717] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.695847] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008ab0c8af to 000000008947f836 +[ 16.695927] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006826e963 to 000000008947f836 +[ 16.712459] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000009c4b6cea +[ 16.712553] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.712720] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000f9ca01d3 to 00000000ff2589cf +[ 16.712842] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000025c10342 to 00000000ff2589cf +[ 16.729448] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000061100816 +[ 16.729631] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.729959] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000543adfb7 to 000000006d2f16fe +[ 16.730273] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006eb0ca12 to 000000006d2f16fe +[ 16.747218] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000ee63da82 +[ 16.747426] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.747786] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000590e9478 to 00000000461702a2 +[ 16.748047] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009529c2d0 to 00000000461702a2 +[ 16.763043] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d4738e15 +[ 16.763287] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.763682] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008a9608c0 to 00000000461702a2 +[ 16.763952] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009593a4fa to 00000000461702a2 +[ 16.780457] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000000865c71a +[ 16.780661] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.781011] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000146cfa3a to 000000006d2f16fe +[ 16.781301] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a7f5644d to 000000006d2f16fe +[ 16.796420] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005581ce6d +[ 16.796625] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.796971] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008b8efc18 to 00000000ff2589cf +[ 16.797260] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f9fc28cb to 00000000ff2589cf +[ 16.813833] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004fc0f44f +[ 16.814036] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.814403] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e09c1d06 to 000000008947f836 +[ 16.814674] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000008a97fc46 to 000000008947f836 +[ 16.830479] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000043fa0d6f +[ 16.830681] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.831024] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000004700a836 to 000000003fcc7543 +[ 16.831320] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000048b93344 to 000000003fcc7543 +[ 16.847124] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004cb53221 +[ 16.847363] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.847710] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000cbe22701 to 000000005c6129fe +[ 16.847965] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000febf8ea4 to 000000005c6129fe +[ 16.862014] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000fa67bd34 +[ 16.862069] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.862176] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000040e50b74 to 00000000aba500ca +[ 16.862254] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000019a1fafb to 00000000aba500ca +[ 16.878975] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e05694e8 +[ 16.879032] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.879159] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006c8b1211 to 00000000aba500ca +[ 16.879234] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000019a1fafb to 00000000aba500ca +[ 16.895807] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000f6ee3bcb +[ 16.895904] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.896063] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000313eb8a5 to 000000005c6129fe +[ 16.896224] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000febf8ea4 to 000000005c6129fe +[ 16.913430] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000034041e5a +[ 16.913611] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.913943] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000225624f1 to 000000003fcc7543 +[ 16.914238] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000048b93344 to 000000003fcc7543 +[ 16.930495] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000f6ee3bcb +[ 16.930701] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.931045] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000225624f1 to 000000008947f836 +[ 16.931327] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000008a97fc46 to 000000008947f836 +[ 16.947126] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e05694e8 +[ 16.947365] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.947730] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000313eb8a5 to 00000000ff2589cf +[ 16.947996] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f9fc28cb to 00000000ff2589cf +[ 16.963783] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000fa67bd34 +[ 16.963984] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.964353] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006c8b1211 to 000000006d2f16fe +[ 16.964622] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a7f5644d to 000000006d2f16fe +[ 16.979662] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004cb53221 +[ 16.979863] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.980222] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000040e50b74 to 00000000461702a2 +[ 16.980494] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009593a4fa to 00000000461702a2 +[ 16.996371] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000043fa0d6f +[ 16.996574] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 16.996930] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000cbe22701 to 00000000461702a2 +[ 16.997217] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009529c2d0 to 00000000461702a2 +[ 17.013700] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004fc0f44f +[ 17.013901] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 17.014259] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000004700a836 to 000000006d2f16fe +[ 17.014530] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006eb0ca12 to 000000006d2f16fe +[ 17.017227] i915 0000:00:02.0: [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD off +[ 17.017630] i915 0000:00:02.0: [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067 +[ 17.029916] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005581ce6d +[ 17.030116] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 17.030501] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e09c1d06 to 00000000ff2589cf +[ 17.030772] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000025c10342 to 00000000ff2589cf +[ 17.047098] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000000865c71a +[ 17.047340] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 17.047702] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008b8efc18 to 000000008947f836 +[ 17.047965] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006826e963 to 000000008947f836 +[ 17.063763] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d4738e15 +[ 17.063965] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 17.064324] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000146cfa3a to 000000003fcc7543 +[ 17.064593] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001e742f88 to 000000003fcc7543 +[ 17.080563] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000000865c71a +[ 17.080756] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 17.081062] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008a9608c0 to 000000005c6129fe +[ 17.081358] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000bbff093d to 000000005c6129fe +[ 18.122378] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling power well 2 +[ 18.122705] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 18.122994] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 18.123238] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 67.486555] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 67.486904] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 67.489157] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d581081a +[ 67.489231] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 67.489329] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000bc48f90b to 000000008710c86f +[ 67.489424] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000fa6fb80e to 000000008710c86f +[ 67.597590] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 67.597940] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 67.598275] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 127.497459] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 127.497824] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 127.499438] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000827170b0 +[ 127.499702] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 127.499993] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000072c9d5d8 to 0000000017ea7642 +[ 127.500171] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006450a144 to 0000000017ea7642 +[ 127.606100] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 127.606455] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 127.606792] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 187.487889] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 187.488258] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 187.489927] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000008987c68e +[ 187.490182] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 187.490555] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000c15fa6b7 to 00000000ff2f5b3c +[ 187.490927] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000e0ce4c38 to 00000000ff2f5b3c +[ 187.597095] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 187.597443] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 187.597784] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 247.496944] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 247.497267] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 247.498616] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000084d59a61 +[ 247.498862] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 247.499211] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000004c7de499 to 000000003c9c3d04 +[ 247.499464] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000c81860d to 000000003c9c3d04 +[ 247.604470] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 247.604820] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 247.605164] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 307.488374] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 307.488740] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 307.490392] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000105c9f92 +[ 307.490684] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 307.490981] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000036263828 to 0000000096b86ddb +[ 307.491269] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000074c38614 to 0000000096b86ddb +[ 307.596003] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 307.596353] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 307.596697] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 315.941061] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 315.941155] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 315.941530] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000006bea936f +[ 315.941597] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 315.941675] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000fc8e81fd to 000000008f35dd6e +[ 315.941750] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d5f64486 to 000000008f35dd6e +[ 315.971822] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000f296b664 +[ 315.971931] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 315.972113] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006e5a0f55 to 0000000052cb0ac1 +[ 315.972255] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000008db100ca to 0000000052cb0ac1 +[ 315.989557] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000088afb50 +[ 315.989756] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 315.990075] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 0000000052cb0ac1 +[ 315.990369] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002e900bdf to 0000000052cb0ac1 +[ 316.006551] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000036ac3e2a +[ 316.006779] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.007142] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 0000000068444932 +[ 316.007474] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff0bddfa to 0000000068444932 +[ 316.023268] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 316.023540] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.023961] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000000ba7c32c +[ 316.024277] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007598e897 to 000000000ba7c32c +[ 316.039881] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.040108] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.040508] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 000000001bf0e229 +[ 316.040828] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d1c7c834 to 000000001bf0e229 +[ 316.073342] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 316.073610] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.074034] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 00000000fd993181 +[ 316.074433] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000670f7b8f to 00000000fd993181 +[ 316.089879] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.090106] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.090509] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000006408dae8 +[ 316.090834] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000095adcba to 000000006408dae8 +[ 316.106734] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 316.106961] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.107369] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 000000006408dae8 +[ 316.107685] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000286a41d9 to 000000006408dae8 +[ 316.123172] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.123439] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.123855] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 00000000fd993181 +[ 316.124170] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002b468fe5 to 00000000fd993181 +[ 316.139909] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 316.140135] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.140534] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000001bf0e229 +[ 316.140856] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009645eaed to 000000001bf0e229 +[ 316.173422] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.173696] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.174123] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000000ba7c32c +[ 316.174507] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009132c809 to 000000000ba7c32c +[ 316.188199] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 316.188262] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.188392] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 0000000068444932 +[ 316.188476] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af55b7e5 to 0000000068444932 +[ 316.205252] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.205417] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.205659] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 00000000e73404fb +[ 316.205812] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000860d9a4c to 00000000e73404fb +[ 316.223497] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 316.223725] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.224102] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000009436c5de +[ 316.224436] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000012c51492 to 000000009436c5de +[ 316.239901] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.240127] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.240536] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 000000005725e677 +[ 316.240862] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006f27e5f0 to 000000005725e677 +[ 316.273196] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 316.273509] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.273946] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000005725e677 +[ 316.274260] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009ca40a5e to 000000005725e677 +[ 316.289873] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.290102] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.290509] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000009436c5de +[ 316.290824] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003c43e4e5 to 000000009436c5de +[ 316.306629] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 316.306860] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.307232] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 00000000e73404fb +[ 316.307575] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d31fe53b to 00000000e73404fb +[ 316.323189] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.323464] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.323862] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 0000000068444932 +[ 316.324182] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004b652d2d to 0000000068444932 +[ 316.356864] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 316.357129] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.357572] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005611ad5a to 000000000ba7c32c +[ 316.357943] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d5f91bc5 to 000000000ba7c32c +[ 316.373168] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.373433] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.373849] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000001bf0e229 +[ 316.374167] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ae2cc67e to 000000001bf0e229 +[ 316.389945] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 316.390174] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.390589] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 00000000fd993181 +[ 316.390914] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001cbf0212 to 00000000fd993181 +[ 316.406618] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.406847] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.407215] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005611ad5a to 000000006408dae8 +[ 316.407544] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000aa91b5b0 to 000000006408dae8 +[ 316.439865] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 316.440094] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.440493] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000006408dae8 +[ 316.440816] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000099faf01d to 000000006408dae8 +[ 316.456738] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.456964] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.457362] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 00000000fd993181 +[ 316.457680] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a1ca4328 to 00000000fd993181 +[ 316.473193] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 316.473468] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.473865] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000001bf0e229 +[ 316.474178] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007605cd13 to 000000001bf0e229 +[ 316.489833] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.490053] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.490443] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000000ba7c32c +[ 316.490735] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032dd3b35 to 000000000ba7c32c +[ 316.506588] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 316.506807] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.507155] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 0000000068444932 +[ 316.507486] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff73cae2 to 0000000068444932 +[ 316.540116] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.540423] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.540862] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 00000000e73404fb +[ 316.541225] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000e0ae2a2 to 00000000e73404fb +[ 316.556576] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 316.556805] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.557180] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 000000009436c5de +[ 316.557514] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f7b510d7 to 000000009436c5de +[ 316.573159] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.573427] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.573832] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 000000005725e677 +[ 316.574150] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000fab4298d to 000000005725e677 +[ 316.589783] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 316.590007] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.590407] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000005725e677 +[ 316.590729] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f210ed70 to 000000005725e677 +[ 316.623345] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.623579] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.623970] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000009436c5de +[ 316.624304] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003a69d75c to 000000009436c5de +[ 316.639810] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 316.640038] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.640436] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 00000000e73404fb +[ 316.640761] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000bc6900c2 to 00000000e73404fb +[ 316.656571] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.656800] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.657176] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 0000000068444932 +[ 316.657514] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001511988f to 0000000068444932 +[ 316.689912] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 316.690140] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.690543] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000000ba7c32c +[ 316.690871] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007032a555 to 000000000ba7c32c +[ 316.706539] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.706768] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.707134] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 000000001bf0e229 +[ 316.707473] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af07a7e7 to 000000001bf0e229 +[ 316.723076] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 316.723346] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.723723] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 00000000fd993181 +[ 316.724033] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005bbf695f to 00000000fd993181 +[ 316.739775] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.740002] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.740400] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000006408dae8 +[ 316.740719] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032f62567 to 000000006408dae8 +[ 316.773348] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 316.773586] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.773958] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 000000006408dae8 +[ 316.774293] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000086da0966 to 000000006408dae8 +[ 316.789779] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.790006] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.790405] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 00000000fd993181 +[ 316.790724] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000086da0966 to 00000000fd993181 +[ 316.806584] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 316.806815] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.807195] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000001bf0e229 +[ 316.807525] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032f62567 to 000000001bf0e229 +[ 316.840112] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.840423] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.840870] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000000ba7c32c +[ 316.841235] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005bbf695f to 000000000ba7c32c +[ 316.856517] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 316.856744] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.857117] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 0000000068444932 +[ 316.857448] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af07a7e7 to 0000000068444932 +[ 316.873108] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.873386] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.873796] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 00000000e73404fb +[ 316.874111] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007032a555 to 00000000e73404fb +[ 316.889773] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 316.890001] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.890398] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000009436c5de +[ 316.890713] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001511988f to 000000009436c5de +[ 316.923244] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 316.923518] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.923908] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 000000005725e677 +[ 316.924223] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000bc6900c2 to 000000005725e677 +[ 316.939755] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 316.939985] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.940383] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000005725e677 +[ 316.940707] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003a69d75c to 000000005725e677 +[ 316.956538] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 316.956766] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.957133] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000009436c5de +[ 316.957464] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f210ed70 to 000000009436c5de +[ 316.989907] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 316.990135] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 316.990538] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 00000000e73404fb +[ 316.990857] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000fab4298d to 00000000e73404fb +[ 317.006551] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 317.006780] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.007158] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 0000000068444932 +[ 317.007511] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f7b510d7 to 0000000068444932 +[ 317.023114] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 317.023390] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.023805] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005611ad5a to 000000000ba7c32c +[ 317.024120] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000e0ae2a2 to 000000000ba7c32c +[ 317.056317] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 317.056552] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.056919] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000001bf0e229 +[ 317.057229] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff73cae2 to 000000001bf0e229 +[ 317.073076] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 317.073342] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.073757] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 00000000fd993181 +[ 317.074071] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032dd3b35 to 00000000fd993181 +[ 317.089773] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 317.090000] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.090400] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005611ad5a to 000000006408dae8 +[ 317.090721] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007605cd13 to 000000006408dae8 +[ 317.123324] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 317.123558] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.123932] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000006408dae8 +[ 317.124245] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a1ca4328 to 000000006408dae8 +[ 317.139737] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 317.139966] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.140364] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 00000000fd993181 +[ 317.140687] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000099faf01d to 00000000fd993181 +[ 317.156545] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 317.156775] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.157145] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000001bf0e229 +[ 317.157487] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000aa91b5b0 to 000000001bf0e229 +[ 317.189877] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 317.190106] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.190503] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000000ba7c32c +[ 317.190820] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001cbf0212 to 000000000ba7c32c +[ 317.206490] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 317.206719] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.207086] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 0000000068444932 +[ 317.207420] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ae2cc67e to 0000000068444932 +[ 317.223096] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000001a47882b +[ 317.223366] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.223783] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 00000000e73404fb +[ 317.224096] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d5f91bc5 to 00000000e73404fb +[ 317.256835] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 317.257054] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.257441] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 000000009436c5de +[ 317.257739] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004b652d2d to 000000009436c5de +[ 317.273168] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 317.273436] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.273808] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 000000005725e677 +[ 317.274103] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d31fe53b to 000000005725e677 +[ 317.289744] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 317.289971] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.290364] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000005725e677 +[ 317.290686] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003c43e4e5 to 000000005725e677 +[ 317.323391] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 317.323660] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.324092] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000009436c5de +[ 317.324486] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009ca40a5e to 000000009436c5de +[ 317.339720] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 317.339947] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.340347] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 00000000e73404fb +[ 317.340667] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006f27e5f0 to 00000000e73404fb +[ 317.356460] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 317.356692] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.357062] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 0000000068444932 +[ 317.357397] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000012c51492 to 0000000068444932 +[ 317.390021] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 317.390324] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.390769] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 000000000ba7c32c +[ 317.391133] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000860d9a4c to 000000000ba7c32c +[ 317.406464] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 317.406691] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.407052] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000001bf0e229 +[ 317.407381] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af55b7e5 to 000000001bf0e229 +[ 317.438001] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 317.438067] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.438198] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 00000000fd993181 +[ 317.438293] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009132c809 to 00000000fd993181 +[ 317.454775] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 317.454870] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.455062] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000006408dae8 +[ 317.455207] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009645eaed to 000000006408dae8 +[ 317.473001] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 317.473221] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.473618] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 000000006408dae8 +[ 317.473917] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002b468fe5 to 000000006408dae8 +[ 317.506219] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 317.506494] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.506891] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 00000000fd993181 +[ 317.507209] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000286a41d9 to 00000000fd993181 +[ 317.523001] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 317.523231] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.523640] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000001bf0e229 +[ 317.523954] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000095adcba to 000000001bf0e229 +[ 317.539763] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 317.539993] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.540394] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 000000000ba7c32c +[ 317.540721] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000670f7b8f to 000000000ba7c32c +[ 317.573423] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 317.573689] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.574106] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 0000000068444932 +[ 317.574448] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d1c7c834 to 0000000068444932 +[ 317.589743] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 317.589970] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.590367] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 00000000e73404fb +[ 317.590691] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007598e897 to 00000000e73404fb +[ 317.623228] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 317.623500] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.623897] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 000000009436c5de +[ 317.624208] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff0bddfa to 000000009436c5de +[ 317.639724] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 317.639952] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.640342] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000005725e677 +[ 317.640663] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002e900bdf to 000000005725e677 +[ 317.673191] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 317.673499] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.673936] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000005725e677 +[ 317.674320] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d0c5655f to 000000005725e677 +[ 317.689714] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 317.689942] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.690333] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000009436c5de +[ 317.690651] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004a1f5eb3 to 000000009436c5de +[ 317.706458] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 317.706689] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.707075] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 00000000e73404fb +[ 317.707406] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006c388ada to 00000000e73404fb +[ 317.739954] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 317.740217] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.740672] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 0000000068444932 +[ 317.741048] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006c388ada to 0000000068444932 +[ 317.756400] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 317.756634] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.757026] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 000000000ba7c32c +[ 317.757356] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004a1f5eb3 to 000000000ba7c32c +[ 317.789957] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 317.790221] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.790673] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000001bf0e229 +[ 317.791050] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d0c5655f to 000000001bf0e229 +[ 317.806416] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 317.806647] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.807011] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005611ad5a to 00000000fd993181 +[ 317.807332] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002e900bdf to 00000000fd993181 +[ 317.839935] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 317.840195] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.840649] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000006408dae8 +[ 317.841022] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff0bddfa to 000000006408dae8 +[ 317.856400] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 317.856631] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.857023] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 000000006408dae8 +[ 317.857365] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007598e897 to 000000006408dae8 +[ 317.872976] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 317.873201] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.873615] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 00000000fd993181 +[ 317.873930] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d1c7c834 to 00000000fd993181 +[ 317.906759] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 317.907026] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.907475] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000001bf0e229 +[ 317.907843] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000670f7b8f to 000000001bf0e229 +[ 317.923369] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 317.923638] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.924054] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005611ad5a to 000000000ba7c32c +[ 317.924442] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000095adcba to 000000000ba7c32c +[ 317.956661] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 317.956924] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.957385] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 0000000068444932 +[ 317.957757] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000286a41d9 to 0000000068444932 +[ 317.972955] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 317.973183] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 317.973588] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 00000000e73404fb +[ 317.973909] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002b468fe5 to 00000000e73404fb +[ 318.020360] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 318.020594] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.020968] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000009436c5de +[ 318.021303] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009645eaed to 000000009436c5de +[ 318.056387] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 318.056648] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.057045] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 000000005725e677 +[ 318.057403] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009132c809 to 000000005725e677 +[ 318.072909] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 318.073137] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.073538] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000005725e677 +[ 318.073860] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af55b7e5 to 000000005725e677 +[ 318.106156] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.106427] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.106819] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000009436c5de +[ 318.107132] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000860d9a4c to 000000009436c5de +[ 318.122915] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 318.123140] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.123540] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 00000000e73404fb +[ 318.123856] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000012c51492 to 00000000e73404fb +[ 318.156441] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 318.156673] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.157039] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 0000000068444932 +[ 318.157384] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006f27e5f0 to 0000000068444932 +[ 318.172894] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 318.173122] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.173523] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 000000000ba7c32c +[ 318.173841] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009ca40a5e to 000000000ba7c32c +[ 318.206104] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.206363] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.206769] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000001bf0e229 +[ 318.207081] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003c43e4e5 to 000000001bf0e229 +[ 318.222908] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 318.223137] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.223543] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 00000000fd993181 +[ 318.223865] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d31fe53b to 00000000fd993181 +[ 318.256646] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 318.256911] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.257359] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000006408dae8 +[ 318.257725] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004b652d2d to 000000006408dae8 +[ 318.273505] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 318.273769] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.274187] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 000000006408dae8 +[ 318.274566] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d5f91bc5 to 000000006408dae8 +[ 318.306574] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.306840] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.307285] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 00000000fd993181 +[ 318.307656] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ae2cc67e to 00000000fd993181 +[ 318.322856] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 318.323081] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.323479] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000001bf0e229 +[ 318.323792] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001cbf0212 to 000000001bf0e229 +[ 318.356016] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 318.356243] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.356646] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 000000000ba7c32c +[ 318.356968] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000aa91b5b0 to 000000000ba7c32c +[ 318.390114] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 318.390422] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.390861] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 0000000068444932 +[ 318.391219] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000099faf01d to 0000000068444932 +[ 318.406235] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.406501] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.406894] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 00000000e73404fb +[ 318.407211] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a1ca4328 to 00000000e73404fb +[ 318.439799] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 318.440053] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.440494] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 000000009436c5de +[ 318.440790] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007605cd13 to 000000009436c5de +[ 318.456223] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 318.456493] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.456890] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000005725e677 +[ 318.457200] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032dd3b35 to 000000005725e677 +[ 318.489675] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 318.489905] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.490303] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000005725e677 +[ 318.490621] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff73cae2 to 000000005725e677 +[ 318.506191] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.506458] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.506856] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000009436c5de +[ 318.507167] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000e0ae2a2 to 000000009436c5de +[ 318.539365] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 318.539602] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.539981] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 00000000e73404fb +[ 318.540317] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f7b510d7 to 00000000e73404fb +[ 318.573159] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 318.573467] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.573899] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 0000000068444932 +[ 318.574280] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000fab4298d to 0000000068444932 +[ 318.589616] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 318.589844] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.590220] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 000000000ba7c32c +[ 318.590550] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f210ed70 to 000000000ba7c32c +[ 318.622979] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.623204] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.623608] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000001bf0e229 +[ 318.623927] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003a69d75c to 000000001bf0e229 +[ 318.639594] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 318.639825] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.640192] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000005611ad5a to 00000000fd993181 +[ 318.640521] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000bc6900c2 to 00000000fd993181 +[ 318.672973] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 318.673203] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.673603] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000006408dae8 +[ 318.673928] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001511988f to 000000006408dae8 +[ 318.704402] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 318.704494] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.704683] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 000000006408dae8 +[ 318.704797] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007032a555 to 000000006408dae8 +[ 318.722670] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.722899] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.723298] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 00000000fd993181 +[ 318.723618] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af07a7e7 to 00000000fd993181 +[ 318.756360] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000eb6786ee +[ 318.756594] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.756970] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000001bf0e229 +[ 318.757303] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005bbf695f to 000000001bf0e229 +[ 318.789897] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.790118] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.790502] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000000ba7c32c +[ 318.790798] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032f62567 to 000000000ba7c32c +[ 318.806161] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 318.806438] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.806828] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 0000000068444932 +[ 318.807140] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000086da0966 to 0000000068444932 +[ 318.839575] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 318.839807] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.840184] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 00000000e73404fb +[ 318.840519] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000086da0966 to 00000000e73404fb +[ 318.872964] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 318.873191] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.873596] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 000000009436c5de +[ 318.873915] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032f62567 to 000000009436c5de +[ 318.889652] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 318.889871] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.890208] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 000000005725e677 +[ 318.890547] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005bbf695f to 000000005725e677 +[ 318.922909] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 318.923137] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.923537] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000005725e677 +[ 318.923857] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af07a7e7 to 000000005725e677 +[ 318.939565] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 318.939794] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.940173] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 000000009436c5de +[ 318.940505] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007032a555 to 000000009436c5de +[ 318.973042] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 318.973360] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 318.973812] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 00000000e73404fb +[ 318.974176] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001511988f to 00000000e73404fb +[ 319.006603] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.006871] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.007319] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 0000000068444932 +[ 319.007686] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000bc6900c2 to 0000000068444932 +[ 319.039814] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 319.040077] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.040528] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 000000000ba7c32c +[ 319.040903] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003a69d75c to 000000000ba7c32c +[ 319.056125] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 319.056396] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.056796] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000001bf0e229 +[ 319.057117] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f210ed70 to 000000001bf0e229 +[ 319.089282] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 319.089518] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.089903] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 00000000fd993181 +[ 319.090218] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000fab4298d to 00000000fd993181 +[ 319.122631] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.122860] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.123272] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 000000006408dae8 +[ 319.123589] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f7b510d7 to 000000006408dae8 +[ 319.139559] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 319.139789] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.140164] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 000000006408dae8 +[ 319.140494] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000e0ae2a2 to 000000006408dae8 +[ 319.172923] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 319.173185] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.173635] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 00000000fd993181 +[ 319.173988] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff73cae2 to 00000000fd993181 +[ 319.206316] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 319.206575] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.206974] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000001bf0e229 +[ 319.207339] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032dd3b35 to 000000001bf0e229 +[ 319.239828] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.240093] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.240549] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 000000000ba7c32c +[ 319.240924] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007605cd13 to 000000000ba7c32c +[ 319.256462] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 319.256728] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.257149] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 0000000068444932 +[ 319.257488] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a1ca4328 to 0000000068444932 +[ 319.289705] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 319.289970] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.290428] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 00000000e73404fb +[ 319.290795] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000099faf01d to 00000000e73404fb +[ 319.323097] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 319.323403] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.323844] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 000000009436c5de +[ 319.324208] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000aa91b5b0 to 000000009436c5de +[ 319.356712] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.356977] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.357419] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000005725e677 +[ 319.357783] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001cbf0212 to 000000005725e677 +[ 319.389781] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 319.390043] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.390494] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 000000005725e677 +[ 319.390865] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ae2cc67e to 000000005725e677 +[ 319.406070] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 319.406344] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.406748] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000009436c5de +[ 319.407065] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d5f91bc5 to 000000009436c5de +[ 319.439557] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 319.439785] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.440159] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 00000000e73404fb +[ 319.440494] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004b652d2d to 00000000e73404fb +[ 319.472867] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.473095] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.473494] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 0000000068444932 +[ 319.473818] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d31fe53b to 0000000068444932 +[ 319.506330] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 319.506563] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.506945] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000000ba7c32c +[ 319.507278] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003c43e4e5 to 000000000ba7c32c +[ 319.539491] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 319.539720] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.540099] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000001bf0e229 +[ 319.540438] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009ca40a5e to 000000001bf0e229 +[ 319.556058] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 319.556325] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.556733] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 00000000fd993181 +[ 319.557044] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006f27e5f0 to 00000000fd993181 +[ 319.589561] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.589788] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.590166] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000006408dae8 +[ 319.590504] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000012c51492 to 000000006408dae8 +[ 319.623096] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 319.623407] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.623849] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000006408dae8 +[ 319.624213] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000860d9a4c to 000000006408dae8 +[ 319.656502] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 319.656766] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.657185] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 00000000fd993181 +[ 319.657576] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af55b7e5 to 00000000fd993181 +[ 319.689727] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 319.689991] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.690435] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000001bf0e229 +[ 319.690800] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009132c809 to 000000001bf0e229 +[ 319.722855] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.723087] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.723487] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 000000000ba7c32c +[ 319.723809] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009645eaed to 000000000ba7c32c +[ 319.756531] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 319.756795] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.757208] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 0000000068444932 +[ 319.757590] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002b468fe5 to 0000000068444932 +[ 319.789554] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 319.789782] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.790148] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 00000000e73404fb +[ 319.790480] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000286a41d9 to 00000000e73404fb +[ 319.806053] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 319.806322] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.806720] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000009436c5de +[ 319.807031] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000095adcba to 000000009436c5de +[ 319.839486] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.839716] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.840091] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 000000005725e677 +[ 319.840434] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000670f7b8f to 000000005725e677 +[ 319.873005] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 319.873309] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.873749] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 000000005725e677 +[ 319.874114] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d1c7c834 to 000000005725e677 +[ 319.906510] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 319.906776] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.907194] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 000000009436c5de +[ 319.907584] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007598e897 to 000000009436c5de +[ 319.939115] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 319.939381] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.939769] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 00000000e73404fb +[ 319.940084] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff0bddfa to 00000000e73404fb +[ 319.973049] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 319.973355] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 319.973802] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 0000000068444932 +[ 319.974162] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002e900bdf to 0000000068444932 +[ 320.006448] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 320.006712] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.007130] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000000ba7c32c +[ 320.007519] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d0c5655f to 000000000ba7c32c +[ 320.039503] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 320.039736] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.040107] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 000000001bf0e229 +[ 320.040437] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004a1f5eb3 to 000000001bf0e229 +[ 320.073403] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 320.073667] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.074085] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 00000000fd993181 +[ 320.074480] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006c388ada to 00000000fd993181 +[ 320.106459] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 320.106727] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.107142] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000006408dae8 +[ 320.107527] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006c388ada to 000000006408dae8 +[ 320.139470] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 320.139736] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.140152] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000006408dae8 +[ 320.140537] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004a1f5eb3 to 000000006408dae8 +[ 320.172978] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 320.173282] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.173721] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 00000000fd993181 +[ 320.174086] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d0c5655f to 00000000fd993181 +[ 320.206464] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 320.206731] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.207158] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 000000001bf0e229 +[ 320.207541] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002e900bdf to 000000001bf0e229 +[ 320.239276] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 320.239510] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.239880] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 000000000ba7c32c +[ 320.240196] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff0bddfa to 000000000ba7c32c +[ 320.272978] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 320.273285] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.273729] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 0000000068444932 +[ 320.274094] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007598e897 to 0000000068444932 +[ 320.306450] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 320.306714] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.307138] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 00000000e73404fb +[ 320.307525] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d1c7c834 to 00000000e73404fb +[ 320.339818] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 320.340081] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.340537] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000009abab35 to 000000009436c5de +[ 320.340910] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000670f7b8f to 000000009436c5de +[ 320.389722] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 320.390012] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.390406] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000005725e677 +[ 320.390721] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000095adcba to 000000005725e677 +[ 320.422673] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 320.422903] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.423300] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 000000005725e677 +[ 320.423621] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000286a41d9 to 000000005725e677 +[ 320.456126] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 320.456398] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.456798] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000009436c5de +[ 320.457112] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002b468fe5 to 000000009436c5de +[ 320.489209] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 320.489488] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.489889] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 00000000e73404fb +[ 320.490209] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009645eaed to 00000000e73404fb +[ 320.522845] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 320.523120] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.523516] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 0000000068444932 +[ 320.523841] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009132c809 to 0000000068444932 +[ 320.556417] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 320.556682] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.557107] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000000ba7c32c +[ 320.557484] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af55b7e5 to 000000000ba7c32c +[ 320.606566] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 320.606828] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.607270] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 000000001bf0e229 +[ 320.607637] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000860d9a4c to 000000001bf0e229 +[ 320.639203] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002c41e6a2 +[ 320.639475] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.639876] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 00000000fd993181 +[ 320.640192] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000012c51492 to 00000000fd993181 +[ 320.672447] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 320.672676] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.673048] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000006408dae8 +[ 320.673387] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000006f27e5f0 to 000000006408dae8 +[ 320.706149] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 320.706423] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.706820] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000006408dae8 +[ 320.707130] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000009ca40a5e to 000000006408dae8 +[ 320.756171] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 320.756480] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.756909] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 00000000fd993181 +[ 320.757295] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003c43e4e5 to 00000000fd993181 +[ 320.789095] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 320.789338] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.789728] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000001bf0e229 +[ 320.789999] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d31fe53b to 000000001bf0e229 +[ 320.822879] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 320.823101] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.823485] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000000ba7c32c +[ 320.823778] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004b652d2d to 000000000ba7c32c +[ 320.855666] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 320.855892] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.856292] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 0000000068444932 +[ 320.856614] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d5f91bc5 to 0000000068444932 +[ 320.905969] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 320.906197] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.906594] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 00000000e73404fb +[ 320.906914] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ae2cc67e to 00000000e73404fb +[ 320.939403] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 320.939632] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.940010] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 000000009436c5de +[ 320.940344] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001cbf0212 to 000000009436c5de +[ 320.972790] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 320.973049] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 320.973445] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000005725e677 +[ 320.973768] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000aa91b5b0 to 000000005725e677 +[ 321.023158] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 321.023465] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.023907] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000005725e677 +[ 321.024296] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000099faf01d to 000000005725e677 +[ 321.055860] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 321.056086] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.056487] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000009436c5de +[ 321.056814] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a1ca4328 to 000000009436c5de +[ 321.105900] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 321.106127] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.106528] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 00000000e73404fb +[ 321.106844] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007605cd13 to 00000000e73404fb +[ 321.137368] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 321.137421] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.137503] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000050fc2a1f to 0000000068444932 +[ 321.137571] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032dd3b35 to 0000000068444932 +[ 321.170930] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 321.171028] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.171183] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 000000000ba7c32c +[ 321.171326] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff73cae2 to 000000000ba7c32c +[ 321.222424] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 321.222652] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.223017] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 000000001bf0e229 +[ 321.223355] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000e0ae2a2 to 000000001bf0e229 +[ 321.254731] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 321.254795] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.254934] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 00000000fd993181 +[ 321.255016] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f7b510d7 to 00000000fd993181 +[ 321.306442] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 321.306670] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.307035] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 000000006408dae8 +[ 321.307369] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000fab4298d to 000000006408dae8 +[ 321.355841] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 321.356068] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.356476] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 000000006408dae8 +[ 321.356797] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f210ed70 to 000000006408dae8 +[ 321.387798] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 321.387858] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.387987] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 00000000fd993181 +[ 321.388063] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003a69d75c to 00000000fd993181 +[ 321.438965] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 321.439191] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.439588] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000001bf0e229 +[ 321.439910] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000bc6900c2 to 000000001bf0e229 +[ 321.472791] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 321.473021] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.473416] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 000000000ba7c32c +[ 321.473736] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001511988f to 000000000ba7c32c +[ 321.522696] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 321.522923] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.523322] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 0000000068444932 +[ 321.523641] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007032a555 to 0000000068444932 +[ 321.572388] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 321.572615] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.572973] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 00000000e73404fb +[ 321.573310] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af07a7e7 to 00000000e73404fb +[ 321.605645] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 321.605874] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.606273] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 000000009436c5de +[ 321.606591] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005bbf695f to 000000009436c5de +[ 321.655833] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 321.656060] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.656463] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 000000005725e677 +[ 321.656792] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032f62567 to 000000005725e677 +[ 321.706424] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 321.706687] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.707100] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 000000005725e677 +[ 321.707484] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000086da0966 to 000000005725e677 +[ 321.755959] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 321.756265] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.756702] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a45193f3 to 000000009436c5de +[ 321.757063] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000086da0966 to 000000009436c5de +[ 321.789557] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 321.789819] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.790257] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000001d635ddf to 00000000e73404fb +[ 321.790620] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000032f62567 to 00000000e73404fb +[ 321.839737] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 321.839966] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.840361] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000be59cb19 to 0000000068444932 +[ 321.840678] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005bbf695f to 0000000068444932 +[ 321.889321] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 321.889552] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.889929] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000296a318c to 000000000ba7c32c +[ 321.890264] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000af07a7e7 to 000000000ba7c32c +[ 321.939638] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 321.939866] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.940258] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000e0325007 to 000000001bf0e229 +[ 321.940589] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007032a555 to 000000001bf0e229 +[ 321.988321] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000e78358d0 +[ 321.988420] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 321.988584] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008f8b1cb5 to 00000000fd993181 +[ 321.988704] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000001511988f to 00000000fd993181 +[ 322.039155] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 322.039424] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.039827] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006475263b to 000000006408dae8 +[ 322.040139] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000bc6900c2 to 000000006408dae8 +[ 322.089384] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000001a47882b +[ 322.089613] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.089978] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006db83c8e to 000000006408dae8 +[ 322.090311] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000003a69d75c to 000000006408dae8 +[ 322.139362] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 322.139591] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.139957] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000dbdb1ead to 00000000fd993181 +[ 322.140292] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f210ed70 to 00000000fd993181 +[ 322.188459] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000035dc3d93 +[ 322.188576] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.188765] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ed8a5e71 to 000000001bf0e229 +[ 322.188916] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000fab4298d to 000000001bf0e229 +[ 322.239134] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000075a6cd4e +[ 322.239404] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.239788] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007b922054 to 000000000ba7c32c +[ 322.240097] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f7b510d7 to 000000000ba7c32c +[ 322.289359] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004dee76d3 +[ 322.289587] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.289953] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006d1fcf28 to 0000000068444932 +[ 322.290288] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000e0ae2a2 to 0000000068444932 +[ 322.355394] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000005f7cb55e +[ 322.355577] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.355902] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d0779b06 to 00000000e73404fb +[ 322.356146] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000ff73cae2 to 00000000e73404fb +[ 322.406080] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000027953542 +[ 322.406335] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.406693] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000002f203824 to 00000000b24c7c9b +[ 322.406986] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005d8fad14 to 00000000b24c7c9b +[ 322.454387] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000089557617 +[ 322.454492] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.454654] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000003ee26382 to 0000000084bbc205 +[ 322.454788] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005328c6ab to 0000000084bbc205 +[ 322.522599] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000a1f3e6a3 +[ 322.522862] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.523300] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000003ee26382 to 000000009ac420cf +[ 322.523659] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005da10ebe to 000000009ac420cf +[ 322.572807] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000051b1d9b2 +[ 322.573069] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.573527] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000002f203824 to 00000000019afa00 +[ 322.573896] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000b869fd6f to 00000000019afa00 +[ 322.639663] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002f22346f +[ 322.639925] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.640369] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000009952da61 to 00000000a69e5e5a +[ 322.640739] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000c7a6b4b to 00000000a69e5e5a +[ 322.688763] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d64f2376 +[ 322.689027] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.689488] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000087214c6d to 00000000d3f4e416 +[ 322.689811] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000edf516e3 to 00000000d3f4e416 +[ 322.755916] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000c620429e +[ 322.756180] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.756645] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000c8cd6a0a to 00000000270a29e5 +[ 322.756961] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a0c0a5e9 to 00000000270a29e5 +[ 322.822985] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d64f2376 +[ 322.823293] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.823738] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007221143d to 00000000b99890f0 +[ 322.824102] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007622d990 to 00000000b99890f0 +[ 322.889660] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002f22346f +[ 322.889925] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.890369] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000645ebf90 to 00000000b99890f0 +[ 322.890736] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000b65f7cfc to 00000000b99890f0 +[ 322.939417] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000051b1d9b2 +[ 322.939680] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 322.940091] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000d900ef88 to 00000000270a29e5 +[ 322.940480] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002f72be68 to 00000000270a29e5 +[ 323.006013] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000a1f3e6a3 +[ 323.006316] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.006752] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007d0e7f4c to 00000000d3f4e416 +[ 323.007113] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f088fab0 to 00000000d3f4e416 +[ 323.072661] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000089557617 +[ 323.072926] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.073369] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000060f296f1 to 00000000a69e5e5a +[ 323.073726] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005f5fda96 to 00000000a69e5e5a +[ 323.155632] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000027953542 +[ 323.155903] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.156348] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000086b3446e to 00000000019afa00 +[ 323.156721] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004133e849 to 00000000019afa00 +[ 323.222357] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d5b07c8a +[ 323.222621] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.223034] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ff36063a to 000000009ac420cf +[ 323.223427] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f171e67e to 000000009ac420cf +[ 323.288444] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000068906714 +[ 323.288592] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.288843] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006c972397 to 0000000084bbc205 +[ 323.289040] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000070ddc50e to 0000000084bbc205 +[ 323.372611] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000646bc720 +[ 323.372841] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.373238] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000071d14689 to 00000000b24c7c9b +[ 323.373553] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d0ae589b to 00000000b24c7c9b +[ 323.438903] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005519a74b +[ 323.439132] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.439533] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000006685de0 to 000000008a6c4e8d +[ 323.439936] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002549f906 to 000000008a6c4e8d +[ 323.522158] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 000000004f59af44 +[ 323.522427] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.522807] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000245056d6 to 0000000068d23289 +[ 323.523119] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000704c516d to 0000000068d23289 +[ 323.606484] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005f7b0c28 +[ 323.606713] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.607081] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000ee18a62c to 00000000fabba15c +[ 323.607419] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000704c516d to 00000000fabba15c +[ 323.688498] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d64f2376 +[ 323.688729] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.689103] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008364fdce to 00000000d375e97a +[ 323.689426] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002549f906 to 00000000d375e97a +[ 323.772603] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000002f22346f +[ 323.772867] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.773299] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000006f56799e to 0000000059061cbb +[ 323.773660] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000d0ae589b to 0000000059061cbb +[ 323.872922] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000051b1d9b2 +[ 323.873225] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.873656] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000bdb2105d to 00000000705a1ad0 +[ 323.874020] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000070ddc50e to 00000000705a1ad0 +[ 323.972291] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000a1f3e6a3 +[ 323.972559] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 323.972985] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000a4f1a0ee to 000000006f1d7fca +[ 323.973369] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f171e67e to 000000006f1d7fca +[ 324.073130] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 0000000089557617 +[ 324.073465] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 324.073666] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000060c2678 to 000000006f1d7fca +[ 324.073783] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000004133e849 to 000000006f1d7fca +[ 324.172821] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000b096f16c +[ 324.173074] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 324.173555] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008854f4b1 to 00000000705a1ad0 +[ 324.173898] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000005f5fda96 to 00000000705a1ad0 +[ 324.283763] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 324.284160] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 324.284540] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 324.287644] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 324.288016] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 324.289273] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d5b07c8a +[ 324.289537] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 324.289888] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000008d04a490 to 0000000059061cbb +[ 324.290258] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000f088fab0 to 0000000059061cbb +[ 324.395397] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 324.395800] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 324.396137] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 324.421118] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 324.421537] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 324.422775] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 0000000068906714 +[ 324.423036] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 324.423413] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000b8190764 to 00000000d375e97a +[ 324.423766] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000002f72be68 to 00000000d375e97a +[ 324.531760] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 324.532152] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 324.532544] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 324.554817] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 324.555227] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 324.556476] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000646bc720 +[ 324.556738] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 324.557091] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000f94c7380 to 00000000fabba15c +[ 324.557467] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000b65f7cfc to 00000000fabba15c +[ 324.667353] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 324.667748] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 324.668085] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 324.687731] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 324.688127] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 324.688611] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000005519a74b +[ 324.688691] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 324.688787] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000001ca2969 to 0000000068d23289 +[ 324.688884] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000007622d990 to 0000000068d23289 +[ 324.795758] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 324.796151] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 324.796541] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 324.871380] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 324.871778] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 324.873110] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d64f2376 +[ 324.873402] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 324.873755] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000c1f90824 to 000000008a6c4e8d +[ 324.874104] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000a0c0a5e9 to 000000008a6c4e8d +[ 324.979730] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 324.980085] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 324.980424] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 325.054743] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 325.055133] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 325.056399] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000c620429e +[ 325.056661] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 325.057010] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000026d97fa4 to 00000000b24c7c9b +[ 325.057389] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000edf516e3 to 00000000b24c7c9b +[ 325.163739] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 325.164091] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 325.164440] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 325.321337] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 325.321727] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 325.322984] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000b3fe1f21 +[ 325.323273] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 325.323628] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000605e8c00 to 0000000084bbc205 +[ 325.323978] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000000c7a6b4b to 0000000084bbc205 +[ 325.435745] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 325.436148] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 325.436530] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 325.960462] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 325.960586] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 325.960974] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000004f59af44 +[ 325.961048] i915 0000:00:02.0: [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000005519a74b to [NOCRTC] +[ 325.961080] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005519a74b +[ 325.961174] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 325.961279] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 +[ 325.961378] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 00000000c49ec285 to 000000009ac420cf +[ 325.961482] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000b869fd6f to 000000009ac420cf +[ 325.961577] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm +[ 325.961646] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 2, 3, 3, 5, 6, 6, 7, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 325.961713] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 9, 9, 11, 11, 17, 20, 20, 23, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 325.961778] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 10, 10, 12, 12, 18, 21, 21, 24, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +[ 326.075731] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 326.076076] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 326.076418] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 367.487323] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 367.487421] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 367.487810] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000d64f2376 +[ 367.487871] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 367.487950] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000069195890 to 00000000019afa00 +[ 367.488031] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000068aac624 to 00000000019afa00 +[ 367.595237] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 367.595570] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 367.595887] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 427.488425] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 427.488624] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 427.489586] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 00000000b3fe1f21 +[ 427.489722] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 427.489902] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 000000007a1cf8df to 00000000a69e5e5a +[ 427.490077] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 0000000077b25317 to 00000000a69e5e5a +[ 427.602750] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 427.603094] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 427.603427] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 487.480581] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 487.480716] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 487.481296] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:128] for [PLANE:31:plane 1A] state 00000000a713a431 +[ 487.481394] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 487.481512] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000007ae5785 to 000000001a6e0872 +[ 487.481627] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 00000000fa6fb80e to 000000001a6e0872 +[ 487.585837] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 487.586196] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 487.586550] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 +[ 547.487913] i915 0000:00:02.0: [drm:__intel_display_power_get_domain.part.0 [i915]] enabling DC off +[ 547.488114] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 +[ 547.489129] i915 0000:00:02.0: [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:125] for [PLANE:31:plane 1A] state 000000009ef8cbd4 +[ 547.489301] i915 0000:00:02.0: [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 +[ 547.489523] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000002a02f336 state 0000000090aba3d1 to 00000000756d0f1e +[ 547.489771] i915 0000:00:02.0: [drm:intel_atomic_get_global_obj_state [i915]] Added new global object 000000001af8bdd1 state 000000008b9b3877 to 00000000756d0f1e +[ 547.593123] i915 0000:00:02.0: [drm:__intel_display_power_put_domain [i915]] disabling DC off +[ 547.593593] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +[ 547.593928] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 diff --git a/i915_dp.c b/i915_dp.c new file mode 100644 index 0000000..c48cb14 --- /dev/null +++ b/i915_dp.c @@ -0,0 +1,3287 @@ +#include "i915_controller.h" +#include "i915_debug.h" +#include "i915_gmbus.h" +#include "i915_ddi.h" +#include "i915_dp.h" +#include "i915_hdmi.h" +#include "i915_reg.h" +#include +#include + +/* Cedartrail */ +#define PP_ON_DELAYS 0x61208 /* Cedartrail */ +#define PANEL_PORT_SELECT_MASK (3 << 30) +#define PANEL_PORT_SELECT_LVDS (0 << 30) +#define PANEL_PORT_SELECT_EDP (1 << 30) +#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) +#define PANEL_POWER_UP_DELAY_SHIFT 16 +#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) +#define PANEL_LIGHT_ON_DELAY_SHIFT 0 + +#define PP_OFF_DELAYS 0x6120c /* Cedartrail */ +#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) +#define PANEL_POWER_DOWN_DELAY_SHIFT 16 +#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) +#define PANEL_LIGHT_OFF_DELAY_SHIFT 0 + +//#define PP_DIVISOR 0x61210 /* Cedartrail */ +#define PP_REFERENCE_DIVIDER_MASK (0xffffff00) +#define PP_REFERENCE_DIVIDER_SHIFT 8 +#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) +#define PANEL_POWER_CYCLE_DELAY_SHIFT 0 +static bool edp_panel_vdd_on(struct intel_dp *intel_dp); + +void memcpy(void *dest, void *src, UINTN n) +{ + // Typecast src and dest addresses to (char *) + char *csrc = (char *)src; + char *cdest = (char *)dest; + + // Copy contents of src[] to dest[] + for (int i = 0; i < n; i++) + cdest[i] = csrc[i]; +} +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max/clamp at all, of course. + */ +#define min_t(type, x, y) ( \ + { \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1 : __min2; \ + }) + +#define max_t(type, x, y) ( \ + { \ + type __max1 = (x); \ + type __max2 = (y); \ + __max1 > __max2 ? __max1 : __max2; \ + }) +static int max(int in1, int in2) +{ + return max_t(int, in1, in2); +} +/** + * clamp_t - return a value clamped to a given range using a given type + * @type: the type of variable to use + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of type + * 'type' to make all the comparisons. + */ +#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi) + +EFI_STATUS ReadEDIDDP(EDID *result, i915_CONTROLLER *controller, UINT8 pin) +{ + + UINT32 *p = (UINT32 *)result; + edp_panel_vdd_on(controller->intel_dp); + + PRINT_DEBUG(EFI_D_ERROR, "trying DP aux %d\n", pin); + // aux message header is 3-4 bytes: ctrl8 addr16 len8 + // the data is big endian + // len is receive buffer size-1 + // i2c init + UINT32 send_ctl = + (DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_TIME_OUT_MAX | + DP_AUX_CH_CTL_RECEIVE_ERROR | (3 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32)); + /* Must try at least 3 times according to DP spec, WHICH WE DON'T CARE */ + controller->write32(_DPA_AUX_CH_DATA1 + (pin << 8), + ((AUX_I2C_MOT | AUX_I2C_WRITE) << 28) | (0x50 << 8) | + 0); + controller->write32(_DPA_AUX_CH_CTL + (pin << 8), send_ctl); + UINT32 aux_status; + UINT32 counter = 0; + for (;;) + { + aux_status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8)); + if (!(aux_status & DP_AUX_CH_CTL_SEND_BUSY)) + { + break; + } + counter += 1; + if (counter >= 1500) + { + PRINT_DEBUG(EFI_D_ERROR, "DP AUX channel timeout"); + break; + } + gBS->Stall(10); + } + controller->write32(_DPA_AUX_CH_CTL + (pin << 8), + aux_status | DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR); + // i2c send 1 byte + send_ctl = + (DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_TIME_OUT_MAX | + DP_AUX_CH_CTL_RECEIVE_ERROR | (5 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32)); + controller->write32(_DPA_AUX_CH_DATA1 + (pin << 8), + (AUX_I2C_WRITE << 28) | (0x50 << 8) | 0); + controller->write32(_DPA_AUX_CH_DATA2 + (pin << 8), 0); + controller->write32(_DPA_AUX_CH_CTL + (pin << 8), send_ctl); + counter = 0; + for (;;) + { + aux_status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8)); + if (!(aux_status & DP_AUX_CH_CTL_SEND_BUSY)) + { + break; + } + counter += 1; + if (counter >= 1500) + { + PRINT_DEBUG(EFI_D_ERROR, "DP AUX channel timeout"); + break; + } + gBS->Stall(10); + } + controller->write32(_DPA_AUX_CH_CTL + (pin << 8), + aux_status | DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR); + if (aux_status & + (DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_RECEIVE_ERROR)) + { + return EFI_NOT_FOUND; + } + // i2c read 1 byte * 128 + PRINT_DEBUG(EFI_D_ERROR, "reading DP aux %d\n", pin); + // aux message header is 3-4 bytes: ctrl8 addr16 len8 + // the data is big endian + // len is receive buffer size-1 + // i2c init + send_ctl = + (DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_TIME_OUT_MAX | + DP_AUX_CH_CTL_RECEIVE_ERROR | (3 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32)); + /* Must try at least 3 times according to DP spec, WHICH WE DON'T CARE */ + controller->write32(_DPA_AUX_CH_DATA1 + (pin << 8), + ((AUX_I2C_MOT | AUX_I2C_READ) << 28) | (0x50 << 8) | 0); + controller->write32(_DPA_AUX_CH_CTL + (pin << 8), send_ctl); + counter = 0; + for (;;) + { + aux_status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8)); + if (!(aux_status & DP_AUX_CH_CTL_SEND_BUSY)) + { + break; + } + counter += 1; + if (counter >= 1500) + { + PRINT_DEBUG(EFI_D_ERROR, "DP AUX channel timeout"); + break; + } + gBS->Stall(10); + } + controller->write32(_DPA_AUX_CH_CTL + (pin << 8), + aux_status | DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR); + UINT32 i = 0; + for (i = 0; i < 128; i++) + { + send_ctl = (DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_TIME_OUT_MAX | + DP_AUX_CH_CTL_RECEIVE_ERROR | + (4 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32)); + controller->write32(_DPA_AUX_CH_DATA1 + (pin << 8), + (AUX_I2C_READ << 28) | (0x50 << 8) | 0); + controller->write32(_DPA_AUX_CH_CTL + (pin << 8), send_ctl); + counter = 0; + for (;;) + { + aux_status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8)); + if (!(aux_status & DP_AUX_CH_CTL_SEND_BUSY)) + { + break; + } + counter += 1; + if (counter >= 1500) + { + PRINT_DEBUG(EFI_D_ERROR, "DP AUX channel timeout"); + break; + } + gBS->Stall(10); + } + controller->write32(_DPA_AUX_CH_CTL + (pin << 8), + aux_status | DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR); + UINT32 word = controller->read32(_DPA_AUX_CH_DATA1 + (pin << 8)); + ((UINT8 *)p)[i] = (word >> 16) & 0xff; + } + for (UINT32 i = 0; i < 16; i++) + { + for (UINT32 j = 0; j < 8; j++) + { + DebugPrint(EFI_D_ERROR, "%02x ", ((UINT8 *)(p))[i * 8 + j]); + } + DebugPrint(EFI_D_ERROR, "\n"); + } + if (i >= 128 && *(UINT64 *)result->magic == 0x00FFFFFFFFFFFF00uLL) + { + controller->OutputPath.AuxCh = pin; + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +static int cnp_rawclk(i915_CONTROLLER *controller) +{ + int divider, fraction; + + if (controller->read32(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) + { + /* 24 MHz */ + divider = 24000; + fraction = 0; + } + else + { + /* 19.2 MHz */ + divider = 19000; + fraction = 200; + } + + /* rawclk = CNP_RAWCLK_DIV(divider / 1000); + if (fraction) { + int numerator = 1; + + rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, + fraction) - 1); + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + rawclk |= ICP_RAWCLK_NUM(numerator); + } + + controller->write32(PCH_RAWCLK_FREQ, rawclk); */ + return divider + fraction; +} + +// //WE CAN USE THIS TO GET BETTER DELAY VALUES +// // static void +// // intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) +// // { +// // //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); +// // //struct edp_power_seq cur, vbt, spec; +// // //*final = &intel_dp->pps_delays; + +// // //lockdep_assert_held(&dev_priv->pps_mutex); + +// // /* already initialized? */ +// // if (final->t11_t12 != 0) +// // return; + +// // intel_pps_readout_hw_state(intel_dp, &cur); + +// // intel_pps_dump_state("cur", &cur); + +// // vbt = dev_priv->vbt.edp.pps; +// // /* On Toshiba Satellite P50-C-18C system the VBT T12 delay +// // * of 500ms appears to be too short. Ocassionally the panel +// // * just fails to power back on. Increasing the delay to 800ms +// // * seems sufficient to avoid this problem. +// // */ +// // if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { +// // vbt.t11_t12 = max_t(UINT16, vbt.t11_t12, 1300 * 10); +// // drm_dbg_kms(&dev_priv->drm, +// // "Increasing T12 panel delay as per the quirk to %d\n", +// // vbt.t11_t12); +// // } +// // /* T11_T12 delay is special and actually in units of 100ms, but zero +// // * based in the hw (so we need to add 100 ms). But the sw vbt +// // * table multiplies it with 1000 to make it in units of 100usec, +// // * too. */ +// // vbt.t11_t12 += 100 * 10; + +// // /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of +// // * our hw here, which are all in 100usec. */ +// // spec.t1_t3 = 210 * 10; +// // spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ +// // spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ +// // spec.t10 = 500 * 10; +// // /* This one is special and actually in units of 100ms, but zero +// // * based in the hw (so we need to add 100 ms). But the sw vbt +// // * table multiplies it with 1000 to make it in units of 100usec, +// // * too. */ +// // spec.t11_t12 = (510 + 100) * 10; + +// // intel_pps_dump_state("vbt", &vbt); + +// // /* Use the max of the register settings and vbt. If both are +// // * unset, fall back to the spec limits. */ +// // #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? spec.field : max(cur.field, vbt.field)) +// // assign_final(t1_t3); +// // assign_final(t8); +// // assign_final(t9); +// // assign_final(t10); +// // assign_final(t11_t12); +// // #undef assign_final + +// // #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) +// // intel_dp->panel_power_up_delay = get_delay(t1_t3); +// // intel_dp->backlight_on_delay = get_delay(t8); +// // intel_dp->backlight_off_delay = get_delay(t9); +// // intel_dp->panel_power_down_delay = get_delay(t10); +// // intel_dp->panel_power_cycle_delay = get_delay(t11_t12); +// // #undef get_delay + +// // drm_dbg_kms(&dev_priv->drm, +// // "panel power up delay %d, power down delay %d, power cycle delay %d\n", +// // intel_dp->panel_power_up_delay, +// // intel_dp->panel_power_down_delay, +// // intel_dp->panel_power_cycle_delay); + +// // drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n", +// // intel_dp->backlight_on_delay, +// // intel_dp->backlight_off_delay); + +// // /* +// // * We override the HW backlight delays to 1 because we do manual waits +// // * on them. For T8, even BSpec recommends doing it. For T9, if we +// // * don't do this, we'll end up waiting for the backlight off delay +// // * twice: once when we do the manual sleep, and once when we disable +// // * the panel and wait for the PP_STATUS bit to become zero. +// // */ +// // final->t8 = 1; +// // final->t9 = 1; + +// // /* +// // * HW has only a 100msec granularity for t11_t12 so round it up +// // * accordingly. +// // */ +// // final->t11_t12 = roundup(final->t11_t12, 100 * 10); +// // } +// static void +// intel_dp_init_panel_power_sequencer_registers(i915_CONTROLLER *controller) +// { +// //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); +// UINT32 pp_on, pp_off, port_sel = 0; +// //int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; +// int div = cnp_rawclk(controller); //Varies by generation +// //struct pps_registers regs; +// //UINT32 port = controller->OutputPath.Port; +// //const struct edp_power_seq *seq = &intel_dp->pps_delays; + +// // lockdep_assert_held(&dev_priv->pps_mutex); + +// // intel_pps_get_registers(intel_dp, ®s); + +// //units are 100us +// pp_on = (2100 << 15) | +// (500); +// pp_off = (5000 << 15) | +// (500); +// /* Haswell doesn't have any port selection bits for the panel +// * power sequencer any more. */ +// /* +// if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { +// port_sel = PANEL_PORT_SELECT_VLV(port); +// } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { +// switch (port) { +// case PORT_A: +// port_sel = PANEL_PORT_SELECT_DPA; +// break; +// case PORT_C: +// port_sel = PANEL_PORT_SELECT_DPC; +// break; +// case PORT_D: +// port_sel = PANEL_PORT_SELECT_DPD; +// break; +// default: +// MISSING_CASE(port); +// break; +// } +// } +// */ +// pp_on |= port_sel; + +// controller->write32(PP_ON, pp_on); +// controller->write32(PP_OFF, pp_off); + +// /* +// * Compute the divisor for the pp clock, simply match the Bspec formula. +// */ +// //if (i915_mmio_reg_valid(PP_DIVISOR)) { +// controller->write32(PP_DIVISOR, +// (((100 * div) / 2 - 1) << 7) | 11); +// // controller->write32(PP_DIVISOR, +// // 0xffffffff); +// /* } else { USED FOR Gens where divisor is in cntrl var +// UINT32 pp_ctl; + +// pp_ctl = controller->read32( regs.pp_ctrl); +// pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; +// pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); +// controller->write32(regs.pp_ctrl, pp_ctl); +// } */ + +// PRINT_DEBUG(EFI_D_ERROR, +// "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", +// controller->read32(PP_ON), +// controller->read32(PP_OFF), +// controller->read32(PP_DIVISOR)); +// } +struct pps_registers +{ + UINT64 pp_ctrl; + UINT64 pp_stat; + UINT64 pp_on; + UINT64 pp_off; + UINT64 pp_div; +}; + +static void intel_pps_get_registers(struct intel_dp *intel_dp, + struct pps_registers *regs) +{ + //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + // int pps_idx = 0; + gBS->SetMem(regs, sizeof(*regs), 0); + //memset(regs, 0, sizeof(*regs)); + + // if (IS_GEN9_LP(dev_priv)) + // pps_idx = bxt_power_sequencer_idx(intel_dp); + // else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + // pps_idx = vlv_power_sequencer_pipe(intel_dp); + + regs->pp_ctrl = PP_CONTROL; + regs->pp_stat = PP_STATUS; + regs->pp_on = PP_ON_DELAYS; + regs->pp_off = PP_OFF_DELAYS; + regs->pp_div = PP_DIVISOR; +} +static u32 ironlake_get_pp_control(i915_CONTROLLER *controller) +{ + //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u32 control; + + // lockdep_assert_held(&dev_priv->pps_mutex); + + control = controller->read32(PP_CONTROL); + if ((control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS) + { + control &= ~PANEL_UNLOCK_MASK; + control |= PANEL_UNLOCK_REGS; + } + return control; +} +static void +intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) +{ + // struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; + struct pps_registers regs; + + intel_pps_get_registers(intel_dp, ®s); + + /* Workaround: Need to write PP_CONTROL with the unlock key as + * the very first thing. */ + pp_ctl = ironlake_get_pp_control(intel_dp->controller); + + pp_on = intel_dp->controller->read32(regs.pp_on); + pp_off = intel_dp->controller->read32(regs.pp_off); + // if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && + // !HAS_PCH_ICP(dev_priv)) + // { + intel_dp->controller->write32(regs.pp_ctrl, pp_ctl); + pp_div = intel_dp->controller->read32(regs.pp_div); + // } + + /* Pull timing values out of registers */ + seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> + PANEL_POWER_UP_DELAY_SHIFT; + + seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> + PANEL_LIGHT_ON_DELAY_SHIFT; + + seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> + PANEL_LIGHT_OFF_DELAY_SHIFT; + + seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> + PANEL_POWER_DOWN_DELAY_SHIFT; + + // if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || + // HAS_PCH_ICP(dev_priv)) + // { + // seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> + // BXT_POWER_CYCLE_DELAY_SHIFT) * + // 1000; + // } + // else + //{ + seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> + PANEL_POWER_CYCLE_DELAY_SHIFT) * + 1000; + //} +} + +static void +intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) +{ + PRINT_DEBUG(EFI_D_ERROR, "%a t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", + state_name, + seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); +} +static void +intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) +{ + //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct edp_power_seq cur, vbt, spec, + *final = &intel_dp->pps_delays; + + // lockdep_assert_held(&dev_priv->pps_mutex); + + + /* already initialized? */ + if (final->t11_t12 != 0) { + PRINT_DEBUG(EFI_D_ERROR, "PPS already set. Exiting. t11_t12: %d\n", final->t11_t12); + return; + } + intel_pps_readout_hw_state(intel_dp, &cur); + + intel_pps_dump_state("cur", &cur); + + vbt = intel_dp->controller->vbt.edp.pps; + // /* On Toshiba Satellite P50-C-18C system the VBT T12 delay + // * of 500ms appears to be too short. Ocassionally the panel + // * just fails to power back on. Increasing the delay to 800ms + // * seems sufficient to avoid this problem. + // */ + // if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) + // { + // vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); + // PRINT_DEBUG(EFI_D_ERROR,"Increasing T12 panel delay as per the quirk to %d\n", + // vbt.t11_t12); + // } + /* T11_T12 delay is special and actually in units of 100ms, but zero + * based in the hw (so we need to add 100 ms). But the sw vbt + * table multiplies it with 1000 to make it in units of 100usec, + * too. */ + vbt.t11_t12 += 100 * 10; + + /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of + * our hw here, which are all in 100usec. */ + spec.t1_t3 = 210 * 10; + spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ + spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ + spec.t10 = 500 * 10; + /* This one is special and actually in units of 100ms, but zero + * based in the hw (so we need to add 100 ms). But the sw vbt + * table multiplies it with 1000 to make it in units of 100usec, + * too. */ + spec.t11_t12 = (510 + 100) * 10; + + intel_pps_dump_state("vbt", &vbt); + + /* Use the max of the register settings and vbt. If both are + * unset, fall back to the spec limits. */ +#define assign_final(field) do {\ + final->field = (max(cur.field, vbt.field) == 0 ? spec.field : max(cur.field, vbt.field)); \ + PRINT_DEBUG(EFI_D_ERROR, "Assigning val %d as cur: %d, vbt: %d, spec: %d\n", final->field, cur.field, vbt.field, spec.field);\ + } while (0) + assign_final(t1_t3); + assign_final(t8); + assign_final(t9); + assign_final(t10); + assign_final(t11_t12); +#undef assign_final + +#define get_delay(field) (DIV_ROUND_UP(final->field, 10)) + intel_dp->panel_power_up_delay = get_delay(t1_t3); + intel_dp->backlight_on_delay = get_delay(t8); + intel_dp->backlight_off_delay = get_delay(t9); + intel_dp->panel_power_down_delay = get_delay(t10); + intel_dp->panel_power_cycle_delay = get_delay(t11_t12); +#undef get_delay + + PRINT_DEBUG(EFI_D_ERROR, "panel power up delay %d, power down delay %d, power cycle delay %d\n", + intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, + intel_dp->panel_power_cycle_delay); + + PRINT_DEBUG(EFI_D_ERROR, "backlight on delay %d, off delay %d\n", + intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); + + /* + * We override the HW backlight delays to 1 because we do manual waits + * on them. For T8, even BSpec recommends doing it. For T9, if we + * don't do this, we'll end up waiting for the backlight off delay + * twice: once when we do the manual sleep, and once when we disable + * the panel and wait for the PP_STATUS bit to become zero. + */ + final->t8 = 1; + final->t9 = 1; + + /* + * HW has only a 100msec granularity for t11_t12 so round it up + * accordingly. + */ + final->t11_t12 = roundup(final->t11_t12, 100 * 10); +} + +static void +intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp) +{ + //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u32 pp_on, pp_off, pp_div = 0; + int div = intel_dp->controller->rawclk_freq / 1000; + struct pps_registers regs; + // enum port port = dp_to_dig_port(intel_dp)->base.port; + const struct edp_power_seq *seq = &intel_dp->pps_delays; + + //lockdep_assert_held(&intel_dp->controller->pps_mutex); + + intel_pps_get_registers(intel_dp, ®s); + + // /* ALways false + // * On some VLV machines the BIOS can leave the VDD + // * enabled even on power sequencers which aren't + // * hooked up to any port. This would mess up the + // * power domain tracking the first time we pick + // * one of these power sequencers for use since + // * edp_panel_vdd_on() would notice that the VDD was + // * already on and therefore wouldn't grab the power + // * domain reference. Disable VDD first to avoid this. + // * This also avoids spuriously turning the VDD on as + // * soon as the new power sequencer gets initialized. + // */ + // if (force_disable_vdd) + // { + // u32 pp = ironlake_get_pp_control(intel_dp); + + // WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); + + // if (pp & EDP_FORCE_VDD) + // PRINT_DEBUG(EFI_D_ERROR,"VDD already on, disabling first\n"); + + // pp &= ~EDP_FORCE_VDD; + + // intel_dp->controller->write32(regs.pp_ctrl, pp); + // } + + pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | + (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); + pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | + (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); + /* Compute the divisor for the pp clock, simply match the Bspec + * formula. */ + // if (IS_GEN9_LP(intel_dp->controller) || HAS_PCH_CNP(intel_dp->controller) || + // HAS_PCH_ICP(intel_dp->controller)) + // { + // pp_div = intel_dp->controller->read32(regs.pp_ctrl); + // pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; + // pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) + // << BXT_POWER_CYCLE_DELAY_SHIFT); + // } + // else + { + pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; + pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) + << PANEL_POWER_CYCLE_DELAY_SHIFT); + } + + // /* Haswell doesn't have any port selection bits for the panel + // * power sequencer any more. */ + // if (IS_VALLEYVIEW(intel_dp->controller) || IS_CHERRYVIEW(intel_dp->controller)) + // { + // port_sel = PANEL_PORT_SELECT_VLV(port); + // } + // else if (HAS_PCH_IBX(intel_dp->controller) || HAS_PCH_CPT(intel_dp->controller)) + // { + // switch (port) + // { + // case PORT_A: + // port_sel = PANEL_PORT_SELECT_DPA; + // break; + // case PORT_C: + // port_sel = PANEL_PORT_SELECT_DPC; + // break; + // case PORT_D: + // port_sel = PANEL_PORT_SELECT_DPD; + // break; + // default: + // MISSING_CASE(port); + // break; + // } + // } + + // pp_on |= port_sel; + + intel_dp->controller->write32(regs.pp_on, pp_on); + intel_dp->controller->write32(regs.pp_off, pp_off); + // if (IS_GEN9_LP(intel_dp->controller) || HAS_PCH_CNP(intel_dp->controller) || + // HAS_PCH_ICP(intel_dp->controller)) + // intel_dp->controller->write32(regs.pp_ctrl, pp_div); + // else + intel_dp->controller->write32(regs.pp_div, pp_div); + + PRINT_DEBUG(EFI_D_ERROR, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", + intel_dp->controller->read32(regs.pp_on), + intel_dp->controller->read32(regs.pp_off), intel_dp->controller->read32(regs.pp_div)); +} + +void intel_dp_pps_init(i915_CONTROLLER *controller) +{ + //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + // if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + // vlv_initial_power_sequencer_setup(intel_dp); + // } else { + intel_dp_init_panel_power_sequencer(controller->intel_dp); + intel_dp_init_panel_power_sequencer_registers(controller->intel_dp); + //} +} + +EFI_STATUS SetupClockeDP(i915_CONTROLLER *controller) +{ + + UINT32 ctrl1; + UINT32 port = controller->OutputPath.Port; + + UINT8 id = controller->OutputPath.DPLL; + /* + * See comment in intel_dpll_hw_state to understand why we always use 0 + * as the DPLL id in this function. Basically, we put them in the first 6 bits then shift them into place for easier comparison + */ + ctrl1 = DPLL_CTRL1_OVERRIDE(id); //Enable Programming + ctrl1 |= DPLL_CTRL1_SSC(id); + // ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); //Set Mode to HDMI + + UINT32 val = controller->read32(DPLL_CTRL2); + + //val &= ~(DPLL_CTRL2_DDI_CLK_OFF(PORT_A) | + // DPLL_CTRL2_DDI_CLK_SEL_MASK(PORT_A)); + //val |= (DPLL_CTRL2_DDI_CLK_SEL(id, PORT_A) | + // DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_A)); + + val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port)); + val |= (DPLL_CTRL2_DDI_CLK_OFF(port)); + + controller->write32(DPLL_CTRL2, val); + controller->write32(LCPLL2_CTL, controller->read32(LCPLL2_CTL) & ~(LCPLL_PLL_ENABLE)); + controller->write32(LCPLL1_CTL, controller->read32(LCPLL1_CTL) & ~(LCPLL_PLL_ENABLE)); + val = controller->read32(DPLL_CTRL1); + for (UINT32 counter = 0;; counter++) + { + if (controller->read32(DPLL_STATUS) & DPLL_LOCK(id)) + { + PRINT_DEBUG(EFI_D_ERROR, "DPLL %d locked\n", id); + break; + } + if (counter > 500) + { + PRINT_DEBUG(EFI_D_ERROR, "DPLL %d not locked\n", id); + break; + } + gBS->Stall(10); + } + //it's clock id! + //how's port clock comptued? + UINT64 clock_khz = controller->OutputPath.LinkRate; + PRINT_DEBUG(EFI_D_ERROR, "Link Rate: %u\n", clock_khz); + UINT32 linkrate = DPLL_CTRL1_LINK_RATE_810; + if (clock_khz >> 1 >= 135000) + { + linkrate = DPLL_CTRL1_LINK_RATE_1350; + } + else if (clock_khz >> 1 >= 270000) + { + linkrate = DPLL_CTRL1_LINK_RATE_2700; + } + //hack: anything else hangs + // UINT32 id = DPLL_CTRL1_LINK_RATE_1350; + ctrl1 |= DPLL_CTRL1_LINK_RATE(linkrate, id); + + val &= ~(DPLL_CTRL1_HDMI_MODE(id) | + DPLL_CTRL1_SSC(id) | + DPLL_CTRL1_LINK_RATE_MASK(id)); + val |= ctrl1; + + //DPLL 1 + controller->write32(DPLL_CTRL1, val); + controller->read32(DPLL_CTRL1); + + //845 80400173 3a5 + PRINT_DEBUG(EFI_D_ERROR, "DPLL_CTRL1 = %08x\n", controller->read32(DPLL_CTRL1)); + PRINT_DEBUG(EFI_D_ERROR, "_DPLL1_CFGCR1 = %08x\n", controller->read32(_DPLL1_CFGCR1)); + PRINT_DEBUG(EFI_D_ERROR, "_DPLL1_CFGCR2 = %08x\n", controller->read32(_DPLL1_CFGCR2)); + + /* the enable bit is always bit 31 */ + controller->write32(LCPLL2_CTL, controller->read32(LCPLL2_CTL) | LCPLL_PLL_ENABLE); + controller->write32(LCPLL1_CTL, controller->read32(LCPLL1_CTL) | LCPLL_PLL_ENABLE); + + for (UINT32 counter = 0;; counter++) + { + if (controller->read32(DPLL_STATUS) & DPLL_LOCK(id)) + { + PRINT_DEBUG(EFI_D_ERROR, "DPLL %d locked\n", id); + break; + } + if (counter > 500) + { + PRINT_DEBUG(EFI_D_ERROR, "DPLL %d not locked\n", id); + break; + } + gBS->Stall(10); + } + + //intel_encoders_pre_enable(crtc, pipe_config, old_state); + //could be intel_ddi_pre_enable_hdmi + //intel_ddi_clk_select(encoder, crtc_state); + PRINT_DEBUG(EFI_D_ERROR, "port is %d\n", port); + { + UINT32 val = controller->read32(DPLL_CTRL2); + + //val &= ~(DPLL_CTRL2_DDI_CLK_OFF(PORT_A) | + // DPLL_CTRL2_DDI_CLK_SEL_MASK(PORT_A)); + //val |= (DPLL_CTRL2_DDI_CLK_SEL(id, PORT_A) | + // DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_A)); + + val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | + DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); + val |= (DPLL_CTRL2_DDI_CLK_SEL(id, port) | + DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); + + controller->write32(DPLL_CTRL2, val); + } + PRINT_DEBUG(EFI_D_ERROR, "DPLL_CTRL2 = %08x\n", controller->read32(DPLL_CTRL2)); + return EFI_SUCCESS; +} +struct ddi_buf_trans +{ + UINT32 trans1; /* balance leg enable, de-emph level */ + UINT32 trans2; /* vref sel, vswing */ + UINT8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ +}; +/* Skylake H and S */ +static const struct ddi_buf_trans skl_ddi_translations_dp[] = { + {0x00002016, 0x000000A0, 0x0}, + {0x00005012, 0x0000009B, 0x0}, + {0x00007011, 0x00000088, 0x0}, + {0x80009010, 0x000000C0, 0x1}, + {0x00002016, 0x0000009B, 0x0}, + {0x00005012, 0x00000088, 0x0}, + {0x80007011, 0x000000C0, 0x1}, + {0x00002016, 0x000000DF, 0x0}, + {0x80005012, 0x000000C0, 0x1}, +}; + +/* Skylake U */ +static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { + {0x0000201B, 0x000000A2, 0x0}, + {0x00005012, 0x00000088, 0x0}, + {0x80007011, 0x000000CD, 0x1}, + {0x80009010, 0x000000C0, 0x1}, + {0x0000201B, 0x0000009D, 0x0}, + {0x80005012, 0x000000C0, 0x1}, + {0x80007011, 0x000000C0, 0x1}, + {0x00002016, 0x00000088, 0x0}, + {0x80005012, 0x000000C0, 0x1}, +}; + +/* Skylake Y */ +static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { + {0x00000018, 0x000000A2, 0x0}, + {0x00005012, 0x00000088, 0x0}, + {0x80007011, 0x000000CD, 0x3}, + {0x80009010, 0x000000C0, 0x3}, + {0x00000018, 0x0000009D, 0x0}, + {0x80005012, 0x000000C0, 0x3}, + {0x80007011, 0x000000C0, 0x3}, + {0x00000018, 0x00000088, 0x0}, + {0x80005012, 0x000000C0, 0x3}, +}; +#define IS_SKL_ULX(cont) (0) +#define IS_SKL_ULT(cont) (1) +static const struct ddi_buf_trans * +skl_get_buf_trans_dp(i915_CONTROLLER *controller, int *n_entries) +{ + if (IS_SKL_ULX(controller)) + { + *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); + return skl_y_ddi_translations_dp; + } + else if (IS_SKL_ULT(controller)) + { + *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); + return skl_u_ddi_translations_dp; + } + else + { + *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); + return skl_ddi_translations_dp; + } +} + +/* Display Port */ +#define DP_A _MMIO(0x64000) /* eDP */ +#define DP_B _MMIO(0x64100) +#define DP_C _MMIO(0x64200) +#define DP_D _MMIO(0x64300) + +EFI_STATUS SetupDDIBufferDP(i915_CONTROLLER *controller) +{ + const struct ddi_buf_trans *ddi_translations; + + int i, n_entries; + + ddi_translations = skl_get_buf_trans_dp(controller, + &n_entries); + /* If we're boosting the current, set bit 31 of trans1 */ + // if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) + // iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; + UINT32 port = controller->OutputPath.Port; + for (i = 0; i < n_entries; i++) + { + controller->write32(DDI_BUF_TRANS_LO(port, i), + ddi_translations[i].trans1); + controller->write32(DDI_BUF_TRANS_HI(port, i), + ddi_translations[i].trans2); + } + return EFI_SUCCESS; +} +/** + * struct drm_dp_aux_msg - DisplayPort AUX channel transaction + * @address: address of the (first) register to access + * @request: contains the type of transaction (see DP_AUX_* macros) + * @reply: upon completion, contains the reply type of the transaction + * @buffer: pointer to a transmission or reception buffer + * @size: size of @buffer + */ +struct drm_dp_aux_msg +{ + unsigned int address; + UINT8 request; + UINT8 reply; + void *buffer; + UINT32 size; +}; + +struct cec_adapter; +struct edid; +struct drm_connector; + +/** + * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX + * @lock: mutex protecting this struct + * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. + * @connector: the connector this CEC adapter is associated with + * @unregister_work: unregister the CEC adapter + */ +/* struct drm_dp_aux_cec { + struct mutex lock; + struct cec_adapter *adap; + struct drm_connector *connector; + struct delayed_work unregister_work; +}; */ + +/** + * struct drm_dp_aux - DisplayPort AUX channel + * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter + * @ddc: I2C adapter that can be used for I2C-over-AUX communication + * @dev: pointer to struct device that is the parent for this AUX channel + * @crtc: backpointer to the crtc that is currently using this AUX channel + * @hw_mutex: internal mutex used for locking transfers + * @crc_work: worker that captures CRCs for each frame + * @crc_count: counter of captured frame CRCs + * @transfer: transfers a message representing a single AUX transaction + * + * The .dev field should be set to a pointer to the device that implements + * the AUX channel. + * + * The .name field may be used to specify the name of the I2C adapter. If set to + * NULL, dev_name() of .dev will be used. + * + * Drivers provide a hardware-specific implementation of how transactions + * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg + * structure describing the transaction is passed into this function. Upon + * success, the implementation should return the number of payload bytes + * that were transferred, or a negative error-code on failure. Helpers + * propagate errors from the .transfer() function, with the exception of + * the -EBUSY error, which causes a transaction to be retried. On a short, + * helpers will return -EPROTO to make it simpler to check for failure. + * + * An AUX channel can also be used to transport I2C messages to a sink. A + * typical application of that is to access an EDID that's present in the + * sink device. The .transfer() function can also be used to execute such + * transactions. The drm_dp_aux_register() function registers an I2C + * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers + * should call drm_dp_aux_unregister() to remove the I2C adapter. + * The I2C adapter uses long transfers by default; if a partial response is + * received, the adapter will drop down to the size given by the partial + * response for this transaction only. + * + * Note that the aux helper code assumes that the .transfer() function + * only modifies the reply field of the drm_dp_aux_msg structure. The + * retry logic and i2c helpers assume this is the case. + */ +#define BARE_ADDRESS_SIZE 3 +#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) + +static void +intel_dp_aux_header(UINT8 txbuf[HEADER_SIZE], + const struct drm_dp_aux_msg *msg) +{ + txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); + txbuf[1] = (msg->address >> 8) & 0xff; + txbuf[2] = msg->address & 0xff; + txbuf[3] = msg->size - 1; +} +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define ETIMEDOUT 35 +static UINT32 +intel_dp_aux_wait_done(i915_CONTROLLER *controller) +{ + UINT32 pin = controller->OutputPath.AuxCh; + UINT64 ch_ctl = _DPA_AUX_CH_CTL + (pin << 8); + const unsigned int timeout_ms = 10; + UINT32 status; + BOOLEAN done; + +#define C (((status = controller->read32(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) + gBS->Stall(10 * 1000); + done = C; + /* done = wait_event_timeout(i915->gmbus_wait_queue, C, + msecs_to_jiffies_timeout(timeout_ms)); */ + + /* just trace the final value */ + //trace_i915_reg_rw(FALSE, ch_ctl, status, sizeof(status), TRUE); + + if (!done) + PRINT_DEBUG(EFI_D_ERROR, + "%s: did not complete or timeout within %ums (status 0x%08x)\n", + pin, timeout_ms, status); +#undef C + + return status; +} +static UINT32 skl_get_aux_clock_divider(int index) +{ + /* + * SKL doesn't need us to program the AUX clock divider (Hardware will + * derive the clock from CDCLK automatically). We still implement the + * get_aux_clock_divider vfunc to plug-in into the existing code. + */ + return index ? 0 : 1; +} +UINT32 intel_dp_pack_aux(const UINT8 *src, int src_bytes) +{ + int i; + UINT32 v = 0; + + if (src_bytes > 4) + src_bytes = 4; + for (i = 0; i < src_bytes; i++) + v |= ((UINT32)src[i]) << ((3 - i) * 8); + return v; +} + +static void intel_dp_unpack_aux(UINT32 src, UINT8 *dst, int dst_bytes) +{ + int i; + if (dst_bytes > 4) + dst_bytes = 4; + for (i = 0; i < dst_bytes; i++) + dst[i] = src >> ((3 - i) * 8); +} +static UINT32 skl_get_aux_send_ctl( + int send_bytes, + UINT32 unused) +{ + /* struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *i915 = + to_i915(intel_dig_port->base.base.dev); + enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); */ + UINT32 ret; + + ret = DP_AUX_CH_CTL_SEND_BUSY | + DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_INTERRUPT | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_TIME_OUT_MAX | + DP_AUX_CH_CTL_RECEIVE_ERROR | + (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); + + /* if (intel_phy_is_tc(i915, phy) && + intel_dig_port->tc_mode == TC_PORT_TBT_ALT) + ret |= DP_AUX_CH_CTL_TBT_IO; */ + + return ret; +} +static EFI_STATUS intel_wait_for_register(i915_CONTROLLER *controller, + UINT64 reg, + u32 mask, + u32 value, + unsigned int timeout_ms) +{ + for (int i = 0; i < timeout_ms; i++) + { + if ((controller->read32(reg) & mask) == value) + { + return EFI_SUCCESS; + } + gBS->Stall(1000); + } + return EFI_TIMEOUT; +} +#define PP_READY (1 << 30) +#define PP_SEQUENCE_NONE (0 << 28) +#define PP_SEQUENCE_POWER_UP (1 << 28) +#define PP_SEQUENCE_POWER_DOWN (2 << 28) +#define PP_SEQUENCE_MASK (3 << 28) +#define PP_SEQUENCE_SHIFT 28 +#define PP_CYCLE_DELAY_ACTIVE (1 << 27) +#define PP_SEQUENCE_STATE_MASK 0x0000000f +#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) +#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) +#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) +#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) +#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) +#define PP_SEQUENCE_STATE_RESET (0xf << 0) +#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) +#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) + +#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) +#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) + +#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) +#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) +static void +wait_panel_status(struct intel_dp *intel_dp, + u32 mask, + u32 value) +{ + // struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + // i915_reg_t pp_stat_reg, pp_ctrl_reg; + + // lockdep_assert_held(&dev_priv->pps_mutex); + + // intel_pps_verify_state(intel_dp); + + // pp_stat_reg = _pp_stat_reg(intel_dp); + // pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + + PRINT_DEBUG(EFI_D_ERROR, "mask %08x value %08x status %08x control %08x\n", + mask, value, + intel_dp->controller->read32(PP_STATUS), + intel_dp->controller->read32(PP_CONTROL)); + + if (intel_wait_for_register(intel_dp->controller, + PP_STATUS, mask, value, + 5000)) + PRINT_DEBUG(EFI_D_ERROR, "Panel status timeout: status %08x control %08x\n", + intel_dp->controller->read32(PP_STATUS), + intel_dp->controller->read32(PP_CONTROL)); + + PRINT_DEBUG(EFI_D_ERROR, "Wait complete\n"); +} + +static void wait_panel_on(struct intel_dp *intel_dp) +{ + PRINT_DEBUG(EFI_D_ERROR, "Wait for panel power on\n"); + wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); +} + +// static void wait_panel_off(struct intel_dp *intel_dp) +// { +// PRINT_DEBUG(EFI_D_ERROR, "Wait for panel power off time\n"); +// wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); +// } + +static void wait_panel_power_cycle(struct intel_dp *intel_dp) +{ + // ktime_t panel_power_on_time; + // s64 panel_power_off_duration; + + PRINT_DEBUG(EFI_D_ERROR, "Wait for panel power cycle\n"); + + // /* take the difference of currrent time and panel power off time + // * and then make panel wait for t11_t12 if needed. */ + // panel_power_on_time = ktime_get_boottime(); + // panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); + + // /* When we disable the VDD override bit last we have to do the manual + // * wait. */ + // if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) + // wait_remaining_ms_from_jiffies(jiffies, + // intel_dp->panel_power_cycle_delay - panel_power_off_duration); + PRINT_DEBUG(EFI_D_ERROR, "Panel Power Cycle Delay: %d\n", intel_dp->panel_power_cycle_delay); + gBS->Stall(intel_dp->panel_power_cycle_delay); + wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); +} + +// static void wait_backlight_on(struct intel_dp *intel_dp) +// { +// gBS->Stall(intel_dp->backlight_on_delay); + +// // wait_remaining_ms_from_jiffies(intel_dp->last_power_on, +// // intel_dp->backlight_on_delay); +// } + +// static void edp_wait_backlight_off(struct intel_dp *intel_dp) +// { +// gBS->Stall(intel_dp->backlight_off_delay); + +// // wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, +// // intel_dp->backlight_off_delay); +// } +static bool edp_have_panel_power(i915_CONTROLLER *controller) +{ + // struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + // lockdep_assert_held(&dev_priv->pps_mutex); + + // if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + // intel_dp->pps_pipe == INVALID_PIPE) + // return false; + + return (controller->read32(PP_STATUS) & PP_ON) != 0; +} + +// static bool edp_have_panel_vdd(i915_CONTROLLER *controller) +// { +// // struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + +// // lockdep_assert_held(&dev_priv->pps_mutex); + +// // if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && +// // intel_dp->pps_pipe == INVALID_PIPE) +// // return false; +// return controller->read32(PP_CONTROL) & EDP_FORCE_VDD; +// } + +/* + * Must be paired with edp_panel_vdd_off(). + * Must hold pps_mutex around the whole on/off sequence. + * Can be nested with intel_edp_panel_vdd_{on,off}() calls. + */ +static bool edp_panel_vdd_on(struct intel_dp *intel_dp) +{ + //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + // struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + u32 pp; + //i915_reg_t pp_stat_reg, pp_ctrl_reg; + //bool need_to_disable = !intel_dp->want_panel_vdd; + + // lockdep_assert_held(&dev_priv->pps_mutex); + + // if (!intel_dp_is_edp(intel_dp)) + // return false; + + // cancel_delayed_work(&intel_dp->panel_vdd_work); + // intel_dp->want_panel_vdd = true; + + // if (edp_have_panel_vdd(intel_dp)) + // return need_to_disable; + + // intel_display_power_get(dev_priv, + // intel_aux_power_domain(intel_dig_port)); + + PRINT_DEBUG(EFI_D_ERROR, "Turning eDP VDD on\n"); + + if (!edp_have_panel_power(intel_dp->controller)) + wait_panel_power_cycle(intel_dp); + + pp = ironlake_get_pp_control(intel_dp->controller); + pp |= EDP_FORCE_VDD; + + // pp_stat_reg = _pp_stat_reg(intel_dp); + // pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + intel_dp->controller->write32(PP_CONTROL, pp); + //intel_dp->controller->write32(pp_ctrl_reg, pp); + //POSTING_READ(pp_ctrl_reg); + PRINT_DEBUG(EFI_D_ERROR, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", + intel_dp->controller->read32(PP_STATUS), intel_dp->controller->read32(PP_CONTROL)); + + /* + * If the panel wasn't on, delay before accessing aux channel + */ + if (!edp_have_panel_power(intel_dp->controller)) + { + PRINT_DEBUG(EFI_D_ERROR, "eDP port panel power wasn't enabled\n"); + gBS->Stall(1000 * intel_dp->panel_power_up_delay); + } + + return true; +} +static void edp_panel_on(struct intel_dp *intel_dp) +{ + // struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u32 pp; + // i915_reg_t pp_ctrl_reg; + + PRINT_DEBUG(EFI_D_ERROR, "Turn eDP port panel power on\n"); + + if (edp_have_panel_power(intel_dp->controller)) + { + + PRINT_DEBUG(EFI_D_ERROR, "eDP port panel power already on\n"); + return; + } + wait_panel_power_cycle(intel_dp); + + //pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + pp = ironlake_get_pp_control(intel_dp->controller); + // if (IS_GEN5(dev_priv)) + // { + // /* ILK workaround: disable reset around power sequence */ + // pp &= ~PANEL_POWER_RESET; + // intel_dp->controller->write32(pp_ctrl_reg, pp); + // POSTING_READ(pp_ctrl_reg); + // } + + pp |= PANEL_POWER_ON; + // if (!IS_GEN5(dev_priv)) + pp |= PANEL_POWER_RESET; + intel_dp->controller->write32(PP_CONTROL, pp); + + // intel_dp->controller->write32(pp_ctrl_reg, pp); + // POSTING_READ(pp_ctrl_reg); + + wait_panel_on(intel_dp); + //intel_dp->last_power_on = jiffies; + + // if (IS_GEN5(dev_priv)) + // { + // pp |= PANEL_POWER_RESET; /* restore panel reset bit */ + // intel_dp->controller->write32(pp_ctrl_reg, pp); + // POSTING_READ(pp_ctrl_reg); + // } +} +static int +intel_dp_aux_xfer(i915_CONTROLLER *controller, + const UINT8 *send, int send_bytes, + UINT8 *recv, int recv_size, + UINT32 aux_send_ctl_flags) +{ + struct intel_dp *intel_dp = controller->intel_dp; + // struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + // struct drm_i915_private *i915 = + // to_i915(intel_dig_port->base.base.dev); + //struct intel_uncore *uncore = &i915->uncore; + // enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); + // BOOLEAN is_tc_port = intel_phy_is_tc(i915, phy); + UINT64 ch_ctl, ch_data[5]; + UINT32 aux_clock_divider; + //enum intel_display_power_domain aux_domain; + //intel_wakeref_t aux_wakeref; + // intel_wakeref_t pps_wakeref; + int i, ret, recv_bytes; + int try, clock = 0; + UINT32 val; + UINT32 status; + // BOOLEAN vdd; + UINT32 pin = controller->OutputPath.AuxCh; + ch_ctl = _DPA_AUX_CH_CTL + (pin << 8); +#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) + + for (i = 0; i < ARRAY_SIZE(ch_data); i++) + ch_data[i] = (_DPA_AUX_CH_DATA1 + pin * (0x64114 - _DPA_AUX_CH_DATA1)) + (i)*4; + + /* if (is_tc_port) + intel_tc_port_lock(intel_dig_port); + + aux_domain = intel_aux_power_domain(intel_dig_port); + + aux_wakeref = intel_display_power_get(i915, aux_domain); + pps_wakeref = pps_lock(intel_dp); */ + + /* + * We will be called with VDD already enabled for dpcd/edid/oui reads. + * In such cases we want to leave VDD enabled and it's up to upper layers + * to turn it off. But for eg. i2c-dev access we need to turn it on/off + * ourselves. + */ + //controller->write32(PP_CONTROL, 15); + //vdd = edp_panel_vdd_on(intel_dp); + edp_panel_vdd_on(intel_dp); + + /* dp aux is extremely sensitive to irq latency, hence request the + * lowest possible wakeup latency and so prevent the cpu from going into + * deep sleep states. + */ + /* cpu_latency_qos_update_request(&i915->pm_qos, 0); + + intel_dp_check_edp(intel_dp); */ + + /* Try to wait for any previous AUX channel activity */ + for (try = 0; try < 3; try++) + { + status = controller->read32(ch_ctl); + if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) + break; + gBS->Stall(1000); + } + /* just trace the final value */ + //trace_i915_reg_rw(FALSE, ch_ctl, status, sizeof(status), TRUE); + + if (try == 3) + { + /* const UINT32 status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8)); */ + + /* if (status != intel_dp->aux_busy_last_status) { + drm_WARN(&i915->drm, 1, + "%s: not started (status 0x%08x)\n", + pin, status); + intel_dp->aux_busy_last_status = status; + } */ + + ret = -EBUSY; + goto out; + } + + /* Only 5 data registers! */ + if (send_bytes > 20 || recv_size > 20) + { + ret = -E2BIG; + goto out; + } + + while ((aux_clock_divider = skl_get_aux_clock_divider(clock++))) + { + UINT32 send_ctl = skl_get_aux_send_ctl( + send_bytes, + aux_clock_divider); + + send_ctl |= aux_send_ctl_flags; + + /* Must try at least 3 times according to DP spec */ + for (try = 0; try < 5; try++) + { + /* Load the send data into the aux channel data registers */ + for (i = 0; i < send_bytes; i += 4) + controller->write32( + ch_data[i >> 2], + intel_dp_pack_aux(send + i, + send_bytes - i)); + + /* Send the command and wait for it to complete */ + controller->write32(ch_ctl, send_ctl); + + status = intel_dp_aux_wait_done(controller); + + /* Clear done status and any errors */ + controller->write32( + ch_ctl, + status | + DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR); + + /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 + * 400us delay required for errors and timeouts + * Timeout errors from the HW already meet this + * requirement so skip to next iteration + */ + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) + continue; + + if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) + { + gBS->Stall(500); + continue; + } + if (status & DP_AUX_CH_CTL_DONE) + goto done; + } + } + + if ((status & DP_AUX_CH_CTL_DONE) == 0) + { + PRINT_DEBUG(EFI_D_ERROR, "%s: not done (status 0x%08x)\n", + pin, status); + ret = -EBUSY; + goto out; + } + +done: + /* Check for timeout or receive error. + * Timeouts occur when the sink is not connected + */ + if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) + { + PRINT_DEBUG(EFI_D_ERROR, "%s: receive error (status 0x%08x)\n", + pin, status); + ret = -EIO; + goto out; + } + + /* Timeouts occur when the device isn't connected, so they're + * "normal" -- don't fill the kernel log with these */ + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) + { + PRINT_DEBUG(EFI_D_ERROR, "%s: timeout (status 0x%08x)\n", + pin, status); + ret = -ETIMEDOUT; + goto out; + } + + /* Unload any bytes sent back from the other side */ + recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> + DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); + + /* + * By BSpec: "Message sizes of 0 or >20 are not allowed." + * We have no idea of what happened so we return -EBUSY so + * drm layer takes care for the necessary retries. + */ + if (recv_bytes == 0 || recv_bytes > 20) + { + PRINT_DEBUG(EFI_D_ERROR, + "%s: Forbidden recv_bytes = %d on aux transaction\n", + pin, recv_bytes); + ret = -EBUSY; + goto out; + } + + if (recv_bytes > recv_size) + recv_bytes = recv_size; + + for (i = 0; i < recv_bytes; i += 4) + intel_dp_unpack_aux(controller->read32(ch_data[i >> 2]), + recv + i, recv_bytes - i); + + ret = recv_bytes; +out: + + val = controller->read32(PP_CONTROL); + val &= ~(1 << 3); + controller->write32(PP_CONTROL, val); + // pps_unlock(intel_dp, pps_wakeref); + // intel_display_power_put_async(i915, aux_domain, aux_wakeref); + + // if (is_tc_port) + // intel_tc_port_unlock(intel_dig_port); + + return ret; +} + +static INT32 intel_dp_aux_transfer(i915_CONTROLLER *controller, struct drm_dp_aux_msg *msg) +{ + + //struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); + UINT8 txbuf[20], rxbuf[20]; + UINTN txsize, rxsize; + int ret; + + intel_dp_aux_header(txbuf, msg); + + switch (msg->request & ~DP_AUX_I2C_MOT) + { + case DP_AUX_NATIVE_WRITE: + case DP_AUX_I2C_WRITE: + case DP_AUX_I2C_WRITE_STATUS_UPDATE: + txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; + rxsize = 2; /* 0 or 1 data bytes */ + + if (txsize > 20) + return -E2BIG; + + //WARN_ON(!msg->buffer != !msg->size); + + if (msg->buffer) + memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); + + ret = intel_dp_aux_xfer(controller, txbuf, txsize, + rxbuf, rxsize, 0); + if (ret > 0) + { + msg->reply = rxbuf[0] >> 4; + + if (ret > 1) + { + /* Number of bytes written in a short write. */ + ret = clamp_t(int, rxbuf[1], 0, msg->size); + } + else + { + /* Return payload size. */ + ret = msg->size; + } + } + break; + + case DP_AUX_NATIVE_READ: + case DP_AUX_I2C_READ: + txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; + rxsize = msg->size + 1; + + if ((rxsize > 20)) + return -E2BIG; + + ret = intel_dp_aux_xfer(controller, txbuf, txsize, + rxbuf, rxsize, 0); + if (ret > 0) + { + msg->reply = rxbuf[0] >> 4; + /* + * Assume happy day, and copy the data. The caller is + * expected to check msg->reply before touching it. + * + * Return payload size. + */ + ret--; + memcpy(msg->buffer, rxbuf + 1, ret); + } + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + +/** + * DOC: dp helpers + * + * The DisplayPort AUX channel is an abstraction to allow generic, driver- + * independent access to AUX functionality. Drivers can take advantage of + * this by filling in the fields of the drm_dp_aux structure. + * + * Transactions are described using a hardware-independent drm_dp_aux_msg + * structure, which is passed into a driver's .transfer() implementation. + * Both native and I2C-over-AUX transactions are supported. + */ +#define AUX_RETRY_INTERVAL 500 /* us */ + +static RETURN_STATUS drm_dp_dpcd_access(UINT8 request, + unsigned int offset, void *buffer, UINT32 size, i915_CONTROLLER *controller) +{ + struct drm_dp_aux_msg msg; + unsigned int retry, native_reply; + RETURN_STATUS err = 0, ret = 0; + + // memset(&msg, 0, sizeof(msg)); //Not Defined + msg.address = offset; + msg.request = request; + msg.buffer = buffer; + msg.size = size; + + /* + * The specification doesn't give any recommendation on how often to + * retry native transactions. We used to retry 7 times like for + * aux i2c transactions but real world devices this wasn't + * sufficient, bump to 32 which makes Dell 4k monitors happier. + */ + for (retry = 0; retry < 32; retry++) + { + if (ret != 0 && ret != -RETURN_TIMEOUT) + { + gBS->Stall(AUX_RETRY_INTERVAL); + } + + ret = intel_dp_aux_transfer(controller, &msg); + if (ret >= 0) + { + native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; + if (native_reply == DP_AUX_NATIVE_REPLY_ACK) + { + if (ret == size) + goto unlock; + + ret = -RETURN_PROTOCOL_ERROR; + } + else + ret = -RETURN_NOT_FOUND; + } + + /* + * We want the error we return to be the error we received on + * the first transaction, since we may get a different error the + * next time we retry + */ + if (!err) + err = ret; + } + + PRINT_DEBUG(EFI_D_ERROR, "Too many retries, giving up. First error: %d\n", err); + ret = err; + +unlock: + return ret; +} +/** + * drm_dp_dpcd_read() - read a series of bytes from the DPCD + * @aux: DisplayPort AUX channel (SST or MST) + * @offset: address of the (first) register to read + * @buffer: buffer to store the register values + * @size: number of bytes in @buffer + * + * Returns the number of bytes transferred on success, or a negative error + * code on failure. -EIO is returned if the request was NAKed by the sink or + * if the retry count was exceeded. If not all bytes were transferred, this + * function returns -EPROTO. Errors from the underlying AUX channel transfer + * function, with the exception of -EBUSY (which causes the transaction to + * be retried), are propagated to the caller. + */ +INT32 drm_dp_dpcd_read(unsigned int offset, + void *buffer, UINT32 size, i915_CONTROLLER *controller) +{ + int ret; + + /* + * HP ZR24w corrupts the first DPCD access after entering power save + * mode. Eg. on a read, the entire buffer will be filled with the same + * byte. Do a throw away read to avoid corrupting anything we care + * about. Afterwards things will work correctly until the monitor + * gets woken up and subsequently re-enters power save mode. + * + * The user pressing any button on the monitor is enough to wake it + * up, so there is no particularly good place to do the workaround. + * We just have to do it before any DPCD access and hope that the + * monitor doesn't power down exactly after the throw away read. + */ + //if (!aux->is_remote) { + ret = drm_dp_dpcd_access(DP_AUX_NATIVE_READ, DP_DPCD_REV, + buffer, 1, controller); + if (ret != 1) + goto out; + // } + + // if (aux->is_remote) + // ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); + // else + ret = drm_dp_dpcd_access(DP_AUX_NATIVE_READ, offset, + buffer, size, controller); + +out: + return ret; +} +BOOLEAN +intel_dp_get_link_status(UINT8 link_status[DP_LINK_STATUS_SIZE], i915_CONTROLLER *controller) +{ + return drm_dp_dpcd_read(DP_LANE0_1_STATUS, link_status, + DP_LINK_STATUS_SIZE, controller) == DP_LINK_STATUS_SIZE; +} +/* Helpers for DP link training */ +static UINT8 dp_link_status(const UINT8 link_status[DP_LINK_STATUS_SIZE], int r) +{ + return link_status[r - DP_LANE0_1_STATUS]; +} +static UINT8 dp_get_lane_status(const UINT8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_LANE0_1_STATUS + (lane >> 1); + int s = (lane & 1) * 4; + UINT8 l = dp_link_status(link_status, i); + return (l >> s) & 0xf; +} +BOOLEAN drm_dp_clock_recovery_ok(const UINT8 link_status[DP_LINK_STATUS_SIZE], + int lane_count) +{ + int lane; + UINT8 lane_status; + + for (lane = 0; lane < lane_count; lane++) + { + lane_status = dp_get_lane_status(link_status, lane); + if ((lane_status & DP_LANE_CR_DONE) == 0) + return FALSE; + } + return TRUE; +} + +UINT8 drm_dp_get_adjust_request_voltage(const UINT8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); + UINT8 l = dp_link_status(link_status, i); + + return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; +} + +UINT8 drm_dp_get_adjust_request_pre_emphasis(const UINT8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); + UINT8 l = dp_link_status(link_status, i); + + return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; +} +/* These are source-specific values. */ +UINT8 +intel_dp_voltage_max() +{ + /* struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + enum port port = encoder->port; */ + + /* if (HAS_DDI(dev_priv)) + return intel_ddi_dp_voltage_max(encoder); + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; + else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) + return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; + else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) + return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; + else */ + return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; +} + +UINT8 +intel_dp_pre_emphasis_max(UINT8 voltage_swing) +{ + /* struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + enum port port = encoder->port; */ + + /* if (HAS_DDI(dev_priv)) { + return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing); + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: + return DP_TRAIN_PRE_EMPH_LEVEL_3; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: + return DP_TRAIN_PRE_EMPH_LEVEL_2; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: + return DP_TRAIN_PRE_EMPH_LEVEL_1; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: + default: + return DP_TRAIN_PRE_EMPH_LEVEL_0; + } + } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: + return DP_TRAIN_PRE_EMPH_LEVEL_2; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: + return DP_TRAIN_PRE_EMPH_LEVEL_1; + default: + return DP_TRAIN_PRE_EMPH_LEVEL_0; + } + } else { */ + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) + { + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: + return DP_TRAIN_PRE_EMPH_LEVEL_2; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: + return DP_TRAIN_PRE_EMPH_LEVEL_2; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: + return DP_TRAIN_PRE_EMPH_LEVEL_1; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: + default: + return DP_TRAIN_PRE_EMPH_LEVEL_0; + } + //} +} + +void intel_dp_get_adjust_train(struct intel_dp *intel_dp, + const UINT8 link_status[DP_LINK_STATUS_SIZE]) +{ + UINT8 v = 0; + UINT8 p = 0; + int lane; + UINT8 voltage_max; + UINT8 preemph_max; + + for (lane = 0; lane < intel_dp->lane_count; lane++) + { + UINT8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); + UINT8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); + PRINT_DEBUG(EFI_D_ERROR, "this_v:%u v:%u this_p:%u p:%u \n", this_v, v, this_p, p); + if (this_v > v) + v = this_v; + if (this_p > p) + p = this_p; + } + + voltage_max = intel_dp_voltage_max(); + if (v >= voltage_max) + v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; + + preemph_max = intel_dp_pre_emphasis_max(v); + if (p >= preemph_max) + p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; + + PRINT_DEBUG(EFI_D_ERROR, "v:%u p:%u \n", v, p); + + UINT8 val = intel_dp->train_set[0]; + if (val < 8) + { + val++; + } + for (lane = 0; lane < 4; lane++) + { + intel_dp->train_set[lane] = v | p; + PRINT_DEBUG(EFI_D_ERROR, "TrainSet[%u]: %u \n", lane, intel_dp->train_set[lane]); + } +} +/** + * drm_dp_dpcd_write() - write a series of bytes to the DPCD + * @aux: DisplayPort AUX channel (SST or MST) + * @offset: address of the (first) register to write + * @buffer: buffer containing the values to write + * @size: number of bytes in @buffer + * + * Returns the number of bytes transferred on success, or a negative error + * code on failure. -EIO is returned if the request was NAKed by the sink or + * if the retry count was exceeded. If not all bytes were transferred, this + * function returns -EPROTO. Errors from the underlying AUX channel transfer + * function, with the exception of -EBUSY (which causes the transaction to + * be retried), are propagated to the caller. + */ +INT32 drm_dp_dpcd_write(unsigned int offset, + void *buffer, UINT32 size, i915_CONTROLLER *controller) +{ + int ret; + + //if (aux->is_remote) + // ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); + //else + ret = drm_dp_dpcd_access(DP_AUX_NATIVE_WRITE, offset, + buffer, size, controller); + + return ret; +} +#define DP_VOLTAGE_0_4 (0 << 25) +#define DP_VOLTAGE_0_6 (1 << 25) +#define DP_VOLTAGE_0_8 (2 << 25) +#define DP_VOLTAGE_1_2 (3 << 25) +#define DP_VOLTAGE_MASK (7 << 25) +#define DP_VOLTAGE_SHIFT 25 + +/* Signal pre-emphasis levels, like voltages, the other end tells us what + * they want + */ +#define DP_PRE_EMPHASIS_0 (0 << 22) +#define DP_PRE_EMPHASIS_3_5 (1 << 22) +#define DP_PRE_EMPHASIS_6 (2 << 22) +#define DP_PRE_EMPHASIS_9_5 (3 << 22) +#define DP_PRE_EMPHASIS_MASK (7 << 22) +#define DP_PRE_EMPHASIS_SHIFT 22 +static UINT32 g4x_signal_levels(UINT8 train_set) +{ + UINT32 signal_levels = 0; + + switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) + { + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: + default: + signal_levels |= DP_VOLTAGE_0_4; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: + signal_levels |= DP_VOLTAGE_0_6; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: + signal_levels |= DP_VOLTAGE_0_8; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: + signal_levels |= DP_VOLTAGE_1_2; + break; + } + switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) + { + case DP_TRAIN_PRE_EMPH_LEVEL_0: + default: + signal_levels |= DP_PRE_EMPHASIS_0; + break; + case DP_TRAIN_PRE_EMPH_LEVEL_1: + signal_levels |= DP_PRE_EMPHASIS_3_5; + break; + case DP_TRAIN_PRE_EMPH_LEVEL_2: + signal_levels |= DP_PRE_EMPHASIS_6; + break; + case DP_TRAIN_PRE_EMPH_LEVEL_3: + signal_levels |= DP_PRE_EMPHASIS_9_5; + break; + } + return signal_levels; +} +#define DP_PORT_EN (1 << 31) + +static void +g4x_set_signal_levels(struct intel_dp *intel_dp) +{ + //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + UINT8 train_set = intel_dp->train_set[0]; + UINT32 signal_levels; + + signal_levels = g4x_signal_levels(train_set); + + PRINT_DEBUG(EFI_D_ERROR, "Using signal levels %08x\n", + signal_levels); + PRINT_DEBUG(EFI_D_ERROR, "Using vswing level %d%a, pre-emphasis level %d%a\n", + train_set & DP_TRAIN_VOLTAGE_SWING_MASK, + train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT, + train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? " (max)" : ""); + UINT32 DP = intel_dp->controller->read32(DDI_BUF_CTL(intel_dp->controller->OutputPath.Port)); + DP |= DP_PORT_EN; + DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); + DP |= signal_levels; + + intel_dp->controller->write32(DDI_BUF_CTL(intel_dp->controller->OutputPath.Port), DP); + //intel_de_posting_read(dev_priv, intel_dp->output_reg); +} +static void intel_dp_set_signal_levels(struct intel_dp *intel_dp) +{ + + //Write to Appropraite DDI_BUF_CTL + g4x_set_signal_levels(intel_dp); +} + +static BOOLEAN +intel_dp_update_link_train(struct intel_dp *intel_dp) +{ + int ret; + + intel_dp_set_signal_levels(intel_dp); + + ret = drm_dp_dpcd_write(DP_TRAINING_LANE0_SET, + intel_dp->train_set, intel_dp->lane_count, intel_dp->controller); + + return ret == intel_dp->lane_count; +} +static inline UINT8 +drm_dp_training_pattern_mask() +{ + //return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : + // DP_TRAINING_PATTERN_MASK; + return DP_TRAINING_PATTERN_MASK; +} +/* CPT Link training mode */ +#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) +#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) +#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) +#define DP_LINK_TRAIN_OFF_CPT (3 << 8) +#define DP_LINK_TRAIN_MASK_CPT (7 << 8) +#define DP_LINK_TRAIN_SHIFT_CPT 8 +static void +g4x_set_link_train(struct intel_dp *intel_dp, + UINT8 dp_train_pat) +{ + UINT32 DP = intel_dp->controller->read32(DP_TP_CTL(intel_dp->controller->OutputPath.Port)); + + DP &= ~DP_LINK_TRAIN_MASK_CPT; + + switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) + { + case DP_TRAINING_PATTERN_DISABLE: + DP |= DP_LINK_TRAIN_OFF_CPT; + break; + case DP_TRAINING_PATTERN_1: + DP |= DP_LINK_TRAIN_PAT_1_CPT; + break; + case DP_TRAINING_PATTERN_2: + DP |= DP_LINK_TRAIN_PAT_2_CPT; + break; + case DP_TRAINING_PATTERN_3: + /* drm_dbg_kms(&dev_priv->drm, + "TPS3 not supported, using TPS2 instead\n"); */ + DP |= DP_LINK_TRAIN_PAT_2_CPT; + break; + } + intel_dp->controller->write32(DP_TP_CTL(intel_dp->controller->OutputPath.Port), DP); +} + +void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, + UINT8 dp_train_pat) +{ + // UINT8 train_pat_mask = drm_dp_training_pattern_mask(); + + g4x_set_link_train(intel_dp, dp_train_pat); +} + +static BOOLEAN +intel_dp_set_link_train(struct intel_dp *intel_dp, + UINT8 dp_train_pat) +{ + UINT8 buf[sizeof(intel_dp->train_set) + 1]; + int ret, len; + i915_CONTROLLER *controller = intel_dp->controller; + intel_dp_program_link_training_pattern(intel_dp, dp_train_pat); + + buf[0] = dp_train_pat; + if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == + DP_TRAINING_PATTERN_DISABLE) + { + /* don't write DP_TRAINING_LANEx_SET on disable */ + len = 1; + } + else + { + for (int i = 0; i < intel_dp->lane_count; i++) + { + buf[i + 1] = intel_dp->train_set[i]; + } + /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ + //memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); + len = intel_dp->lane_count + 1; + } + + ret = drm_dp_dpcd_write(DP_TRAINING_PATTERN_SET, + buf, len, controller); + + return ret == len; +} + +static BOOLEAN +intel_dp_reset_link_train(struct intel_dp *intel_dp, + UINT8 dp_train_pat, i915_CONTROLLER *controller) +{ + for (int i = 0; i < 4; i++) + { + intel_dp->train_set[i] = 0; + } + intel_dp_set_signal_levels(intel_dp); + return intel_dp_set_link_train(intel_dp, dp_train_pat); +} + +UINT8 drm_dp_link_rate_to_bw_code(int link_rate) +{ + /* Spec says link_bw = link_rate / 0.27Gbps */ + return link_rate / 27000; +} +void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, + UINT8 *link_bw, UINT8 *rate_select) +{ + /* eDP 1.4 rate select method. */ + /* if (intel_dp->use_rate_select) { + *link_bw = 0; + *rate_select = + intel_dp_rate_select(intel_dp, port_clock); + } else { */ + *link_bw = drm_dp_link_rate_to_bw_code(port_clock); + *rate_select = 0; + // } +} +static BOOLEAN intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp) +{ + int lane; + + for (lane = 0; lane < intel_dp->lane_count; lane++) + if ((intel_dp->train_set[lane] & + DP_TRAIN_MAX_SWING_REACHED) == 0) + return FALSE; + + return TRUE; +} +#define DP_PLL_FREQ_270MHZ (0 << 16) +#define DP_PLL_FREQ_162MHZ (1 << 16) +#define DP_PLL_FREQ_MASK (3 << 16) +/* Enable corresponding port and start training pattern 1 */ +static BOOLEAN +intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) +{ + i915_CONTROLLER *controller = intel_dp->controller; + //struct drm_i915_private *i915 = dp_to_i915(intel_dp); + UINT8 voltage; + int voltage_tries, cr_tries, max_cr_tries; + BOOLEAN max_vswing_reached = FALSE; + UINT8 link_config[2]; + UINT8 link_bw, rate_select; + intel_dp_compute_rate(intel_dp, intel_dp->link_rate, + &link_bw, &rate_select); + /* if (intel_dp->prepare_link_retrain) + intel_dp->prepare_link_retrain(intel_dp); + */ + /* if ((controller->read32(0x64000) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) + intel_dp_compute_rate(intel_dp, 162000, + &link_bw, &rate_select); + else + intel_dp_compute_rate(intel_dp, 270000, + &link_bw, &rate_select); */ + //WHAT RATE IS PLUGGED IN? Port Clock + + if (link_bw) + PRINT_DEBUG(EFI_D_ERROR, "Using LINK_BW_SET value %u\n", link_bw); + else + PRINT_DEBUG(EFI_D_ERROR, "Using LINK_RATE_SET value %u\n", rate_select); + + /* Write the link configuration data */ + link_config[0] = link_bw; + link_config[1] = intel_dp->lane_count; + /* if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; */ + drm_dp_dpcd_write(DP_LINK_BW_SET, link_config, 2, controller); + + /* eDP 1.4 rate select method. */ + if (!link_bw) + drm_dp_dpcd_write(DP_LINK_RATE_SET, + &rate_select, 1, controller); + + link_config[0] = 0; + link_config[1] = DP_SET_ANSI_8B10B; + drm_dp_dpcd_write(DP_DOWNSPREAD_CTRL, link_config, 2, controller); + + //intel_dp->DP |= DP_PORT_EN; + + /* clock recovery */ + if (!intel_dp_reset_link_train(intel_dp, + DP_TRAINING_PATTERN_1 | + DP_LINK_SCRAMBLING_DISABLE, + controller)) + { + PRINT_DEBUG(EFI_D_ERROR, "failed to enable link training\n"); + return TRUE; + } + + /* + * The DP 1.4 spec defines the max clock recovery retries value + * as 10 but for pre-DP 1.4 devices we set a very tolerant + * retry limit of 80 (4 voltage levels x 4 preemphasis levels x + * x 5 identical voltage retries). Since the previous specs didn't + * define a limit and created the possibility of an infinite loop + * we want to prevent any sync from triggering that corner case. + */ + // if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) + // max_cr_tries = 10; + // else + max_cr_tries = 80; + + voltage_tries = 1; + for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) + { + UINT8 link_status[DP_LINK_STATUS_SIZE]; + gBS->Stall(600); + //drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); + + if (!intel_dp_get_link_status(link_status, controller)) + { + PRINT_DEBUG(EFI_D_ERROR, "failed to get link status\n"); + return FALSE; + } + + if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) + { + PRINT_DEBUG(EFI_D_ERROR, "clock recovery OK\n"); + return TRUE; + } + + if (voltage_tries == 5) + { + PRINT_DEBUG(EFI_D_ERROR, + "Same voltage tried 5 times\n"); + return FALSE; + } + + if (max_vswing_reached) + { + PRINT_DEBUG(EFI_D_ERROR, "Max Voltage Swing reached\n"); + return FALSE; + } + + voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + PRINT_DEBUG(EFI_D_ERROR, + "Voltage used: %08x\n", voltage); + /* Update training set as requested by target */ + intel_dp_get_adjust_train(intel_dp, link_status); + if (!intel_dp_update_link_train(intel_dp)) + { + PRINT_DEBUG(EFI_D_ERROR, + "failed to update link training\n"); + return FALSE; + } + + if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == + voltage) + ++voltage_tries; + else + voltage_tries = 1; + + if (intel_dp_link_max_vswing_reached(intel_dp)) + max_vswing_reached = TRUE; + } + PRINT_DEBUG(EFI_D_ERROR, + "Failed clock recovery %d times, giving up!\n", max_cr_tries); + return FALSE; +} +/* + * Pick training pattern for channel equalization. Training pattern 4 for HBR3 + * or for 1.4 devices that support it, training Pattern 3 for HBR2 + * or 1.2 devices that support it, Training Pattern 2 otherwise. + */ +static UINT32 intel_dp_training_pattern(struct intel_dp *intel_dp) +{ + //BOOELAN source_tps3, sink_tps3, source_tps4, sink_tps4; + + /* + * Intel platforms that support HBR3 also support TPS4. It is mandatory + * for all downstream devices that support HBR3. There are no known eDP + * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 + * specification. + */ + /* source_tps4 = intel_dp_source_supports_hbr3(intel_dp); + sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd); + if (source_tps4 && sink_tps4) { + return DP_TRAINING_PATTERN_4; + } else if (intel_dp->link_rate == 810000) { + if (!source_tps4) + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "8.1 Gbps link rate without source HBR3/TPS4 support\n"); + if (!sink_tps4) + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "8.1 Gbps link rate without sink TPS4 support\n"); */ + //} */ + /* + * Intel platforms that support HBR2 also support TPS3. TPS3 support is + * also mandatory for downstream devices that support HBR2. However, not + * all sinks follow the spec. + */ + /* source_tps3 = intel_dp_source_supports_hbr2(intel_dp); + sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); + if (source_tps3 && sink_tps3) { + return DP_TRAINING_PATTERN_3; + } else if (intel_dp->link_rate >= 540000) { + if (!source_tps3) + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); + if (!sink_tps3) + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); */ + //} */ + + return DP_TRAINING_PATTERN_2; +} +BOOLEAN drm_dp_channel_eq_ok(const UINT8 link_status[DP_LINK_STATUS_SIZE], + int lane_count) +{ + UINT8 lane_align; + UINT8 lane_status; + int lane; + + lane_align = dp_link_status(link_status, + DP_LANE_ALIGN_STATUS_UPDATED); + if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) + { + PRINT_DEBUG(EFI_D_ERROR, "NO Lane Align\n"); + return FALSE; + } + for (lane = 0; lane < lane_count; lane++) + { + lane_status = dp_get_lane_status(link_status, lane); + if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) + { + PRINT_DEBUG(EFI_D_ERROR, "NO EQ BITS\n"); + return FALSE; + } + } + return TRUE; +} +static BOOLEAN +intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) +{ + //struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int tries; + UINT32 training_pattern; + UINT8 link_status[DP_LINK_STATUS_SIZE]; + BOOLEAN channel_eq = FALSE; + + training_pattern = intel_dp_training_pattern(intel_dp); + /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ + if (training_pattern != DP_TRAINING_PATTERN_4) + training_pattern |= DP_LINK_SCRAMBLING_DISABLE; + + /* channel equalization */ + if (!intel_dp_set_link_train(intel_dp, + training_pattern)) + { + PRINT_DEBUG(EFI_D_ERROR, "failed to start channel equalization\n"); + return FALSE; + } + + for (tries = 0; tries < 5; tries++) + { + gBS->Stall(600); + //drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); + if (!intel_dp_get_link_status(link_status, intel_dp->controller)) + { + PRINT_DEBUG(EFI_D_ERROR, + "failed to get link status\n"); + break; + } + PRINT_DEBUG(EFI_D_ERROR, "Read Link Status 0: %x\n", link_status[0]); + PRINT_DEBUG(EFI_D_ERROR, "Read Link Status 1: %x\n", link_status[1]); + PRINT_DEBUG(EFI_D_ERROR, "Read Link Status 2: %x\n", link_status[2]); + PRINT_DEBUG(EFI_D_ERROR, "Read Link Status 3: %x\n", link_status[3]); + PRINT_DEBUG(EFI_D_ERROR, "Read Link Status 4: %x\n", link_status[4]); + PRINT_DEBUG(EFI_D_ERROR, "Read Link Status 5: %x\n", link_status[5]); + + /* Make sure clock is still ok */ + if (!drm_dp_clock_recovery_ok(link_status, + intel_dp->lane_count)) + { + //intel_dp_dump_link_status(link_status); + PRINT_DEBUG(EFI_D_ERROR, + "Clock recovery check failed, cannot continue channel equalization\n"); + break; + } + + if (drm_dp_channel_eq_ok(link_status, + intel_dp->lane_count)) + { + channel_eq = TRUE; + PRINT_DEBUG(EFI_D_ERROR, "Channel EQ done. DP Training " + "successful\n"); + break; + } + + /* Update training set as requested by target */ + intel_dp_get_adjust_train(intel_dp, link_status); + if (!intel_dp_update_link_train(intel_dp)) + { + PRINT_DEBUG(EFI_D_ERROR, + "failed to update link training\n"); + break; + } + } + + /* Try 5 times, else fail and try at lower BW */ + if (tries == 5) + { + //intel_dp_dump_link_status(link_status); + PRINT_DEBUG(EFI_D_ERROR, + "Channel equalization failed 5 times\n"); + } + + UINT32 DP = intel_dp->controller->read32(DP_TP_CTL(intel_dp->controller->OutputPath.Port)); + + DP &= ~DP_LINK_TRAIN_MASK_CPT; + + DP |= DP_TP_CTL_LINK_TRAIN_IDLE; + + intel_dp->controller->write32(DP_TP_CTL(intel_dp->controller->OutputPath.Port), DP); + return channel_eq; +} +static int intersect_rates(const int *source_rates, int source_len, + const int *sink_rates, int sink_len, + int *common_rates) +{ + int i = 0, j = 0, k = 0; + + while (i < source_len && j < sink_len) + { + if (source_rates[i] == sink_rates[j]) + { + if (k >= DP_MAX_SUPPORTED_RATES) + return k; + common_rates[k] = source_rates[i]; + ++k; + ++i; + ++j; + } + else if (source_rates[i] < sink_rates[j]) + { + ++i; + } + else + { + ++j; + } + } + return k; +} +int intel_dp_max_data_rate(int max_link_clock, int max_lanes) +{ + /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the + * link rate that is generally expressed in Gbps. Since, 8 bits of data + * is transmitted every LS_Clk per lane, there is no need to account for + * the channel encoding that is done in the PHY layer here. + */ + + return max_link_clock * max_lanes; +} +INT32 intel_dp_link_required(int pixel_clock, int bpp) +{ + /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ + return DIV_ROUND_UP(pixel_clock * bpp, 8); +} +static BOOLEAN intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, + int link_rate, + UINT8 lane_count) +{ + /* const struct drm_display_mode *fixed_mode = + intel_dp->attached_connector->panel.fixed_mode; */ + int mode_rate, max_rate; + + mode_rate = intel_dp_link_required(intel_dp->controller->edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock * 10, 24); + max_rate = intel_dp_max_data_rate(link_rate, lane_count); + PRINT_DEBUG(EFI_D_ERROR, "Mode: %u, Max:%u\n", mode_rate, max_rate); + if (mode_rate > max_rate) + return FALSE; + + return TRUE; +} +static void intel_dp_set_common_rates(struct intel_dp *intel_dp) +{ + //WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); + + intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, + intel_dp->num_source_rates, + intel_dp->sink_rates, + intel_dp->num_sink_rates, + intel_dp->common_rates); + + /* Paranoia, there should always be something in common. */ + if (intel_dp->num_common_rates == 0) + { + intel_dp->common_rates[0] = 162000; + intel_dp->num_common_rates = 1; + } + intel_dp->max_link_rate = intel_dp->common_rates[intel_dp->num_common_rates - 1]; +} +static int intel_dp_rate_index(const int *rates, int len, int rate) +{ + int i; + + for (i = 0; i < len; i++) + if (rate == rates[i]) + return i; + + return -1; +} +static int intel_dp_max_common_rate(struct intel_dp *intel_dp) +{ + return intel_dp->common_rates[intel_dp->num_common_rates - 1]; +} + +int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, + int link_rate, UINT8 lane_count) +{ + // struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int index; + if (intel_dp->controller->OutputPath.ConType == eDP && !intel_dp->use_max_rate) + { + intel_dp->use_max_rate = true; + return 0; + } + index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + link_rate); + if (index > 0) + { + if (intel_dp->controller->OutputPath.ConType == eDP && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, + intel_dp->common_rates[index - 1], + lane_count)) + { + PRINT_DEBUG(EFI_D_ERROR, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; + intel_dp->max_link_lane_count = lane_count; + } + else if (lane_count > 1) + { + if (intel_dp->controller->OutputPath.ConType == eDP && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, + intel_dp_max_common_rate(intel_dp), + lane_count >> 1)) + { + PRINT_DEBUG(EFI_D_ERROR, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->max_link_lane_count = lane_count >> 1; + } + else + { + PRINT_DEBUG(EFI_D_ERROR, "Link Training Unsuccessful\n"); + return -1; + } + intel_dp->lane_count = intel_dp->max_link_lane_count; + intel_dp->link_rate = intel_dp->max_link_rate; + + return 0; +} +static void +intel_dp_set_source_rates(struct intel_dp *intel_dp) +{ + /* The values must be in increasing order */ + /* static const int cnl_rates[] = { + 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 + }; + static const int bxt_rates[] = { + 162000, 216000, 243000, 270000, 324000, 432000, 540000 + }; + + static const int hsw_rates[] = { + 162000, 270000, 540000 + }; + static const int g4x_rates[] = { + 162000, 270000 + }; +*/ + static const int skl_rates[] = { + 162000, 216000, 270000, 324000, 432000, 540000}; + /* static const int skl_rates[] = { + 162000, 216000, 270000}; */ + /* struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); */ + const int *source_rates; + int size; + //int max_rate = 0, vbt_max_rate; + + /* This should only be done once */ + /* drm_WARN_ON(&dev_priv->drm, + intel_dp->source_rates || intel_dp->num_source_rates); + */ + /* if (INTEL_GEN(dev_priv) >= 10) { + source_rates = cnl_rates; + size = ARRAY_SIZE(cnl_rates); + if (IS_GEN(dev_priv, 10)) + max_rate = cnl_max_source_rate(intel_dp); + else + max_rate = icl_max_source_rate(intel_dp); + } else if (IS_GEN9_LP(dev_priv)) { + source_rates = bxt_rates; + size = ARRAY_SIZE(bxt_rates); + } else if (IS_GEN9_BC(dev_priv)) { */ + source_rates = skl_rates; + size = ARRAY_SIZE(skl_rates); + /* } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || + IS_BROADWELL(dev_priv)) { + source_rates = hsw_rates; + size = ARRAY_SIZE(hsw_rates); + } else { + source_rates = g4x_rates; + size = ARRAY_SIZE(g4x_rates); + } */ + + /* vbt_max_rate = intel_bios_dp_max_link_rate(encoder); + if (max_rate && vbt_max_rate) + max_rate = min(max_rate, vbt_max_rate); + else if (vbt_max_rate) + max_rate = vbt_max_rate; */ + + /* if (max_rate) + size = intel_dp_rate_limit_len(source_rates, size, max_rate); */ + + intel_dp->source_rates = source_rates; + intel_dp->num_source_rates = size; +} + +/* update sink rates from dpcd. We don't read the dpcd(Should we?) So manually adding the 324000 sink rate */ +static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) +{ + static const int dp_rates[] = { + 162000, 270000, 540000, 810000}; + int i, max_rate; + + /* if (drm_dp_has_quirk(&intel_dp->desc, 0, + DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { */ + /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel + int quirk_rates[] = {162000, 270000, 324000}; + + memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); + intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); + + return; + } */ + + max_rate = dp_rates[3]; + + for (i = 0; i < ARRAY_SIZE(dp_rates); i++) + { + if (dp_rates[i] > max_rate) + break; + intel_dp->sink_rates[i] = dp_rates[i]; + } + + intel_dp->num_sink_rates = i; +} +/* Get length of rates array potentially limited by max_rate. */ +static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) +{ + int i; + + /* Limit results by potentially reduced max rate */ + for (i = 0; i < len; i++) + { + if (rates[len - i - 1] <= max_rate) + return len - i; + } + + return 0; +} + +/* Get length of common rates array potentially limited by max_rate. */ +static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, + int max_rate) +{ + return intel_dp_rate_limit_len(intel_dp->common_rates, + intel_dp->num_common_rates, max_rate); +} +/* Optimize link config in order: max bpp, min clock, min lanes */ +static EFI_STATUS +intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, + const struct link_config_limits *limits) +{ + int bpp, clock, lane_count; + int mode_rate, link_clock, link_avail; + + for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) + { + //int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); + int output_bpp = bpp; + + mode_rate = intel_dp_link_required(intel_dp->controller->edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock * 10, + output_bpp); + + for (clock = limits->min_clock; clock <= limits->max_clock; clock++) + { + for (lane_count = limits->min_lane_count; + lane_count <= limits->max_lane_count; + lane_count <<= 1) + { + link_clock = intel_dp->common_rates[clock]; + link_avail = intel_dp_max_data_rate(link_clock, + lane_count); + + if (mode_rate <= link_avail) + { + intel_dp->lane_count = lane_count; + intel_dp->pipe_bpp = bpp; + intel_dp->link_rate = link_clock; + + return 0; + } + } + } + } + + return EFI_UNSUPPORTED; +} + +static EFI_STATUS i915_dp_get_link_config(struct intel_dp *intel_dp) +{ + struct link_config_limits limits; + int common_len; + int ret; + + common_len = intel_dp_common_len_rate_limit(intel_dp, + intel_dp->max_link_rate); + + limits.min_clock = 0; + limits.max_clock = common_len - 1; + + limits.min_lane_count = 1; + limits.max_lane_count = intel_dp->max_link_lane_count; + + limits.min_bpp = 18; + //limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); + limits.max_bpp = 24; //Setting a reasonable(hopefully) default + PRINT_DEBUG(EFI_D_ERROR, "max_clock index: %d, common_len: %d, clock rate[0]: %d, max_link_rate: %d, clockrate[3]: %d \n", limits.max_clock, common_len, intel_dp->common_rates[0], intel_dp->max_link_rate, 0); + if (intel_dp->use_max_rate) + { + /* + * Use the maximum clock and number of lanes the eDP panel + * advertizes being capable of in case the initial fast + * optimal params failed us. The panels are generally + * designed to support only a single clock and lane + * configuration, and typically on older panels these + * values correspond to the native resolution of the panel. + */ + limits.min_lane_count = limits.max_lane_count; + limits.min_clock = limits.max_clock; + } + + //intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); //Ignoring. Hopefully still works. + + PRINT_DEBUG(EFI_D_ERROR, "DP link computation with max lane count %d max rate %d max bpp %d pixel clock %dKHz\n", + limits.max_lane_count, + intel_dp->common_rates[limits.max_clock], + limits.max_bpp, intel_dp->controller->edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock * 10); + + /* + * Optimize for slow and wide for everything, because there are some + * eDP 1.3 and 1.4 panels don't work well with fast and narrow. + */ + ret = intel_dp_compute_link_config_wide(intel_dp, &limits); + return ret; +} + +EFI_STATUS _TrainDisplayPort(struct intel_dp *intel_dp) +{ + UINT32 port = intel_dp->controller->OutputPath.Port; + UINT32 val = intel_dp->controller->read32(DP_TP_CTL(port)); + val &= ~(DP_TP_CTL_ENABLE); + // val |= DP_TP_CTL_MODE_SST; + // val |= DP_TP_CTL_LINK_TRAIN_PAT1; + //val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; + intel_dp->controller->write32(DP_TP_CTL(port), val); + val = intel_dp->controller->read32(DDI_BUF_CTL(port)); + val &= ~(DDI_PORT_WIDTH_MASK | DDI_BUF_CTL_ENABLE); + //val |= DDI_BUF_TRANS_SELECT(0); + //val |= DDI_A_4_LANES; + val |= DDI_PORT_WIDTH(intel_dp->lane_count); + intel_dp->controller->write32(DDI_BUF_CTL(port), val); + + gBS->Stall(600); + val = intel_dp->controller->read32(DP_TP_CTL(port)); + val |= DP_TP_CTL_ENABLE; + intel_dp->controller->write32(DP_TP_CTL(port), val); + + val = intel_dp->controller->read32(DDI_BUF_CTL(port)); + val |= DDI_BUF_CTL_ENABLE; + + intel_dp->controller->write32(DDI_BUF_CTL(port), val); + if (!intel_dp_link_training_clock_recovery(intel_dp)) + goto failure_handling; + if (!intel_dp_link_training_channel_equalization(intel_dp)) + goto failure_handling; + intel_dp_set_link_train(intel_dp, + DP_TRAINING_PATTERN_DISABLE); + UINT32 DP = intel_dp->controller->read32(DP_TP_CTL(port)); + + DP &= ~DP_LINK_TRAIN_MASK_CPT; + + DP |= DP_TP_CTL_LINK_TRAIN_NORMAL; + + intel_dp->controller->write32(DP_TP_CTL(port), DP); + PRINT_DEBUG(EFI_D_ERROR, "Link Rate: %d, lane count: %d\n", + intel_dp->controller->OutputPath.LinkRate, intel_dp->lane_count); + intel_dp->controller->OutputPath.LinkRate = intel_dp->link_rate; + intel_dp->controller->OutputPath.LaneCount = intel_dp->lane_count; + + return EFI_SUCCESS; +failure_handling: + PRINT_DEBUG(EFI_D_ERROR, + " Link Training failed at link rate = %d, lane count = %d\n", + intel_dp->link_rate, intel_dp->lane_count); + if (!intel_dp_get_link_train_fallback_values(intel_dp, + intel_dp->link_rate, + intel_dp->lane_count)) + { + intel_dp->controller->OutputPath.LinkRate = intel_dp->link_rate; + intel_dp->controller->OutputPath.LaneCount = intel_dp->lane_count; + SetupClockeDP(intel_dp->controller); + + /* Schedule a Hotplug Uevent to userspace to start modeset */ + return _TrainDisplayPort(intel_dp); + } + else if (intel_dp->use_max_rate) + { + i915_dp_get_link_config(intel_dp); + return _TrainDisplayPort(intel_dp); + } + return EFI_ABORTED; +} + +EFI_STATUS TrainDisplayPort(i915_CONTROLLER *controller) +{ + UINT32 port = controller->OutputPath.Port; + UINT32 val = 0; + EFI_STATUS status = EFI_SUCCESS; + val |= DP_TP_CTL_ENABLE; + val |= DP_TP_CTL_MODE_SST; + val |= DP_TP_CTL_LINK_TRAIN_PAT1; + val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; + controller->write32(DP_TP_CTL(port), val); + val = DDI_BUF_CTL_ENABLE; + + val |= DDI_BUF_TRANS_SELECT(0); + val |= DDI_A_4_LANES; + val |= DDI_PORT_WIDTH(4); + controller->write32(DDI_BUF_CTL(port), val); + gBS->Stall(500); + + struct intel_dp *intel_dp = controller->intel_dp; + intel_dp->controller = controller; + intel_dp->max_link_lane_count = 4; + edp_panel_on(intel_dp); + // intel_dp->lane_count = 2; + // if ((controller->read32(0x64000) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) + // intel_dp->link_rate = 162000; + // else + // intel_dp->link_rate = 270000; + + intel_dp_set_source_rates(intel_dp); + + intel_dp_set_sink_rates(intel_dp); + + intel_dp_set_common_rates(intel_dp); + i915_dp_get_link_config(intel_dp); + status = _TrainDisplayPort(intel_dp); + UINT8 count = 0; + while (!intel_dp_can_link_train_fallback_for_edp(intel_dp, intel_dp->link_rate, intel_dp->lane_count) && count < 4) + { + PRINT_DEBUG(EFI_D_ERROR, "Higher rate than configured, Trying Lower Pixel Clock\n"); + controller->edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock >>= 1; + count++; + } + if ((count == 4) && (!intel_dp_can_link_train_fallback_for_edp(intel_dp, intel_dp->link_rate, intel_dp->lane_count))) + { + PRINT_DEBUG(EFI_D_ERROR, "Error: Higher rate than configured\n"); + + status = EFI_UNSUPPORTED; + } + return status; +} +/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ +#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ +#define TU_SIZE_SHIFT 25 +#define TU_SIZE_MASK (0x3f << 25) + +#define DATA_LINK_M_N_MASK (0xffffff) +#define DATA_LINK_N_MAX (0x800000) +UINT32 roundup_pow_of_two(UINT32 v) +{ + + v--; + v |= v >> 1; + v |= v >> 2; + v |= v >> 4; + v |= v >> 8; + v |= v >> 16; + v++; + return v; +} +static void +intel_reduce_m_n_ratio(UINT32 *num, UINT32 *den) +{ + while (*num > DATA_LINK_M_N_MASK || + *den > DATA_LINK_M_N_MASK) + { + *num >>= 1; + *den >>= 1; + } +} +static inline UINT64 div_UINT64_rem(UINT64 dividend, UINT32 divisor, UINT32 *remainder) +{ + union + { + UINT64 v64; + UINT32 v32[2]; + } d = {dividend}; + UINT32 upper; + + upper = d.v32[1]; + d.v32[1] = 0; + if (upper >= divisor) + { + d.v32[1] = upper / divisor; + upper %= divisor; + } + asm("divl %2" + : "=a"(d.v32[0]), "=d"(*remainder) + : "rm"(divisor), "0"(d.v32[0]), "1"(upper)); + return d.v64; +} +static inline UINT64 div_UINT64(UINT64 dividend, UINT32 divisor) +{ + UINT32 remainder; + return div_UINT64_rem(dividend, divisor, &remainder); +} +static inline UINT64 mul_UINT32_UINT32(UINT32 a, UINT32 b) +{ + UINT32 high, low; + + asm("mull %[b]" + : "=a"(low), "=d"(high) + : [a] "a"(a), [b] "rm"(b)); + + return low | ((UINT64)high) << 32; +} +static void compute_m_n(unsigned int m, unsigned int n, + UINT32 *ret_m, UINT32 *ret_n, + BOOLEAN constant_n) +{ + /* controller->write32(0x6f030, 0x7e6cf53b); + controller->write32(0x6f034, 0x00800000); + controller->write32(0x6f040, 0x00048a37); + controller->write32(0x6f044, 0x00080000); */ + /* + * Several DP dongles in particular seem to be fussy about + * too large link M/N values. Give N value as 0x8000 that + * should be acceptable by specific devices. 0x8000 is the + * specified fixed N value for asynchronous clock mode, + * which the devices expect also in synchronous clock mode. + */ + PRINT_DEBUG(EFI_D_ERROR, "progressed to dpline %d\n", + __LINE__); + if (constant_n) + *ret_n = 0x8000; + else + *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); + + PRINT_DEBUG(EFI_D_ERROR, "progressed to dpline %d\n", + __LINE__); + PRINT_DEBUG(EFI_D_ERROR, "m: %u, n: %u, ret_n: %u\n", m, n, *ret_n); + *ret_m = div_UINT64(mul_UINT32_UINT32(m, *ret_n), n); + intel_reduce_m_n_ratio(ret_m, ret_n); +} +struct intel_link_m_n +{ + UINT32 tu; + UINT32 gmch_m; + UINT32 gmch_n; + UINT32 link_m; + UINT32 link_n; +}; +void intel_link_compute_m_n(UINT16 bits_per_pixel, int nlanes, + int pixel_clock, int link_clock, + struct intel_link_m_n *m_n, + BOOLEAN constant_n, BOOLEAN fec_enable) +{ + UINT32 data_clock = bits_per_pixel * pixel_clock; + PRINT_DEBUG(EFI_D_ERROR, "intel_link_compute_m_n: bpp: %u, lanes: %u, pclock:%u, link_clock: %u\n", + bits_per_pixel, nlanes, pixel_clock, link_clock); + /* if (fec_enable) + data_clock = intel_dp_mode_to_fec_clock(data_clock); + */ + PRINT_DEBUG(EFI_D_ERROR, "progressed to dpline %d\n", + __LINE__); + m_n->tu = 64; + PRINT_DEBUG(EFI_D_ERROR, "progressed to dpline %d\n", + __LINE__); + compute_m_n(data_clock, + link_clock * nlanes * 8, + &(m_n->gmch_m), &(m_n->gmch_n), + constant_n); + PRINT_DEBUG(EFI_D_ERROR, "progressed to dpline %d\n", + __LINE__); + compute_m_n(pixel_clock, link_clock, + &m_n->link_m, &m_n->link_n, + constant_n); + PRINT_DEBUG(EFI_D_ERROR, "progressed to dpline %d\n", + __LINE__); +} + +EFI_STATUS SetupTranscoderAndPipeDP(i915_CONTROLLER *controller) +{ + UINT32 horz_active = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActive | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActiveBlankMsb >> 4) << 8); + UINT32 horz_blank = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzBlank | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActiveBlankMsb & 0xF) << 8); + UINT32 horz_sync_offset = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzSyncOffset | ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 6) << 8); + UINT32 horz_sync_pulse = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzSyncPulse | + (((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 4) & 0x3) << 8); + + UINT32 horizontal_active = horz_active; + UINT32 horizontal_syncStart = horz_active + horz_sync_offset; + UINT32 horizontal_syncEnd = horz_active + horz_sync_offset + horz_sync_pulse; + UINT32 horizontal_total = horz_active + horz_blank; + + UINT32 vert_active = controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActive | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActiveBlankMsb >> 4) << 8); + UINT32 vert_blank = controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertBlank | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActiveBlankMsb & 0xF) << 8); + UINT32 vert_sync_offset = (controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertSync >> 4) | (((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 2) & 0x3) + << 4); + UINT32 vert_sync_pulse = (controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertSync & 0xF) | ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb & 0x3) << 4); + + UINT32 vertical_active = vert_active; + UINT32 vertical_syncStart = vert_active + vert_sync_offset; + UINT32 vertical_syncEnd = vert_active + vert_sync_offset + vert_sync_pulse; + UINT32 vertical_total = vert_active + vert_blank; + + controller->write32(VSYNCSHIFT_A, 0); + + controller->write32(HTOTAL_A, + (horizontal_active - 1) | + ((horizontal_total - 1) << 16)); + controller->write32(HBLANK_A, + (horizontal_active - 1) | + ((horizontal_total - 1) << 16)); + controller->write32(HSYNC_A, + (horizontal_syncStart - 1) | + ((horizontal_syncEnd - 1) << 16)); + + controller->write32(VTOTAL_A, + (vertical_active - 1) | + ((vertical_total - 1) << 16)); + controller->write32(VBLANK_A, + (vertical_active - 1) | + ((vertical_total - 1) << 16)); + controller->write32(VSYNC_A, + (vertical_syncStart - 1) | + ((vertical_syncEnd - 1) << 16)); + + controller->write32(PIPEASRC, ((horizontal_active - 1) << 16) | (vertical_active - 1)); + struct intel_link_m_n m_n = {0}; + + intel_link_compute_m_n(24, controller->OutputPath.LaneCount, controller->edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock * 10, controller->OutputPath.LinkRate, &m_n, FALSE, FALSE); + controller->write32(PIPEA_DATA_M1, + TU_SIZE(m_n.tu) | m_n.gmch_m); + controller->write32(PIPEA_DATA_N1, + m_n.gmch_n); + controller->write32(PIPEA_LINK_M1, + m_n.link_m); + controller->write32(PIPEA_LINK_N1, + m_n.link_n); + PRINT_DEBUG(EFI_D_ERROR, "HTOTAL_A (%x) = %08x\n", HTOTAL_A, controller->read32(HTOTAL_A)); + PRINT_DEBUG(EFI_D_ERROR, "HBLANK_A (%x) = %08x\n", HBLANK_A, controller->read32(HBLANK_A)); + PRINT_DEBUG(EFI_D_ERROR, "HSYNC_A (%x) = %08x\n", HSYNC_A, controller->read32(HSYNC_A)); + PRINT_DEBUG(EFI_D_ERROR, "VTOTAL_A (%x) = %08x\n", VTOTAL_A, controller->read32(VTOTAL_A)); + PRINT_DEBUG(EFI_D_ERROR, "VBLANK_A (%x) = %08x\n", VBLANK_A, controller->read32(VBLANK_A)); + PRINT_DEBUG(EFI_D_ERROR, "VSYNC_A (%x) = %08x\n", VSYNC_A, controller->read32(VSYNC_A)); + PRINT_DEBUG(EFI_D_ERROR, "PIPEASRC (%x) = %08x\n", PIPEASRC, controller->read32(PIPEASRC)); + PRINT_DEBUG(EFI_D_ERROR, "BCLRPAT_A (%x) = %08x\n", BCLRPAT_A, controller->read32(BCLRPAT_A)); + PRINT_DEBUG(EFI_D_ERROR, "VSYNCSHIFT_A (%x) = %08x\n", VSYNCSHIFT_A, controller->read32(VSYNCSHIFT_A)); + + PRINT_DEBUG(EFI_D_ERROR, "before pipe gamma\n"); + return EFI_SUCCESS; +} +EFI_STATUS SetupTranscoderAndPipeEDP(i915_CONTROLLER *controller) +{ + UINT32 horz_active = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActive | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActiveBlankMsb >> 4) << 8); + UINT32 horz_blank = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzBlank | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActiveBlankMsb & 0xF) << 8); + UINT32 horz_sync_offset = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzSyncOffset | ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 6) << 8); + UINT32 horz_sync_pulse = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzSyncPulse | + (((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 4) & 0x3) << 8); + + UINT32 horizontal_active = horz_active; + UINT32 horizontal_syncStart = horz_active + horz_sync_offset; + UINT32 horizontal_syncEnd = horz_active + horz_sync_offset + horz_sync_pulse; + UINT32 horizontal_total = horz_active + horz_blank; + + UINT32 vert_active = controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActive | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActiveBlankMsb >> 4) << 8); + UINT32 vert_blank = controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertBlank | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActiveBlankMsb & 0xF) << 8); + UINT32 vert_sync_offset = (controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertSync >> 4) | (((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 2) & 0x3) + << 4); + UINT32 vert_sync_pulse = (controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertSync & 0xF) | ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb & 0x3) << 4); + + UINT32 vertical_active = vert_active; + UINT32 vertical_syncStart = vert_active + vert_sync_offset; + UINT32 vertical_syncEnd = vert_active + vert_sync_offset + vert_sync_pulse; + UINT32 vertical_total = vert_active + vert_blank; + + controller->write32(VSYNCSHIFT_EDP, 0); + + controller->write32(HTOTAL_EDP, + (horizontal_active - 1) | + ((horizontal_total - 1) << 16)); + controller->write32(HBLANK_EDP, + (horizontal_active - 1) | + ((horizontal_total - 1) << 16)); + controller->write32(HSYNC_EDP, + (horizontal_syncStart - 1) | + ((horizontal_syncEnd - 1) << 16)); + + controller->write32(VTOTAL_EDP, + (vertical_active - 1) | + ((vertical_total - 1) << 16)); + controller->write32(VBLANK_EDP, + (vertical_active - 1) | + ((vertical_total - 1) << 16)); + controller->write32(VSYNC_EDP, + (vertical_syncStart - 1) | + ((vertical_syncEnd - 1) << 16)); + + controller->write32(PIPEASRC, ((horizontal_active - 1) << 16) | (vertical_active - 1)); + /* controller->write32(0x6f030, 0x7e6cf53b); + controller->write32(0x6f034, 0x00800000); + controller->write32(0x6f040, 0x00048a37); + controller->write32(0x6f044, 0x00080000); */ + struct intel_link_m_n m_n = {0}; + //struct intel_link_m_n *m_n= &m_n + intel_link_compute_m_n(24, controller->OutputPath.LaneCount, controller->edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock * 10, controller->OutputPath.LinkRate, &m_n, FALSE, FALSE); + PRINT_DEBUG(EFI_D_ERROR, "progressed to dpline %d\n", + __LINE__); + PRINT_DEBUG(EFI_D_ERROR, "PIPEEDP_DATA_M1 (%x) = %08x\n", PIPEEDP_DATA_M1, TU_SIZE(m_n.tu) | m_n.gmch_m); + PRINT_DEBUG(EFI_D_ERROR, "PIPEEDP_DATA_N1 (%x) = %08x\n", PIPEEDP_DATA_N1, m_n.gmch_n); + PRINT_DEBUG(EFI_D_ERROR, "PIPEEDP_LINK_M1 (%x) = %08x\n", PIPEEDP_LINK_M1, m_n.link_m); + PRINT_DEBUG(EFI_D_ERROR, "PIPEEDP_LINK_N1 (%x) = %08x\n", PIPEEDP_LINK_N1, m_n.link_n); + + controller->write32(PIPEEDP_DATA_M1, + TU_SIZE(m_n.tu) | m_n.gmch_m); + controller->write32(PIPEEDP_DATA_N1, + m_n.gmch_n); + controller->write32(PIPEEDP_LINK_M1, + m_n.link_m); + controller->write32(PIPEEDP_LINK_N1, + m_n.link_n); + PRINT_DEBUG(EFI_D_ERROR, "HTOTAL_EDP (%x) = %08x\n", HTOTAL_EDP, controller->read32(HTOTAL_EDP)); + PRINT_DEBUG(EFI_D_ERROR, "HBLANK_EDP (%x) = %08x\n", HBLANK_EDP, controller->read32(HBLANK_EDP)); + PRINT_DEBUG(EFI_D_ERROR, "HSYNC_EDP (%x) = %08x\n", HSYNC_EDP, controller->read32(HSYNC_EDP)); + PRINT_DEBUG(EFI_D_ERROR, "VTOTAL_EDP (%x) = %08x\n", VTOTAL_EDP, controller->read32(VTOTAL_EDP)); + PRINT_DEBUG(EFI_D_ERROR, "VBLANK_EDP (%x) = %08x\n", VBLANK_EDP, controller->read32(VBLANK_EDP)); + PRINT_DEBUG(EFI_D_ERROR, "VSYNC_EDP (%x) = %08x\n", VSYNC_EDP, controller->read32(VSYNC_EDP)); + PRINT_DEBUG(EFI_D_ERROR, "PIPEASRC (%x) = %08x\n", PIPEASRC, controller->read32(PIPEASRC)); + PRINT_DEBUG(EFI_D_ERROR, "BCLRPAT_EDP (%x) = %08x\n", BCLRPAT_EDP, controller->read32(BCLRPAT_EDP)); + PRINT_DEBUG(EFI_D_ERROR, "VSYNCSHIFT_EDP (%x) = %08x\n", VSYNCSHIFT_EDP, controller->read32(VSYNCSHIFT_EDP)); + + PRINT_DEBUG(EFI_D_ERROR, "before pipe gamma\n"); + return EFI_SUCCESS; +} +EFI_STATUS SetupPPS(i915_CONTROLLER *controller) +{ + PRINT_DEBUG(EFI_D_ERROR, "Setting up PPS\n"); + gBS->Stall(6000); + UINT32 max = DIV_ROUND_CLOSEST(KHz(cnp_rawclk(controller)), + 200); + controller->write32(_BXT_BLC_PWM_FREQ1, max); + controller->write32(_BXT_BLC_PWM_DUTY1, max); + + UINT32 val = controller->read32(BKL_GRAN_CTL); + val |= 1; + controller->write32(BKL_GRAN_CTL, val); + controller->write32(SBLC_PWM_CTL1, (1 << 31) | (0 << 29)); + gBS->Stall(6000); + intel_dp_pps_init(controller); + + return EFI_SUCCESS; +} +// EFI_STATUS SetupTranscoderAndPipeEDP(i915_CONTROLLER *controller) +// { +// struct intel_dp intel_dp; +// intel_dp.controller = controller; +// controller->intel_dp = &intel_dp; +// edp_panel_on(&intel_dp); +// } diff --git a/i915_dp.h b/i915_dp.h new file mode 100644 index 0000000..0deac75 --- /dev/null +++ b/i915_dp.h @@ -0,0 +1,1418 @@ +#ifndef i915_DPH +#define i915_DPH +#define PP_ON (0xC7208) +#define PP_OFF (0xC720C) +#define PANEL_UNLOCK_REGS (0xabcd << 16) +#define PANEL_UNLOCK_MASK (0xffff << 16) +#define BXT_POWER_CYCLE_DELAY_MASK 0x1f0 +#define BXT_POWER_CYCLE_DELAY_SHIFT 4 +#define EDP_FORCE_VDD (1 << 3) +#define EDP_BLC_ENABLE (1 << 2) +#define PANEL_POWER_RESET (1 << 1) +#define PANEL_POWER_OFF (0 << 0) +#define PANEL_POWER_ON (1 << 0) +#define PP_DIVISOR 0x61210 /* Cedartrail */ +#define PP_STATUS (0xC7200) +#define PP_CONTROL (0xC7204) +//#define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); }))) + +/* + * Local integer constant expression version of is_power_of_2(). + */ +#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x)-1)) == 0)) + +/** + * REG_FIELD_PREP() - Prepare a u32 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to put in the field + * + * Local copy of FIELD_PREP() to generate an integer constant expression, force + * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). + * + * @return: @__val masked and shifted into the field defined by @__mask. + */ +#define REG_FIELD_PREP(__mask, __val) \ + ((UINT32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + (!__is_constexpr(__mask)) + \ + ((__mask) == 0 || (__mask) > __UINT32_MAX__) + \ + (!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + (__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) +#define _PCH_DP_B (0xe4100) +#define _PCH_DPB_AUX_CH_CTL (0xe4110) +#define _PCH_DPB_AUX_CH_DATA1 (0xe4114) +#define _PCH_DPB_AUX_CH_DATA2 (0xe4118) +#define _PCH_DPB_AUX_CH_DATA3 (0xe411c) +#define _PCH_DPB_AUX_CH_DATA4 (0xe4120) +#define _PCH_DPB_AUX_CH_DATA5 (0xe4124) + +#define _DPA_AUX_CH_CTL (0x64010) +#define _DPA_AUX_CH_DATA1 (0x64014) +#define _DPA_AUX_CH_DATA2 (0x64018) +#define _DPA_AUX_CH_DATA3 (0x6401c) +#define _DPA_AUX_CH_DATA4 (0x64020) +#define _DPA_AUX_CH_DATA5 (0x64024) + +#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) +#define DP_AUX_CH_CTL_DONE (1 << 30) +#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) +#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) +#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ +#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) +#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 +#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) +#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 +#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) +#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) +#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) +#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) +#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 +#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) +#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) +#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) +#define DP_AUX_CH_CTL_TBT_IO (1 << 11) +#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) +#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c)-1) << 5) +#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c)-1) +#define AUX_NATIVE_WRITE 0x8 +#define AUX_NATIVE_READ 0x9 +#define AUX_I2C_WRITE 0x0 +#define AUX_I2C_READ 0x1 +#define AUX_I2C_STATUS 0x2 +#define AUX_I2C_MOT 0x4 +#define AUX_I2C_REPLY_ACK 0x0 +/* DisplayPort Transport Control */ + +// #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) +#define DP_TP_CTL_ENABLE (1 << 31) +#define DP_TP_CTL_FEC_ENABLE (1 << 30) +#define DP_TP_CTL_MODE_SST (0 << 27) +#define DP_TP_CTL_MODE_MST (1 << 27) +#define DP_TP_CTL_FORCE_ACT (1 << 25) +#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) +#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) +#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) +#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) +#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) +#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) +#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) +#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) +#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) +#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) +#define DP_MSA_MISC_SYNC_CLOCK (1 << 0) +#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8) +#define DP_MSA_MISC_STEREO_NO_3D (0 << 9) +#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9) +#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9) +/* bits per component for non-RAW */ +#define DP_MSA_MISC_6_BPC (0 << 5) +#define DP_MSA_MISC_8_BPC (1 << 5) +#define DP_MSA_MISC_10_BPC (2 << 5) +#define DP_MSA_MISC_12_BPC (3 << 5) +#define DP_MSA_MISC_16_BPC (4 << 5) +/* bits per component for RAW */ +#define DP_MSA_MISC_RAW_6_BPC (1 << 5) +#define DP_MSA_MISC_RAW_7_BPC (2 << 5) +#define DP_MSA_MISC_RAW_8_BPC (3 << 5) +#define DP_MSA_MISC_RAW_10_BPC (4 << 5) +#define DP_MSA_MISC_RAW_12_BPC (5 << 5) +#define DP_MSA_MISC_RAW_14_BPC (6 << 5) +#define DP_MSA_MISC_RAW_16_BPC (7 << 5) +/* pixel encoding/colorimetry format */ +#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \ + ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1)) +#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0) +#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0) +#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0) +#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1) +#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0) +#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0) +#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0) +#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1) +#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0) +#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1) +#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0) +#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1) +#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0) +#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1) +#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1) +#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0) +#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1) +#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14) + +#define DP_AUX_MAX_PAYLOAD_BYTES 16 + +#define DP_AUX_I2C_WRITE 0x0 +#define DP_AUX_I2C_READ 0x1 +#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 +#define DP_AUX_I2C_MOT 0x4 +#define DP_AUX_NATIVE_WRITE 0x8 +#define DP_AUX_NATIVE_READ 0x9 + +#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) +#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) +#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) +#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) + +#define DP_AUX_I2C_REPLY_ACK (0x0 << 2) +#define DP_AUX_I2C_REPLY_NACK (0x1 << 2) +#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) +#define DP_AUX_I2C_REPLY_MASK (0x3 << 2) + +/* AUX CH addresses */ +/* DPCD */ +#define DP_DPCD_REV 0x000 +#define DP_DPCD_REV_10 0x10 +#define DP_DPCD_REV_11 0x11 +#define DP_DPCD_REV_12 0x12 +#define DP_DPCD_REV_13 0x13 +#define DP_DPCD_REV_14 0x14 + +#define DP_MAX_LINK_RATE 0x001 + +#define DP_MAX_LANE_COUNT 0x002 +#define DP_MAX_LANE_COUNT_MASK 0x1f +#define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ +#define DP_ENHANCED_FRAME_CAP (1 << 7) + +#define DP_MAX_DOWNSPREAD 0x003 +#define DP_MAX_DOWNSPREAD_0_5 (1 << 0) +#define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) +#define DP_TPS4_SUPPORTED (1 << 7) + +#define DP_NORP 0x004 + +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +#define DP_DWN_STRM_PORT_PRESENT (1 << 0) +#define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +#define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) +#define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) +#define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) +#define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) +#define DP_FORMAT_CONVERSION (1 << 3) +#define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 +#define DP_CAP_ANSI_8B10B (1 << 0) + +#define DP_DOWN_STREAM_PORT_COUNT 0x007 +#define DP_PORT_COUNT_MASK 0x0f +#define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ +#define DP_OUI_SUPPORT (1 << 7) + +#define DP_RECEIVE_PORT_0_CAP_0 0x008 +#define DP_LOCAL_EDID_PRESENT (1 << 1) +#define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) + +#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 + +#define DP_RECEIVE_PORT_1_CAP_0 0x00a +#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b + +#define DP_I2C_SPEED_CAP 0x00c /* DPI */ +#define DP_I2C_SPEED_1K 0x01 +#define DP_I2C_SPEED_5K 0x02 +#define DP_I2C_SPEED_10K 0x04 +#define DP_I2C_SPEED_100K 0x08 +#define DP_I2C_SPEED_400K 0x10 +#define DP_I2C_SPEED_1M 0x20 + +#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ +#define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) +#define DP_FRAMING_CHANGE_CAP (1 << 1) +#define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ + +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ +#define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ +#define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ + +#define DP_ADAPTER_CAP 0x00f /* 1.2 */ +#define DP_FORCE_LOAD_SENSE_CAP (1 << 0) +#define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) + +#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ +#define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ + +/* Multiple stream transport */ +#define DP_FAUX_CAP 0x020 /* 1.2 */ +#define DP_FAUX_CAP_1 (1 << 0) + +#define DP_MSTM_CAP 0x021 /* 1.2 */ +#define DP_MST_CAP (1 << 0) + +#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ + +/* AV_SYNC_DATA_BLOCK 1.2 */ +#define DP_AV_GRANULARITY 0x023 +#define DP_AG_FACTOR_MASK (0xf << 0) +#define DP_AG_FACTOR_3MS (0 << 0) +#define DP_AG_FACTOR_2MS (1 << 0) +#define DP_AG_FACTOR_1MS (2 << 0) +#define DP_AG_FACTOR_500US (3 << 0) +#define DP_AG_FACTOR_200US (4 << 0) +#define DP_AG_FACTOR_100US (5 << 0) +#define DP_AG_FACTOR_10US (6 << 0) +#define DP_AG_FACTOR_1US (7 << 0) +#define DP_VG_FACTOR_MASK (0xf << 4) +#define DP_VG_FACTOR_3MS (0 << 4) +#define DP_VG_FACTOR_2MS (1 << 4) +#define DP_VG_FACTOR_1MS (2 << 4) +#define DP_VG_FACTOR_500US (3 << 4) +#define DP_VG_FACTOR_200US (4 << 4) +#define DP_VG_FACTOR_100US (5 << 4) + +#define DP_AUD_DEC_LAT0 0x024 +#define DP_AUD_DEC_LAT1 0x025 + +#define DP_AUD_PP_LAT0 0x026 +#define DP_AUD_PP_LAT1 0x027 + +#define DP_VID_INTER_LAT 0x028 + +#define DP_VID_PROG_LAT 0x029 + +#define DP_REP_LAT 0x02a + +#define DP_AUD_DEL_INS0 0x02b +#define DP_AUD_DEL_INS1 0x02c +#define DP_AUD_DEL_INS2 0x02d +/* End of AV_SYNC_DATA_BLOCK */ + +#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ +#define DP_ALPM_CAP (1 << 0) + +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ +#define DP_AUX_FRAME_SYNC_CAP (1 << 0) + +#define DP_GUID 0x030 /* 1.2 */ + +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ +#define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) + +#define DP_DSC_REV 0x061 +#define DP_DSC_MAJOR_MASK (0xf << 0) +#define DP_DSC_MINOR_MASK (0xf << 4) +#define DP_DSC_MAJOR_SHIFT 0 +#define DP_DSC_MINOR_SHIFT 4 + +#define DP_DSC_RC_BUF_BLK_SIZE 0x062 +#define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 +#define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 +#define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 +#define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 + +#define DP_DSC_RC_BUF_SIZE 0x063 + +#define DP_DSC_SLICE_CAP_1 0x064 +#define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) +#define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) +#define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) +#define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) +#define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) +#define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) +#define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) + +#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 +#define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) +#define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 +#define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 +#define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 +#define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 +#define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 +#define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 +#define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 +#define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 +#define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 + +#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 +#define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) + +#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ + +#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ +#define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) +#define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 + +#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 +#define DP_DSC_RGB (1 << 0) +#define DP_DSC_YCbCr444 (1 << 1) +#define DP_DSC_YCbCr422_Simple (1 << 2) +#define DP_DSC_YCbCr422_Native (1 << 3) +#define DP_DSC_YCbCr420_Native (1 << 4) + +#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A +#define DP_DSC_8_BPC (1 << 1) +#define DP_DSC_10_BPC (1 << 2) +#define DP_DSC_12_BPC (1 << 3) + +#define DP_DSC_PEAK_THROUGHPUT 0x06B +#define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) +#define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 +#define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 +#define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) +#define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ +#define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) +#define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 +#define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0 +#define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) +#define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4) + +#define DP_DSC_MAX_SLICE_WIDTH 0x06C +#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560 +#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 + +#define DP_DSC_SLICE_CAP_2 0x06D +#define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) +#define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) +#define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) + +#define DP_DSC_BITS_PER_PIXEL_INC 0x06F +#define DP_DSC_BITS_PER_PIXEL_1_16 0x0 +#define DP_DSC_BITS_PER_PIXEL_1_8 0x1 +#define DP_DSC_BITS_PER_PIXEL_1_4 0x2 +#define DP_DSC_BITS_PER_PIXEL_1_2 0x3 +#define DP_DSC_BITS_PER_PIXEL_1 0x4 + +#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ +#define DP_PSR_IS_SUPPORTED 1 +#define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ +#define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ + +#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ +#define DP_PSR_NO_TRAIN_ON_EXIT 1 +#define DP_PSR_SETUP_TIME_330 (0 << 1) +#define DP_PSR_SETUP_TIME_275 (1 << 1) +#define DP_PSR_SETUP_TIME_220 (2 << 1) +#define DP_PSR_SETUP_TIME_165 (3 << 1) +#define DP_PSR_SETUP_TIME_110 (4 << 1) +#define DP_PSR_SETUP_TIME_55 (5 << 1) +#define DP_PSR_SETUP_TIME_0 (6 << 1) +#define DP_PSR_SETUP_TIME_MASK (7 << 1) +#define DP_PSR_SETUP_TIME_SHIFT 1 +#define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ +#define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ + +#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ +#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ + +/* + * 0x80-0x8f describe downstream port capabilities, but there are two layouts + * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, + * each port's descriptor is one byte wide. If it was set, each port's is + * four bytes wide, starting with the one byte from the base info. As of + * DP interop v1.1a only VGA defines additional detail. + */ + +/* offset 0 */ +#define DP_DOWNSTREAM_PORT_0 0x80 +#define DP_DS_PORT_TYPE_MASK (7 << 0) +#define DP_DS_PORT_TYPE_DP 0 +#define DP_DS_PORT_TYPE_VGA 1 +#define DP_DS_PORT_TYPE_DVI 2 +#define DP_DS_PORT_TYPE_HDMI 3 +#define DP_DS_PORT_TYPE_NON_EDID 4 +#define DP_DS_PORT_TYPE_DP_DUALMODE 5 +#define DP_DS_PORT_TYPE_WIRELESS 6 +#define DP_DS_PORT_HPD (1 << 3) +/* offset 1 for VGA is maximum megapixels per second / 8 */ +/* offset 2 */ +#define DP_DS_MAX_BPC_MASK (3 << 0) +#define DP_DS_8BPC 0 +#define DP_DS_10BPC 1 +#define DP_DS_12BPC 2 +#define DP_DS_16BPC 3 + +#define DP_MAX_DOWNSTREAM_PORTS 0x10 + +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY 0x090 /* 1.4 */ +#define DP_FEC_CAPABLE (1 << 0) +#define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +#define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) +#define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) + +/* DP Extended DSC Capabilities */ +#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */ +#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 +#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 + +/* link configuration */ +#define DP_LINK_BW_SET 0x100 +#define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ +#define DP_LINK_BW_1_62 0x06 +#define DP_LINK_BW_2_7 0x0a +#define DP_LINK_BW_5_4 0x14 /* 1.2 */ +#define DP_LINK_BW_8_1 0x1e /* 1.4 */ + +#define DP_LANE_COUNT_SET 0x101 +#define DP_LANE_COUNT_MASK 0x0f +#define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) + +#define DP_TRAINING_PATTERN_SET 0x102 +#define DP_TRAINING_PATTERN_DISABLE 0 +#define DP_TRAINING_PATTERN_1 1 +#define DP_TRAINING_PATTERN_2 2 +#define DP_TRAINING_PATTERN_3 3 /* 1.2 */ +#define DP_TRAINING_PATTERN_4 7 /* 1.4 */ +#define DP_TRAINING_PATTERN_MASK 0x3 +#define DP_TRAINING_PATTERN_MASK_1_4 0xf + +/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ +#define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) +#define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) +#define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) +#define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) +#define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) + +#define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) +#define DP_LINK_SCRAMBLING_DISABLE (1 << 5) + +#define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) +#define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) +#define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) +#define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +#define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +#define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) +#define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) +#define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) +#define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) + +#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +#define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) +#define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) +#define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) +#define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) + +#define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) + +#define DP_DOWNSPREAD_CTRL 0x107 +#define DP_SPREAD_AMP_0_5 (1 << 4) +#define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ + +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +#define DP_SET_ANSI_8B10B (1 << 0) + +#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ +/* bitmask as for DP_I2C_SPEED_CAP */ + +#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ +#define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) +#define DP_FRAMING_CHANGE_ENABLE (1 << 1) +#define DP_PANEL_SELF_TEST_ENABLE (1 << 7) + +#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ +#define DP_LINK_QUAL_LANE1_SET 0x10c +#define DP_LINK_QUAL_LANE2_SET 0x10d +#define DP_LINK_QUAL_LANE3_SET 0x10e +#define DP_LINK_QUAL_PATTERN_DISABLE 0 +#define DP_LINK_QUAL_PATTERN_D10_2 1 +#define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 +#define DP_LINK_QUAL_PATTERN_PRBS7 3 +#define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 +#define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 +#define DP_LINK_QUAL_PATTERN_MASK 7 + +#define DP_TRAINING_LANE0_1_SET2 0x10f +#define DP_TRAINING_LANE2_3_SET2 0x110 +#define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) +#define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) +#define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) +#define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) + +#define DP_MSTM_CTRL 0x111 /* 1.2 */ +#define DP_MST_EN (1 << 0) +#define DP_UP_REQ_EN (1 << 1) +#define DP_UPSTREAM_IS_SRC (1 << 2) + +#define DP_AUDIO_DELAY0 0x112 /* 1.2 */ +#define DP_AUDIO_DELAY1 0x113 +#define DP_AUDIO_DELAY2 0x114 + +#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ +#define DP_LINK_RATE_SET_SHIFT 0 +#define DP_LINK_RATE_SET_MASK (7 << 0) + +#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ +#define DP_ALPM_ENABLE (1 << 0) +#define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) + +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ +#define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) +#define DP_IRQ_HPD_ENABLE (1 << 1) + +#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ +#define DP_PWR_NOT_NEEDED (1 << 0) + +#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ +#define DP_FEC_READY (1 << 0) +#define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) +#define DP_FEC_ERR_COUNT_DIS (0 << 1) +#define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +#define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +#define DP_FEC_BIT_ERROR_COUNT (3 << 1) +#define DP_FEC_LANE_SELECT_MASK (3 << 4) +#define DP_FEC_LANE_0_SELECT (0 << 4) +#define DP_FEC_LANE_1_SELECT (1 << 4) +#define DP_FEC_LANE_2_SELECT (2 << 4) +#define DP_FEC_LANE_3_SELECT (3 << 4) + +#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ +#define DP_AUX_FRAME_SYNC_VALID (1 << 0) + +#define DP_DSC_ENABLE 0x160 /* DP 1.4 */ +#define DP_DECOMPRESSION_EN (1 << 0) + +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ +#define DP_PSR_ENABLE (1 << 0) +#define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) +#define DP_PSR_CRC_VERIFICATION (1 << 2) +#define DP_PSR_FRAME_CAPTURE (1 << 3) +#define DP_PSR_SELECTIVE_UPDATE (1 << 4) +#define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) +#define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ + +#define DP_ADAPTER_CTRL 0x1a0 +#define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) + +#define DP_BRANCH_DEVICE_CTRL 0x1a1 +#define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) + +#define DP_PAYLOAD_ALLOCATE_SET 0x1c0 +#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 +#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 + +#define DP_SINK_COUNT 0x200 +/* prior to 1.2 bit 7 was reserved mbz */ +#define DP_GET_SINK_COUNT(x) ((((x)&0x80) >> 1) | ((x)&0x3f)) +#define DP_SINK_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +#define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) +#define DP_AUTOMATED_TEST_REQUEST (1 << 1) +#define DP_CP_IRQ (1 << 2) +#define DP_MCCS_IRQ (1 << 3) +#define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ +#define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ +#define DP_SINK_SPECIFIC_IRQ (1 << 6) + +#define DP_LANE0_1_STATUS 0x202 +#define DP_LANE2_3_STATUS 0x203 +#define DP_LANE_CR_DONE (1 << 0) +#define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +#define DP_LANE_SYMBOL_LOCKED (1 << 2) + +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ + DP_LANE_CHANNEL_EQ_DONE | \ + DP_LANE_SYMBOL_LOCKED) + +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 + +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) + +#define DP_SINK_STATUS 0x205 + +#define DP_RECEIVE_PORT_0_STATUS (1 << 0) +#define DP_RECEIVE_PORT_1_STATUS (1 << 1) + +#define DP_ADJUST_REQUEST_LANE0_1 0x206 +#define DP_ADJUST_REQUEST_LANE2_3 0x207 +#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 +#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 +#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c +#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 +#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 +#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 +#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 +#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 + +#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c +#define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03 +#define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0 +#define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c +#define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2 +#define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30 +#define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4 +#define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0 +#define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6 + +#define DP_TEST_REQUEST 0x218 +#define DP_TEST_LINK_TRAINING (1 << 0) +#define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) +#define DP_TEST_LINK_EDID_READ (1 << 2) +#define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +#define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ +#define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */ +#define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */ + +#define DP_TEST_LINK_RATE 0x219 +#define DP_LINK_RATE_162 (0x6) +#define DP_LINK_RATE_27 (0xa) + +#define DP_TEST_LANE_COUNT 0x220 + +#define DP_TEST_PATTERN 0x221 +#define DP_NO_TEST_PATTERN 0x0 +#define DP_COLOR_RAMP 0x1 +#define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 +#define DP_COLOR_SQUARE 0x3 + +#define DP_TEST_H_TOTAL_HI 0x222 +#define DP_TEST_H_TOTAL_LO 0x223 + +#define DP_TEST_V_TOTAL_HI 0x224 +#define DP_TEST_V_TOTAL_LO 0x225 + +#define DP_TEST_H_START_HI 0x226 +#define DP_TEST_H_START_LO 0x227 + +#define DP_TEST_V_START_HI 0x228 +#define DP_TEST_V_START_LO 0x229 + +#define DP_TEST_HSYNC_HI 0x22A +#define DP_TEST_HSYNC_POLARITY (1 << 7) +#define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) +#define DP_TEST_HSYNC_WIDTH_LO 0x22B + +#define DP_TEST_VSYNC_HI 0x22C +#define DP_TEST_VSYNC_POLARITY (1 << 7) +#define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) +#define DP_TEST_VSYNC_WIDTH_LO 0x22D + +#define DP_TEST_H_WIDTH_HI 0x22E +#define DP_TEST_H_WIDTH_LO 0x22F + +#define DP_TEST_V_HEIGHT_HI 0x230 +#define DP_TEST_V_HEIGHT_LO 0x231 + +#define DP_TEST_MISC0 0x232 +#define DP_TEST_SYNC_CLOCK (1 << 0) +#define DP_TEST_COLOR_FORMAT_MASK (3 << 1) +#define DP_TEST_COLOR_FORMAT_SHIFT 1 +#define DP_COLOR_FORMAT_RGB (0 << 1) +#define DP_COLOR_FORMAT_YCbCr422 (1 << 1) +#define DP_COLOR_FORMAT_YCbCr444 (2 << 1) +#define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3) +#define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) +#define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) +#define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) +#define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) +#define DP_TEST_BIT_DEPTH_MASK (7 << 5) +#define DP_TEST_BIT_DEPTH_SHIFT 5 +#define DP_TEST_BIT_DEPTH_6 (0 << 5) +#define DP_TEST_BIT_DEPTH_8 (1 << 5) +#define DP_TEST_BIT_DEPTH_10 (2 << 5) +#define DP_TEST_BIT_DEPTH_12 (3 << 5) +#define DP_TEST_BIT_DEPTH_16 (4 << 5) + +#define DP_TEST_MISC1 0x233 +#define DP_TEST_REFRESH_DENOMINATOR (1 << 0) +#define DP_TEST_INTERLACED (1 << 1) + +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 + +#define DP_TEST_MISC0 0x232 + +#define DP_TEST_CRC_R_CR 0x240 +#define DP_TEST_CRC_G_Y 0x242 +#define DP_TEST_CRC_B_CB 0x244 + +#define DP_TEST_SINK_MISC 0x246 +#define DP_TEST_CRC_SUPPORTED (1 << 5) +#define DP_TEST_COUNT_MASK 0xf + +#define DP_PHY_TEST_PATTERN 0x248 +#define DP_PHY_TEST_PATTERN_SEL_MASK 0x7 +#define DP_PHY_TEST_PATTERN_NONE 0x0 +#define DP_PHY_TEST_PATTERN_D10_2 0x1 +#define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 +#define DP_PHY_TEST_PATTERN_PRBS7 0x3 +#define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 +#define DP_PHY_TEST_PATTERN_CP2520 0x5 + +#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A +#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 +#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 +#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 +#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 +#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 +#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 +#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 +#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 +#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 +#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 + +#define DP_TEST_RESPONSE 0x260 +#define DP_TEST_ACK (1 << 0) +#define DP_TEST_NAK (1 << 1) +#define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_TEST_EDID_CHECKSUM 0x261 + +#define DP_TEST_SINK 0x270 +#define DP_TEST_SINK_START (1 << 0) +#define DP_TEST_AUDIO_MODE 0x271 +#define DP_TEST_AUDIO_PATTERN_TYPE 0x272 +#define DP_TEST_AUDIO_PERIOD_CH1 0x273 +#define DP_TEST_AUDIO_PERIOD_CH2 0x274 +#define DP_TEST_AUDIO_PERIOD_CH3 0x275 +#define DP_TEST_AUDIO_PERIOD_CH4 0x276 +#define DP_TEST_AUDIO_PERIOD_CH5 0x277 +#define DP_TEST_AUDIO_PERIOD_CH6 0x278 +#define DP_TEST_AUDIO_PERIOD_CH7 0x279 +#define DP_TEST_AUDIO_PERIOD_CH8 0x27A + +#define DP_FEC_STATUS 0x280 /* 1.4 */ +#define DP_FEC_DECODE_EN_DETECTED (1 << 0) +#define DP_FEC_DECODE_DIS_DETECTED (1 << 1) + +#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ + +#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ +#define DP_FEC_ERROR_COUNT_MASK 0x7F +#define DP_FEC_ERR_COUNT_VALID (1 << 7) + +#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ +#define DP_PAYLOAD_TABLE_UPDATED (1 << 0) +#define DP_PAYLOAD_ACT_HANDLED (1 << 1) + +#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ +/* up to ID_SLOT_63 at 0x2ff */ + +#define DP_SOURCE_OUI 0x300 +#define DP_SINK_OUI 0x400 +#define DP_BRANCH_OUI 0x500 +#define DP_BRANCH_ID 0x503 +#define DP_BRANCH_REVISION_START 0x509 +#define DP_BRANCH_HW_REV 0x509 +#define DP_BRANCH_SW_REV 0x50A + +#define DP_SET_POWER 0x600 +#define DP_SET_POWER_D0 0x1 +#define DP_SET_POWER_D3 0x2 +#define DP_SET_POWER_MASK 0x3 +#define DP_SET_POWER_D3_AUX_ON 0x5 + +#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ +#define DP_EDP_11 0x00 +#define DP_EDP_12 0x01 +#define DP_EDP_13 0x02 +#define DP_EDP_14 0x03 +#define DP_EDP_14a 0x04 /* eDP 1.4a */ +#define DP_EDP_14b 0x05 /* eDP 1.4b */ + +#define DP_EDP_GENERAL_CAP_1 0x701 +#define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) +#define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) +#define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) +#define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) +#define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) +#define DP_EDP_FRC_ENABLE_CAP (1 << 5) +#define DP_EDP_COLOR_ENGINE_CAP (1 << 6) +#define DP_EDP_SET_POWER_CAP (1 << 7) + +#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 +#define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) +#define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) +#define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) +#define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) +#define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) +#define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) +#define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) +#define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) + +#define DP_EDP_GENERAL_CAP_2 0x703 +#define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) + +#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ +#define DP_EDP_X_REGION_CAP_MASK (0xf << 0) +#define DP_EDP_X_REGION_CAP_SHIFT 0 +#define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) +#define DP_EDP_Y_REGION_CAP_SHIFT 4 + +#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 +#define DP_EDP_BACKLIGHT_ENABLE (1 << 0) +#define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) +#define DP_EDP_FRC_ENABLE (1 << 2) +#define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) +#define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) + +#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 +#define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) +#define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) +#define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) +#define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) +#define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) +#define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) +#define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) +#define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) +#define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) +#define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ + +#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 +#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 + +#define DP_EDP_PWMGEN_BIT_COUNT 0x724 +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 +#define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) + +#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 + +#define DP_EDP_BACKLIGHT_FREQ_SET 0x728 +#define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 + +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c + +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f + +#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 +#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 + +#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ +#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ + +#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ + +#define DP_SINK_COUNT_ESI 0x2enum port /* 0-5 sink count */ +#define DP_SINK_COUNT_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ +#define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) +#define DP_LOCK_ACQUISITION_REQUEST (1 << 1) +#define DP_CEC_IRQ (1 << 2) + +#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ + +#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ +#define DP_PSR_LINK_CRC_ERROR (1 << 0) +#define DP_PSR_RFB_STORAGE_ERROR (1 << 1) +#define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ + +#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ +#define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ +#define DP_PSR_SINK_INACTIVE 0 +#define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +#define DP_PSR_SINK_ACTIVE_RFB 2 +#define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +#define DP_PSR_SINK_ACTIVE_RESYNC 4 +#define DP_PSR_SINK_INTERNAL_ERROR 7 +#define DP_PSR_SINK_STATE_MASK 0x07 + +#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ +#define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) +#define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 +#define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) +#define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 + +#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ +#define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ +#define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ +#define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ +#define DP_SU_VALID (1 << 3) /* eDP 1.4 */ +#define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ +#define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ +#define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ + +#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ +#define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) + +#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ +#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ +#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ + +#define DP_DP13_DPCD_REV 0x2200 +#define DP_DP13_MAX_LINK_RATE 0x2201 + +#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ +#define DP_GTC_CAP (1 << 0) /* DP 1.3 */ +#define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ +#define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ +#define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ +#define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ +#define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ +#define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ +#define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ + +/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ +#define DP_CEC_TUNNELING_CAPABILITY 0x3000 +#define DP_CEC_TUNNELING_CAPABLE (1 << 0) +#define DP_CEC_SNOOPING_CAPABLE (1 << 1) +#define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) + +#define DP_CEC_TUNNELING_CONTROL 0x3001 +#define DP_CEC_TUNNELING_ENABLE (1 << 0) +#define DP_CEC_SNOOPING_ENABLE (1 << 1) + +#define DP_CEC_RX_MESSAGE_INFO 0x3002 +#define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) +#define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 +#define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) +#define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) +#define DP_CEC_RX_MESSAGE_ACKED (1 << 6) +#define DP_CEC_RX_MESSAGE_ENDED (1 << 7) + +#define DP_CEC_TX_MESSAGE_INFO 0x3003 +#define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) +#define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 +#define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) +#define DP_CEC_TX_RETRY_COUNT_SHIFT 4 +#define DP_CEC_TX_MESSAGE_SEND (1 << 7) + +#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 +#define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) +#define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) +#define DP_CEC_TX_MESSAGE_SENT (1 << 4) +#define DP_CEC_TX_LINE_ERROR (1 << 5) +#define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) +#define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) + +#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ +#define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) +#define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) +#define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) +#define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) +#define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) +#define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) +#define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) +#define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) +#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ +#define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) +#define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) +#define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) +#define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) +#define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) +#define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) +#define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) +#define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) + +#define DP_CEC_RX_MESSAGE_BUFFER 0x3010 +#define DP_CEC_TX_MESSAGE_BUFFER 0x3020 +#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 + +#define DP_AUX_HDCP_BKSV 0x68000 +#define DP_AUX_HDCP_RI_PRIME 0x68005 +#define DP_AUX_HDCP_AKSV 0x68007 +#define DP_AUX_HDCP_AN 0x6800C +#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) +#define DP_AUX_HDCP_BCAPS 0x68028 +#define DP_BCAPS_REPEATER_PRESENT BIT(1) +#define DP_BCAPS_HDCP_CAPABLE BIT(0) +#define DP_AUX_HDCP_BSTATUS 0x68029 +#define DP_BSTATUS_REAUTH_REQ BIT(3) +#define DP_BSTATUS_LINK_FAILURE BIT(2) +#define DP_BSTATUS_R0_PRIME_READY BIT(1) +#define DP_BSTATUS_READY BIT(0) +#define DP_AUX_HDCP_BINFO 0x6802A +#define DP_AUX_HDCP_KSV_FIFO 0x6802C +#define DP_AUX_HDCP_AINFO 0x6803B + +/* DP HDCP2.2 parameter offsets in DPCD address space */ +#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 +#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 +#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B +#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 +#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D +#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 +#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 +#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 +#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 +#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 +#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 +#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 +#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 +#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 +#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 +#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 +#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 +#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 +#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 +#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 +#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 +#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 +#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 +#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 +#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 +#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 + +/* Link Training (LT)-tunable PHY Repeaters */ +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ +#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ +#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ +#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ +#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */ +#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */ + +/* Repeater modes */ +#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ +#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ + +/* DP HDCP message start offsets in DPCD address space */ +#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET +#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET +#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET +#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET +#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET +#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ + DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET +#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET +#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET +#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET +#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET +#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET +#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET +#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET + +#define HDCP_2_2_DP_RXSTATUS_LEN 1 +#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x)&BIT(0)) +#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x)&BIT(1)) +#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x)&BIT(2)) +#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x)&BIT(3)) +#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x)&BIT(4)) + +/* DP 1.2 Sideband message defines */ +/* peer device type - DP 1.2a Table 2-92 */ +#define DP_PEER_DEVICE_NONE 0x0 +#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 +#define DP_PEER_DEVICE_MST_BRANCHING 0x2 +#define DP_PEER_DEVICE_SST_SINK 0x3 +#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 + +/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ +#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */ +#define DP_LINK_ADDRESS 0x01 +#define DP_CONNECTION_STATUS_NOTIFY 0x02 +#define DP_ENUM_PATH_RESOURCES 0x10 +#define DP_ALLOCATE_PAYLOAD 0x11 +#define DP_QUERY_PAYLOAD 0x12 +#define DP_RESOURCE_STATUS_NOTIFY 0x13 +#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 +#define DP_REMOTE_DPCD_READ 0x20 +#define DP_REMOTE_DPCD_WRITE 0x21 +#define DP_REMOTE_I2C_READ 0x22 +#define DP_REMOTE_I2C_WRITE 0x23 +#define DP_POWER_UP_PHY 0x24 +#define DP_POWER_DOWN_PHY 0x25 +#define DP_SINK_EVENT_NOTIFY 0x30 +#define DP_QUERY_STREAM_ENC_STATUS 0x38 + +/* DP 1.2 MST sideband reply types */ +#define DP_SIDEBAND_REPLY_ACK 0x00 +#define DP_SIDEBAND_REPLY_NAK 0x01 + +/* DP 1.2 MST sideband nak reasons - table 2.84 */ +#define DP_NAK_WRITE_FAILURE 0x01 +#define DP_NAK_INVALID_READ 0x02 +#define DP_NAK_CRC_FAILURE 0x03 +#define DP_NAK_BAD_PARAM 0x04 +#define DP_NAK_DEFER 0x05 +#define DP_NAK_LINK_FAILURE 0x06 +#define DP_NAK_NO_RESOURCES 0x07 +#define DP_NAK_DPCD_FAIL 0x08 +#define DP_NAK_I2C_NAK 0x09 +#define DP_NAK_ALLOCATE_FAIL 0x0a + +#define MODE_I2C_START 1 +#define MODE_I2C_WRITE 2 +#define MODE_I2C_READ 4 +#define MODE_I2C_STOP 8 + +/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ +#define DP_MST_PHYSICAL_PORT_0 0 +#define DP_MST_LOGICAL_PORT_0 8 + +#define DP_LINK_STATUS_SIZE 6 + +#define DP_BRANCH_OUI_HEADER_SIZE 0xc +#define DP_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE 0xf +#define EDP_PSR_RECEIVER_CAP_SIZE 2 +#define EDP_DISPLAY_CTL_CAP_SIZE 3 + +#define DP_SDP_AUDIO_TIMESTAMP 0x01 +#define DP_SDP_AUDIO_STREAM 0x02 +#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ +#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ +#define DP_SDP_ISRC 0x06 /* DP 1.2 */ +#define DP_SDP_VSC 0x07 /* DP 1.2 */ +#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ +#define DP_SDP_PPS 0x10 /* DP 1.4 */ +#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ +#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ +/* 0x80+ CEA-861 infoframe types */ + +/** + * struct dp_sdp_header - DP secondary data packet header + * @HB0: Secondary Data Packet ID + * @HB1: Secondary Data Packet Type + * @HB2: Secondary Data Packet Specific header, Byte 0 + * @HB3: Secondary Data packet Specific header, Byte 1 + */ + +#define EDP_SDP_HEADER_REVISION_MASK 0x1F +#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F +#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F + +#define EDP_VSC_PSR_STATE_ACTIVE (1 << 0) +#define EDP_VSC_PSR_UPDATE_RFB (1 << 1) +#define EDP_VSC_PSR_CRC_VALUES_VALID (1 << 2) + +/** + * enum dp_pixelformat - drm DP Pixel encoding formats + * + * This enum is used to indicate DP VSC SDP Pixel encoding formats. + * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through + * DB18] + * + * @DP_PIXELFORMAT_RGB: RGB pixel encoding format + * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format + * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format + * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format + * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format + * @DP_PIXELFORMAT_RAW: RAW pixel encoding format + * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format + */ +enum dp_pixelformat +{ + DP_PIXELFORMAT_RGB = 0, + DP_PIXELFORMAT_YUV444 = 0x1, + DP_PIXELFORMAT_YUV422 = 0x2, + DP_PIXELFORMAT_YUV420 = 0x3, + DP_PIXELFORMAT_Y_ONLY = 0x4, + DP_PIXELFORMAT_RAW = 0x5, + DP_PIXELFORMAT_RESERVED = 0x6, +}; + +/** + * enum dp_colorimetry - drm DP Colorimetry formats + * + * This enum is used to indicate DP VSC SDP Colorimetry formats. + * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through + * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition. + * + * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or + * ITU-R BT.601 colorimetry format + * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format + * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format + * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point + * (scRGB (IEC 61966-2-2)) colorimetry format + * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format + * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format + * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format + * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format + * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format + * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format + * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format + * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format + * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format + * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format + */ +enum dp_colorimetry +{ + DP_COLORIMETRY_DEFAULT = 0, + DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1, + DP_COLORIMETRY_BT709_YCC = 0x1, + DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2, + DP_COLORIMETRY_XVYCC_601 = 0x2, + DP_COLORIMETRY_OPRGB = 0x3, + DP_COLORIMETRY_XVYCC_709 = 0x3, + DP_COLORIMETRY_DCI_P3_RGB = 0x4, + DP_COLORIMETRY_SYCC_601 = 0x4, + DP_COLORIMETRY_RGB_CUSTOM = 0x5, + DP_COLORIMETRY_OPYCC_601 = 0x5, + DP_COLORIMETRY_BT2020_RGB = 0x6, + DP_COLORIMETRY_BT2020_CYCC = 0x6, + DP_COLORIMETRY_BT2020_YCC = 0x7, +}; + +/** + * enum dp_dynamic_range - drm DP Dynamic Range + * + * This enum is used to indicate DP VSC SDP Dynamic Range. + * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through + * DB18] + * + * @DP_DYNAMIC_RANGE_VESA: VESA range + * @DP_DYNAMIC_RANGE_CTA: CTA range + */ +enum dp_dynamic_range +{ + DP_DYNAMIC_RANGE_VESA = 0, + DP_DYNAMIC_RANGE_CTA = 1, +}; + +/** + * enum dp_content_type - drm DP Content Type + * + * This enum is used to indicate DP VSC SDP Content Types. + * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through + * DB18] + * CTA-861-G defines content types and expected processing by a sink device + * + * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type + * @DP_CONTENT_TYPE_GRAPHICS: Graphics type + * @DP_CONTENT_TYPE_PHOTO: Photo type + * @DP_CONTENT_TYPE_VIDEO: Video type + * @DP_CONTENT_TYPE_GAME: Game type + */ +enum dp_content_type +{ + DP_CONTENT_TYPE_NOT_DEFINED = 0x00, + DP_CONTENT_TYPE_GRAPHICS = 0x01, + DP_CONTENT_TYPE_PHOTO = 0x02, + DP_CONTENT_TYPE_VIDEO = 0x03, + DP_CONTENT_TYPE_GAME = 0x04, +}; + +/** + * struct drm_dp_vsc_sdp - drm DP VSC SDP + * + * This structure represents a DP VSC SDP of drm + * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and + * [Table 2-117: VSC SDP Payload for DB16 through DB18] + * + * @sdp_type: secondary-data packet type + * @revision: revision number + * @length: number of valid data bytes + * @pixelformat: pixel encoding format + * @colorimetry: colorimetry format + * @bpc: bit per color + * @dynamic_range: dynamic range information + * @content_type: CTA-861-G defines content types and expected processing by a sink device + */ +struct drm_dp_vsc_sdp +{ + unsigned char sdp_type; + unsigned char revision; + unsigned char length; + enum dp_pixelformat pixelformat; + enum dp_colorimetry colorimetry; + int bpc; + enum dp_dynamic_range dynamic_range; + enum dp_content_type content_type; +}; + +struct link_config_limits +{ + int min_clock, max_clock; + int min_lane_count, max_lane_count; + int min_bpp, max_bpp; +}; + +struct intel_dp +{ + UINT8 lane_count; + UINT8 train_set[4]; + UINT8 pipe_bpp; + int link_rate; + i915_CONTROLLER *controller; + bool use_max_rate; + /* source rates */ + int num_source_rates; + const int *source_rates; + /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ + int num_sink_rates; + int sink_rates[DP_MAX_SUPPORTED_RATES]; + //BOOLEAN use_rate_select; + /* intersection of source and sink rates */ + int num_common_rates; + int common_rates[DP_MAX_SUPPORTED_RATES]; + /* Max lane count for the current link */ + int max_link_lane_count; + /* Max rate for the current link */ + int max_link_rate; + int panel_power_up_delay; + int panel_power_down_delay; + int panel_power_cycle_delay; + int backlight_on_delay; + int backlight_off_delay; + //struct delayed_work panel_vdd_work; + bool want_panel_vdd; + unsigned long last_power_on; + unsigned long last_backlight_off; + //ktime_t panel_power_off_time; + struct edp_power_seq pps_delays; +}; +EFI_STATUS SetupClockeDP(i915_CONTROLLER *controller); +EFI_STATUS SetupClockDP(i915_CONTROLLER *controller); +EFI_STATUS SetupDDIBufferDP(i915_CONTROLLER *controller); +EFI_STATUS SetupTranscoderAndPipeEDP(i915_CONTROLLER *controller); +EFI_STATUS SetupTranscoderAndPipeDP(i915_CONTROLLER *controller); +void intel_dp_pps_init(i915_CONTROLLER *controller); +EFI_STATUS ReadEDIDDP(EDID *result, i915_CONTROLLER *controller, UINT8 pin); +EFI_STATUS SetupPPS(i915_CONTROLLER *controller); +#endif \ No newline at end of file diff --git a/i915_gmbus.c b/i915_gmbus.c new file mode 100644 index 0000000..13393c7 --- /dev/null +++ b/i915_gmbus.c @@ -0,0 +1,33 @@ +#include +#include "i915_gmbus.h" +#include "i915_debug.h" +#include + +EFI_STATUS gmbusWait(i915_CONTROLLER *controller, UINT32 wanted) +{ + UINTN counter = 0; + + for (;;) + { + UINT32 status = controller->read32(gmbusStatus); + counter += 1; + if (counter >= 100) + { + //failed + PRINT_DEBUG(EFI_D_ERROR, "gmbus timeout\n"); + return EFI_DEVICE_ERROR; + } + if (status & GMBUS_SATOER) + { + //failed + PRINT_DEBUG(EFI_D_ERROR, "gmbus error on %d\n", wanted); + return EFI_DEVICE_ERROR; + } + if (status & wanted) + { + //worked + return EFI_SUCCESS; + } + gBS->Stall(100); + } +} \ No newline at end of file diff --git a/i915_gmbus.h b/i915_gmbus.h new file mode 100644 index 0000000..84668bf --- /dev/null +++ b/i915_gmbus.h @@ -0,0 +1,64 @@ +#ifndef i915_GMBUSH +#define i915_GMBUSH +#include "i915_reg.h" +#include "i915_controller.h" + +#define GMBUS0 (PCH_DISPLAY_BASE+0x5100) +#define gmbusSelect (PCH_DISPLAY_BASE+0x5100) +#define GMBUS_AKSV_SELECT (1 << 11) +#define GMBUS_RATE_100KHZ (0 << 8) +#define GMBUS_RATE_50KHZ (1 << 8) +#define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ +#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ +#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ +#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) +#define GMBUS_PIN_DISABLED 0 +#define GMBUS_PIN_SSC 1 +#define GMBUS_PIN_VGADDC 2 +#define GMBUS_PIN_PANEL 3 +#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ +#define GMBUS_PIN_DPC 4 /* HDMIC */ +#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ +#define GMBUS_PIN_DPD 6 /* HDMID */ +#define GMBUS_PIN_RESERVED 7 /* 7 reserved */ +#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */ +#define GMBUS_PIN_2_BXT 2 +#define GMBUS_PIN_3_BXT 3 +#define GMBUS_PIN_4_CNP 4 +#define GMBUS_PIN_9_TC1_ICP 9 +#define GMBUS_PIN_10_TC2_ICP 10 +#define GMBUS_PIN_11_TC3_ICP 11 +#define GMBUS_PIN_12_TC4_ICP 12 +#define GMBUS_PIN_13_TC5_TGP 13 +#define GMBUS_PIN_14_TC6_TGP 14 + +#define gmbusCommand (PCH_DISPLAY_BASE+0x5104) +#define GMBUS_SW_CLR_INT (1 << 31) +#define GMBUS_SW_RDY (1 << 30) +#define GMBUS_ENT (1 << 29) /* enable timeout */ +#define GMBUS_CYCLE_NONE (0 << 25) +#define GMBUS_CYCLE_WAIT (1 << 25) +#define GMBUS_CYCLE_INDEX (2 << 25) +#define GMBUS_CYCLE_STOP (4 << 25) +#define GMBUS_BYTE_COUNT_SHIFT 16 +#define GMBUS_BYTE_COUNT_MAX 256U +#define GEN9_GMBUS_BYTE_COUNT_MAX 511U +#define GMBUS_SLAVE_INDEX_SHIFT 8 +#define GMBUS_SLAVE_ADDR_SHIFT 1 +#define GMBUS_SLAVE_READ (1 << 0) +#define GMBUS_SLAVE_WRITE (0 << 0) + +#define gmbusStatus (PCH_DISPLAY_BASE+0x5108) +#define GMBUS_INUSE (1 << 15) +#define GMBUS_HW_WAIT_PHASE (1 << 14) +#define GMBUS_STALL_TIMEOUT (1 << 13) +#define GMBUS_INT (1 << 12) +#define GMBUS_HW_RDY (1 << 11) +#define GMBUS_SATOER (1 << 10) +#define GMBUS_ACTIVE (1 << 9) + +#define gmbusData (PCH_DISPLAY_BASE+0x510C) +#define GMBUS4 (PCH_DISPLAY_BASE+0x5110) + +EFI_STATUS gmbusWait(i915_CONTROLLER *, UINT32); +#endif \ No newline at end of file diff --git a/i915_gop.c b/i915_gop.c new file mode 100644 index 0000000..a1b7a83 --- /dev/null +++ b/i915_gop.c @@ -0,0 +1,198 @@ +#include "i915_gop.h" + +STATIC EFI_GRAPHICS_OUTPUT_MODE_INFORMATION + g_mode_info[] = { + { + 0, // Version + 1024, // HorizontalResolution + 768, // VerticalResolution + }}; + +STATIC EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE + g_mode = { + ARRAY_SIZE(g_mode_info), // MaxMode + 0, // Mode + g_mode_info, // Info + sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), // SizeOfInfo +}; +STATIC EFI_STATUS + + EFIAPI + i915GraphicsOutputQueryMode( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL + + *This, + IN UINT32 + ModeNumber, + OUT UINTN + *SizeOfInfo, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION + **Info) +{ + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *ModeInfo; + PRINT_DEBUG(EFI_D_ERROR, + "i915: query mode\n"); + + if (Info == NULL || SizeOfInfo == NULL || + ModeNumber >= g_mode.MaxMode) + { + return EFI_INVALID_PARAMETER; + } + ModeInfo = &g_mode_info[ModeNumber]; + + *Info = AllocateCopyPool(sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), ModeInfo); + if (*Info == NULL) + { + return EFI_OUT_OF_RESOURCES; + } + *SizeOfInfo = sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); + + return EFI_SUCCESS; +} + +STATIC FRAME_BUFFER_CONFIGURE + * + g_i915FrameBufferBltConfigure = NULL; +STATIC UINTN + g_i915FrameBufferBltConfigureSize = 0; + +EFI_STATUS i915GraphicsFramebufferConfigure(i915_CONTROLLER *controller) +{ + g_mode.FrameBufferBase = controller->FbBase; + g_mode.FrameBufferSize = controller->fbsize; + + // //test pattern + // //there is just one page wrapping around... why? + // //we have intel_vgpu_mmap in effect so the correct range is mmaped host vmem + // //and the host vmem is actually one-page! + // ((UINT32*)controller->FbBase)[-1]=0x00010203; + // //there is a mechanism called `get_pages` that seems to put main memory behind the aperture or sth + // //the page is the scratch page that unmapped GTT entries point to + // //we need to set up a GTT for our framebuffer: https://bwidawsk.net/blog/index.php/2014/06/the-global-gtt-part-1/ + // UINT32 cnt=0; + // for(cnt=0;cnt<256*16;cnt++){ + // ((UINT32*)controller->FbBase)[cnt]=0x00010203; + // } + // for(cnt=0;cnt<256*4;cnt++){ + // UINT32 c=cnt&255; + // ((UINT32*)controller->FbBase)[cnt]=((cnt+256)&256?c:0)+((cnt+256)&512?c<<8:0)+((cnt+256)&1024?c<<16:0); + // } + // DebugPrint(EFI_D_ERROR,"i915: wrap test %08x %08x %08x %08x\n",((UINT32*)controller->FbBase)[1024],((UINT32*)controller->FbBase)[1025],((UINT32*)controller->FbBase)[1026],((UINT32*)controller->FbBase)[1027]); + // // + // cnt=0; + // for(UINT32 y=0;yFbBase)[cnt]=(data&0xffff00)|0x80; + // cnt++; + // } + // } + // write32(_DSPACNTR,DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888); + + //blt stuff + EFI_STATUS Status; + Status = FrameBufferBltConfigure( + (VOID *)controller->FbBase, + g_mode_info, + g_i915FrameBufferBltConfigure, + &g_i915FrameBufferBltConfigureSize); + + if (Status == RETURN_BUFFER_TOO_SMALL) + { + if (g_i915FrameBufferBltConfigure != NULL) + { + FreePool(g_i915FrameBufferBltConfigure); + } + g_i915FrameBufferBltConfigure = AllocatePool(g_i915FrameBufferBltConfigureSize); + if (g_i915FrameBufferBltConfigure == NULL) + { + g_i915FrameBufferBltConfigureSize = 0; + return EFI_OUT_OF_RESOURCES; + } + + Status = FrameBufferBltConfigure( + (VOID *)controller->FbBase, + g_mode_info, + g_i915FrameBufferBltConfigure, + &g_i915FrameBufferBltConfigureSize); + } + if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR, "failed to setup blt\n"); + } + return EFI_SUCCESS; +} + +STATIC EFI_STATUS + + EFIAPI + i915GraphicsOutputBlt( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL + + *This, + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL + *BltBuffer, + OPTIONAL + IN + EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, + IN + UINTN SourceX, + IN + UINTN SourceY, + IN + UINTN DestinationX, + IN + UINTN DestinationY, + IN + UINTN Width, + IN + UINTN Height, + IN + UINTN Delta) +{ + EFI_STATUS Status = FrameBufferBlt( + g_i915FrameBufferBltConfigure, + BltBuffer, + BltOperation, + SourceX, + SourceY, + DestinationX, + DestinationY, + Width, + Height, + Delta); + //PRINT_DEBUG(EFI_D_ERROR, + //"i915: blt %d %d,%d %dx%d\n",Status,DestinationX,DestinationY,Width,Height); + return Status; +} +STATIC EFI_STATUS + + EFIAPI + i915GraphicsOutputSetMode( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL + + *This, + IN UINT32 + ModeNumber) + +{ + return setDisplayGraphicsMode(ModeNumber); +} + +EFI_STATUS i915GraphicsSetupOutput(EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput, UINT32 x_active, UINT32 y_active) +{ + + g_mode_info[0].HorizontalResolution = x_active; + g_mode_info[0].VerticalResolution = y_active; + g_mode_info[0].PixelsPerScanLine = ((x_active * 4 + 63) & -64) >> 2; + g_mode_info[0].PixelFormat = PixelBlueGreenRedReserved8BitPerColor; + + GraphicsOutput->QueryMode = i915GraphicsOutputQueryMode; + GraphicsOutput->SetMode = i915GraphicsOutputSetMode; + GraphicsOutput->Blt = i915GraphicsOutputBlt; + GraphicsOutput->Mode = &g_mode; + EFI_STATUS stat = GraphicsOutput->SetMode(GraphicsOutput, 0); + PRINT_DEBUG(EFI_D_ERROR, "progressed to gopline %d, status is %u\n", + __LINE__, stat); + return stat; +} \ No newline at end of file diff --git a/i915_gop.h b/i915_gop.h new file mode 100644 index 0000000..483a23d --- /dev/null +++ b/i915_gop.h @@ -0,0 +1,15 @@ +#pragma once +#ifndef i915_GOPH +#define i915_GOPH +#include +#include "i915_display.h" +#include +#include "i915_debug.h" +#include +#include "i915_reg.h" +#include + +EFI_STATUS i915GraphicsFramebufferConfigure(i915_CONTROLLER *controller); + +EFI_STATUS i915GraphicsSetupOutput(EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput, UINT32 x_active, UINT32 y_active); +#endif \ No newline at end of file diff --git a/i915_hdmi.c b/i915_hdmi.c new file mode 100644 index 0000000..f824b74 --- /dev/null +++ b/i915_hdmi.c @@ -0,0 +1,600 @@ +#include "i915_controller.h" +#include "i915_debug.h" +#include "i915_gmbus.h" +#include "i915_ddi.h" +#include "i915_dp.h" +#include "i915_hdmi.h" +#include "i915_reg.h" +#include +#include + +static int intel_hdmi_source_max_tmds_clock() +{ + // struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + int max_tmds_clock; + //, vbt_max_tmds_clock; + + // if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + // max_tmds_clock = 594000; + // else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) + max_tmds_clock = 300000; + // else if (INTEL_GEN(dev_priv) >= 5) + // max_tmds_clock = 225000; + // else + // max_tmds_clock = 165000; + + // vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); + // if (vbt_max_tmds_clock) + // max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); + + return max_tmds_clock; +} +static int hdmi_port_clock_limit() +{ + //struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; + int max_tmds_clock = intel_hdmi_source_max_tmds_clock(); + + return max_tmds_clock; +} +INT32 intel_hdmi_link_required(int pixel_clock, int bpp) +{ + /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ + return DIV_ROUND_UP(pixel_clock * bpp, 8); +} +static BOOLEAN intel_hdmi_valid_link_rate(UINT32 pixelClock) +{ + /* const struct drm_display_mode *fixed_mode = + intel_dp->attached_connector->panel.fixed_mode; */ + int mode_rate, max_rate; + + mode_rate = intel_hdmi_link_required(pixelClock * 10, 8); + max_rate = hdmi_port_clock_limit(); + PRINT_DEBUG(EFI_D_ERROR, "Mode: %u, Max:%u\n", mode_rate, max_rate); + if (mode_rate > max_rate) + return FALSE; + + return TRUE; +} +EFI_STATUS ConvertFallbackEDIDToHDMIEDID(EDID *result, i915_CONTROLLER *controller, UINT8 *fallback) +{ + UINT32 i = 0; + + // it's an INTEL GPU, there's no way we could be big endian + for (i = 0; i < 128; i++) + { + ((UINT8 *)result)[i] = fallback[i]; + } + UINT32 *p = (UINT32 *)result; + // try all the pins on GMBUS + { + // gmbusWait(controller,GMBUS_HW_WAIT_PHASE); + + for (UINT32 i = 0; i < 16; i++) + { + for (UINT32 j = 0; j < 8; j++) + { + DebugPrint(EFI_D_ERROR, "%02x ", ((UINT8 *)(p))[i * 8 + j]); + } + DebugPrint(EFI_D_ERROR, "\n"); + } + if (i >= 128 && *(UINT64 *)result->magic == 0x00FFFFFFFFFFFF00uLL) + { + if (!intel_hdmi_valid_link_rate(result->detailTimings[DETAIL_TIME_SELCTION].pixelClock)) + { + for (int j = 0; j < 4; j++) + { + if (result->detailTimings[j].pixelClock > 0 && intel_hdmi_valid_link_rate(result->detailTimings[j].pixelClock)) + { + result->detailTimings[DETAIL_TIME_SELCTION] = result->detailTimings[j]; + return EFI_SUCCESS; + } + } + PRINT_DEBUG(EFI_D_ERROR, "pixelClock: %d\n", result->detailTimings[DETAIL_TIME_SELCTION].pixelClock); + + for (int j = 0; j < 4; j++) + { + if (result->detailTimings[j].pixelClock >> 1 > 0 && intel_hdmi_valid_link_rate(result->detailTimings[j].pixelClock >> 1)) + { + result->detailTimings[j].pixelClock = result->detailTimings[j].pixelClock >> 1; + result->detailTimings[DETAIL_TIME_SELCTION] = result->detailTimings[j]; + return EFI_SUCCESS; + } + } + PRINT_DEBUG(EFI_D_ERROR, "pixelClock: %d\n", result->detailTimings[DETAIL_TIME_SELCTION].pixelClock); + } + // if (result->detailTimings[DETAIL_TIME_SELCTION].pixelClock > 3) { + // result->detailTimings[DETAIL_TIME_SELCTION].pixelClock >> 1; + // } + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; +} +EFI_STATUS ReadEDIDHDMI(EDID *result, i915_CONTROLLER *controller, UINT8 pin) +{ + // it's an INTEL GPU, there's no way we could be big endian + UINT32 *p = (UINT32 *)result; + // try all the pins on GMBUS + { + PRINT_DEBUG(EFI_D_ERROR, "trying pin %d\n", pin); + controller->write32(gmbusSelect, pin); + if (EFI_ERROR(gmbusWait(controller, GMBUS_HW_RDY))) + { + + return EFI_NOT_FOUND; + } + // set read offset: i2cWrite(0x50, &offset, 1); + controller->write32(gmbusData, 0); + controller->write32(gmbusCommand, (0x50 << GMBUS_SLAVE_ADDR_SHIFT) | + (1 << GMBUS_BYTE_COUNT_SHIFT) | + GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | + GMBUS_SW_RDY); + // gmbusWait(controller,GMBUS_HW_WAIT_PHASE); + gmbusWait(controller, GMBUS_HW_RDY); + PRINT_DEBUG(EFI_D_ERROR, "trying pin %d\n", pin); + + // read the edid: i2cRead(0x50, &edid, 128); + // note that we could fail here! + controller->write32(gmbusCommand, (0x50 << GMBUS_SLAVE_ADDR_SHIFT) | + (128 << GMBUS_BYTE_COUNT_SHIFT) | + GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT | + GMBUS_SW_RDY); + UINT32 i = 0; + for (i = 0; i < 128; i += 4) + { + if (EFI_ERROR(gmbusWait(controller, GMBUS_HW_RDY))) + { + PRINT_DEBUG(EFI_D_ERROR, "trying pin %d\n", pin); + + break; + } + p[i >> 2] = controller->read32(gmbusData); + } + // gmbusWait(controller,GMBUS_HW_WAIT_PHASE); + gmbusWait(controller, GMBUS_HW_RDY); + PRINT_DEBUG(EFI_D_ERROR, "trying pin %d\n", pin); + + for (UINT32 i = 0; i < 16; i++) + { + for (UINT32 j = 0; j < 8; j++) + { + DebugPrint(EFI_D_ERROR, "%02x ", ((UINT8 *)(p))[i * 8 + j]); + } + DebugPrint(EFI_D_ERROR, "\n"); + } + if (i >= 128 && *(UINT64 *)result->magic == 0x00FFFFFFFFFFFF00uLL) + { + if (!intel_hdmi_valid_link_rate(result->detailTimings[DETAIL_TIME_SELCTION].pixelClock)) + { + for (int j = 0; j < 4; j++) + { + if (result->detailTimings[j].pixelClock > 0 && intel_hdmi_valid_link_rate(result->detailTimings[j].pixelClock)) + { + result->detailTimings[DETAIL_TIME_SELCTION] = result->detailTimings[j]; + return EFI_SUCCESS; + } + } + PRINT_DEBUG(EFI_D_ERROR, "pixelClock: %d\n", result->detailTimings[DETAIL_TIME_SELCTION].pixelClock); + + for (int j = 0; j < 4; j++) + { + if (result->detailTimings[j].pixelClock >> 1 > 0 && intel_hdmi_valid_link_rate(result->detailTimings[j].pixelClock >> 1)) + { + result->detailTimings[j].pixelClock = result->detailTimings[j].pixelClock >> 1; + result->detailTimings[DETAIL_TIME_SELCTION] = result->detailTimings[j]; + return EFI_SUCCESS; + } + } + PRINT_DEBUG(EFI_D_ERROR, "pixelClock: %d\n", result->detailTimings[DETAIL_TIME_SELCTION].pixelClock); + } + // if (result->detailTimings[DETAIL_TIME_SELCTION].pixelClock > 3) { + // result->detailTimings[DETAIL_TIME_SELCTION].pixelClock >> 1; + // } + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; +} +static void skl_wrpll_get_multipliers(UINT64 p, + UINT64 *p0 /* out */, + UINT64 *p1 /* out */, + UINT64 *p2 /* out */) +{ + /* even dividers */ + if (p % 2 == 0) + { + UINT64 half = p / 2; + + if (half == 1 || half == 2 || half == 3 || half == 5) + { + *p0 = 2; + *p1 = 1; + *p2 = half; + } + else if (half % 2 == 0) + { + *p0 = 2; + *p1 = half / 2; + *p2 = 2; + } + else if (half % 3 == 0) + { + *p0 = 3; + *p1 = half / 3; + *p2 = 2; + } + else if (half % 7 == 0) + { + *p0 = 7; + *p1 = half / 7; + *p2 = 2; + } + } + else if (p == 3 || p == 9) + { /* 3, 5, 7, 9, 15, 21, 35 */ + *p0 = 3; + *p1 = 1; + *p2 = p / 3; + } + else if (p == 5 || p == 7) + { + *p0 = p; + *p1 = 1; + *p2 = 1; + } + else if (p == 15) + { + *p0 = 3; + *p1 = 1; + *p2 = 5; + } + else if (p == 21) + { + *p0 = 7; + *p1 = 1; + *p2 = 3; + } + else if (p == 35) + { + *p0 = 7; + *p1 = 1; + *p2 = 5; + } +} + +#define KHz(x) (1000 * (x)) +#define MHz(x) KHz(1000 * (x)) + +static void skl_wrpll_params_populate(struct skl_wrpll_params *params, + UINT64 afe_clock, + UINT64 central_freq, + UINT64 p0, UINT64 p1, UINT64 p2) +{ + UINT64 dco_freq; + + switch (central_freq) + { + case 9600000000ULL: + params->central_freq = 0; + break; + case 9000000000ULL: + params->central_freq = 1; + break; + case 8400000000ULL: + params->central_freq = 3; + } + + switch (p0) + { + case 1: + params->pdiv = 0; + break; + case 2: + params->pdiv = 1; + break; + case 3: + params->pdiv = 2; + break; + case 7: + params->pdiv = 4; + break; + default: + PRINT_DEBUG(EFI_D_ERROR, "Incorrect PDiv\n"); + } + + switch (p2) + { + case 5: + params->kdiv = 0; + break; + case 2: + params->kdiv = 1; + break; + case 3: + params->kdiv = 2; + break; + case 1: + params->kdiv = 3; + break; + default: + PRINT_DEBUG(EFI_D_ERROR, "Incorrect KDiv\n"); + } + + params->qdiv_ratio = p1; + params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; + + dco_freq = p0 * p1 * p2 * afe_clock; + + /* + * Intermediate values are in Hz. + * Divide by MHz to match bsepc + */ + params->dco_integer = (dco_freq) / (24 * MHz(1)); + params->dco_fraction = (((dco_freq) / (24) - params->dco_integer * MHz(1)) * 0x8000) / (MHz(1)); +} + +static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, + UINT64 central_freq, + UINT64 dco_freq, + UINT64 divider) +{ + UINT64 deviation; + INT64 abs_diff = (INT64)dco_freq - (INT64)central_freq; + if (abs_diff < 0) + { + abs_diff = -abs_diff; + } + + deviation = (10000 * (UINT64)abs_diff) / (central_freq); + + /* positive deviation */ + if (dco_freq >= central_freq) + { + if (deviation < SKL_DCO_MAX_PDEVIATION && + deviation < ctx->min_deviation) + { + ctx->min_deviation = deviation; + ctx->central_freq = central_freq; + ctx->dco_freq = dco_freq; + ctx->p = divider; + } + /* negative deviation */ + } + else if (deviation < SKL_DCO_MAX_NDEVIATION && + deviation < ctx->min_deviation) + { + ctx->min_deviation = deviation; + ctx->central_freq = central_freq; + ctx->dco_freq = dco_freq; + ctx->p = divider; + } +} + +EFI_STATUS SetupClockHDMI(i915_CONTROLLER *controller) +{ + + UINT32 ctrl1, cfgcr1, cfgcr2; + struct skl_wrpll_params wrpll_params = { + 0, + }; + + /* + * See comment in intel_dpll_hw_state to understand why we always use 0 + * as the DPLL id in this function. Basically, we put them in the first 6 bits then shift them into place for easier comparison + */ + ctrl1 = DPLL_CTRL1_OVERRIDE(0); //Enable Programming + ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); //Set Mode to HDMI + + { + //clock in Hz + UINT64 clock = (UINT64)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock) * 10000; + UINT64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ + UINT64 dco_central_freq[3] = {8400000000ULL, 9000000000ULL, 9600000000ULL}; + + struct skl_wrpll_context ctx = {0}; + UINT64 dco, d, i; + UINT64 p0, p1, p2; + + //Find the DCO, Dividers, and DCO central freq + ctx.min_deviation = 1ULL << 62; + + for (d = 0; d < ARRAY_SIZE(dividers); d++) + { + for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) + { + for (i = 0; i < dividers[d].n_dividers; i++) + { + UINT64 p = dividers[d].list[i]; + UINT64 dco_freq = p * afe_clock; + + skl_wrpll_try_divider(&ctx, + dco_central_freq[dco], + dco_freq, + p); + /* + * Skip the remaining dividers if we're sure to + * have found the definitive divider, we can't + * improve a 0 deviation. + */ + if (ctx.min_deviation == 0) + goto skip_remaining_dividers; + } + } + + skip_remaining_dividers: + /* + * If a solution is found with an even divider, prefer + * this one. + */ + if (d == 0 && ctx.p) + break; + } + + if (!ctx.p) + { + PRINT_DEBUG(EFI_D_ERROR, "No valid divider found for %dHz\n", clock); + return EFI_UNSUPPORTED; + } + + /* + * gcc incorrectly analyses that these can be used without being + * initialized. To be fair, it's hard to guess. + */ + p0 = p1 = p2 = 0; + skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); + skl_wrpll_params_populate(&wrpll_params, afe_clock, ctx.central_freq, + p0, p1, p2); + } + + cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | + DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | + wrpll_params.dco_integer; + + cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | + DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | + DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | + DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | + wrpll_params.central_freq; + + UINT32 val = controller->read32(DPLL_CTRL1); + + //it's clock id! + //how's port clock comptued? + //UINT64 clock_khz=(UINT64)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock)*10; + //UINT32 id=DPLL_CTRL1_LINK_RATE_810; + //if(clock_khz>>1 >=135000){ + // id=DPLL_CTRL1_LINK_RATE_1350; + //}else if(clock_khz>>1 >=270000){ + // id=DPLL_CTRL1_LINK_RATE_2700; + //} + //hack: anything else hangs + UINT32 id = DPLL_CTRL1_LINK_RATE_1350; + + val &= ~(DPLL_CTRL1_HDMI_MODE(id) | + DPLL_CTRL1_SSC(id) | + DPLL_CTRL1_LINK_RATE_MASK(id)); + val |= ctrl1 << (id * 6); + + //DPLL 1 + controller->write32(DPLL_CTRL1, val); + controller->read32(DPLL_CTRL1); + + controller->write32(_DPLL1_CFGCR1, cfgcr1); + controller->write32(_DPLL1_CFGCR2, cfgcr2); + controller->read32(_DPLL1_CFGCR1); + controller->read32(_DPLL1_CFGCR2); + + //845 80400173 3a5 + PRINT_DEBUG(EFI_D_ERROR, "DPLL_CTRL1 = %08x\n", controller->read32(DPLL_CTRL1)); + PRINT_DEBUG(EFI_D_ERROR, "_DPLL1_CFGCR1 = %08x\n", controller->read32(_DPLL1_CFGCR1)); + PRINT_DEBUG(EFI_D_ERROR, "_DPLL1_CFGCR2 = %08x\n", controller->read32(_DPLL1_CFGCR2)); + + /* the enable bit is always bit 31 */ + controller->write32(LCPLL2_CTL, controller->read32(LCPLL2_CTL) | LCPLL_PLL_ENABLE); + + for (UINT32 counter = 0;; counter++) + { + if (controller->read32(DPLL_STATUS) & DPLL_LOCK(1)) + { + PRINT_DEBUG(EFI_D_ERROR, "DPLL %d locked\n", 1); + break; + } + if (counter > 500) + { + PRINT_DEBUG(EFI_D_ERROR, "DPLL %d not locked\n", 1); + break; + } + gBS->Stall(10); + } + + //intel_encoders_pre_enable(crtc, pipe_config, old_state); + //could be intel_ddi_pre_enable_hdmi + //intel_ddi_clk_select(encoder, crtc_state); + UINT32 port = controller->OutputPath.Port; + PRINT_DEBUG(EFI_D_ERROR, "port is %d\n", port); + { + UINT32 val = controller->read32(DPLL_CTRL2); + + //val &= ~(DPLL_CTRL2_DDI_CLK_OFF(PORT_A) | + // DPLL_CTRL2_DDI_CLK_SEL_MASK(PORT_A)); + //val |= (DPLL_CTRL2_DDI_CLK_SEL(id, PORT_A) | + // DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_A)); + + val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | + DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); + val |= (DPLL_CTRL2_DDI_CLK_SEL(id, port) | + DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); + + controller->write32(DPLL_CTRL2, val); + } + PRINT_DEBUG(EFI_D_ERROR, "DPLL_CTRL2 = %08x\n", controller->read32(DPLL_CTRL2)); + return EFI_SUCCESS; +} +EFI_STATUS SetupTranscoderAndPipeHDMI(i915_CONTROLLER *controller) +{ + UINT32 horz_active = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActive | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActiveBlankMsb >> 4) << 8); + UINT32 horz_blank = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzBlank | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzActiveBlankMsb & 0xF) << 8); + UINT32 horz_sync_offset = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzSyncOffset | ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 6) << 8); + UINT32 horz_sync_pulse = controller->edid.detailTimings[DETAIL_TIME_SELCTION].horzSyncPulse | + (((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 4) & 0x3) << 8); + + UINT32 horizontal_active = horz_active; + UINT32 horizontal_syncStart = horz_active + horz_sync_offset; + UINT32 horizontal_syncEnd = horz_active + horz_sync_offset + horz_sync_pulse; + UINT32 horizontal_total = horz_active + horz_blank; + + UINT32 vert_active = controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActive | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActiveBlankMsb >> 4) << 8); + UINT32 vert_blank = controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertBlank | + ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertActiveBlankMsb & 0xF) << 8); + UINT32 vert_sync_offset = (controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertSync >> 4) | (((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb >> 2) & 0x3) + << 4); + UINT32 vert_sync_pulse = (controller->edid.detailTimings[DETAIL_TIME_SELCTION].vertSync & 0xF) | ((UINT32)(controller->edid.detailTimings[DETAIL_TIME_SELCTION].syncMsb & 0x3) << 4); + + UINT32 vertical_active = vert_active; + UINT32 vertical_syncStart = vert_active + vert_sync_offset; + UINT32 vertical_syncEnd = vert_active + vert_sync_offset + vert_sync_pulse; + UINT32 vertical_total = vert_active + vert_blank; + + controller->write32(VSYNCSHIFT_A, 0); + + controller->write32(HTOTAL_A, + (horizontal_active - 1) | + ((horizontal_total - 1) << 16)); + controller->write32(HBLANK_A, + (horizontal_active - 1) | + ((horizontal_total - 1) << 16)); + controller->write32(HSYNC_A, + (horizontal_syncStart - 1) | + ((horizontal_syncEnd - 1) << 16)); + + controller->write32(VTOTAL_A, + (vertical_active - 1) | + ((vertical_total - 1) << 16)); + controller->write32(VBLANK_A, + (vertical_active - 1) | + ((vertical_total - 1) << 16)); + controller->write32(VSYNC_A, + (vertical_syncStart - 1) | + ((vertical_syncEnd - 1) << 16)); + + controller->write32(PIPEASRC, ((horizontal_active - 1) << 16) | (vertical_active - 1)); + UINT32 multiplier = 1; + controller->write32(PIPE_MULT_A, multiplier - 1); + + PRINT_DEBUG(EFI_D_ERROR, "HTOTAL_A (%x) = %08x\n", HTOTAL_A, controller->read32(HTOTAL_A)); + PRINT_DEBUG(EFI_D_ERROR, "HBLANK_A (%x) = %08x\n", HBLANK_A, controller->read32(HBLANK_A)); + PRINT_DEBUG(EFI_D_ERROR, "HSYNC_A (%x) = %08x\n", HSYNC_A, controller->read32(HSYNC_A)); + PRINT_DEBUG(EFI_D_ERROR, "VTOTAL_A (%x) = %08x\n", VTOTAL_A, controller->read32(VTOTAL_A)); + PRINT_DEBUG(EFI_D_ERROR, "VBLANK_A (%x) = %08x\n", VBLANK_A, controller->read32(VBLANK_A)); + PRINT_DEBUG(EFI_D_ERROR, "VSYNC_A (%x) = %08x\n", VSYNC_A, controller->read32(VSYNC_A)); + PRINT_DEBUG(EFI_D_ERROR, "PIPEASRC (%x) = %08x\n", PIPEASRC, controller->read32(PIPEASRC)); + PRINT_DEBUG(EFI_D_ERROR, "BCLRPAT_A (%x) = %08x\n", BCLRPAT_A, controller->read32(BCLRPAT_A)); + PRINT_DEBUG(EFI_D_ERROR, "VSYNCSHIFT_A (%x) = %08x\n", VSYNCSHIFT_A, controller->read32(VSYNCSHIFT_A)); + PRINT_DEBUG(EFI_D_ERROR, "PIPE_MULT_A (%x) = %08x\n", PIPE_MULT_A, controller->read32(PIPE_MULT_A)); + + PRINT_DEBUG(EFI_D_ERROR, "before pipe gamma\n"); + return EFI_SUCCESS; +} \ No newline at end of file diff --git a/i915_hdmi.h b/i915_hdmi.h new file mode 100644 index 0000000..f621af3 --- /dev/null +++ b/i915_hdmi.h @@ -0,0 +1,71 @@ +#ifndef i915_HDMIH +#define i915_HDMIH +#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id)*6 + 5)) +#define _DPLL1_CFGCR1 0x6C040 +#define _DPLL2_CFGCR1 0x6C048 +#define _DPLL3_CFGCR1 0x6C050 +#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) +#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) +#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) +#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) + +#define _DPLL1_CFGCR2 0x6C044 +#define _DPLL2_CFGCR2 0x6C04C +#define _DPLL3_CFGCR2 0x6C054 +#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) +#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) +#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) +#define DPLL_CFGCR2_KDIV_MASK (3 << 5) +#define DPLL_CFGCR2_KDIV(x) ((x) << 5) +#define DPLL_CFGCR2_KDIV_5 (0 << 5) +#define DPLL_CFGCR2_KDIV_2 (1 << 5) +#define DPLL_CFGCR2_KDIV_3 (2 << 5) +#define DPLL_CFGCR2_KDIV_1 (3 << 5) +#define DPLL_CFGCR2_PDIV_MASK (7 << 2) +#define DPLL_CFGCR2_PDIV(x) ((x) << 2) +#define DPLL_CFGCR2_PDIV_1 (0 << 2) +#define DPLL_CFGCR2_PDIV_2 (1 << 2) +#define DPLL_CFGCR2_PDIV_3 (2 << 2) +#define DPLL_CFGCR2_PDIV_7 (4 << 2) +#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) +/* DCO freq must be within +1%/-6% of the DCO central freq */ +#define SKL_DCO_MAX_PDEVIATION 100 +#define SKL_DCO_MAX_NDEVIATION 600 +struct skl_wrpll_params +{ + UINT32 dco_fraction; + UINT32 dco_integer; + UINT32 qdiv_ratio; + UINT32 qdiv_mode; + UINT32 kdiv; + UINT32 pdiv; + UINT32 central_freq; +}; + +static const int even_dividers[] = {4, 6, 8, 10, 12, 14, 16, 18, 20, + 24, 28, 30, 32, 36, 40, 42, 44, + 48, 52, 54, 56, 60, 64, 66, 68, + 70, 72, 76, 78, 80, 84, 88, 90, + 92, 96, 98}; +static const int odd_dividers[] = {3, 5, 7, 9, 15, 21, 35}; +static const struct +{ + const int *list; + int n_dividers; +} dividers[] = { + {even_dividers, ARRAY_SIZE(even_dividers)}, + {odd_dividers, ARRAY_SIZE(odd_dividers)}, +}; + +struct skl_wrpll_context +{ + UINT64 min_deviation; /* current minimal deviation */ + UINT64 central_freq; /* chosen central freq */ + UINT64 dco_freq; /* chosen dco freq */ + UINT64 p; /* chosen divider */ +}; +EFI_STATUS SetupClockHDMI(i915_CONTROLLER *controller); +EFI_STATUS SetupTranscoderAndPipeHDMI(i915_CONTROLLER *controller); +EFI_STATUS ReadEDIDHDMI(EDID *result, i915_CONTROLLER *controller, UINT8 pin); +EFI_STATUS ConvertFallbackEDIDToHDMIEDID(EDID *result, i915_CONTROLLER *controller, UINT8 *fallback); +#endif \ No newline at end of file diff --git a/i915_reg.h b/i915_reg.h new file mode 100644 index 0000000..6217d8b --- /dev/null +++ b/i915_reg.h @@ -0,0 +1,200 @@ +#ifndef i915_REGH +#define i915_REGH +#define PCH_DISPLAY_BASE 0xc0000u +#define DETAIL_TIME_SELCTION 0 +#define DPLL_CTRL1 (0x6C058) +#define DPLL_CTRL1_SSC(id) (1 << ((id)*6 + 4)) +#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id)*6 + 1)) +#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6 + 1) +#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id)*6 + 1)) +#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id)*6)) +#define DPLL_CTRL1_LINK_RATE_2700 0 +#define DPLL_CTRL1_LINK_RATE_1350 1 +#define DPLL_CTRL1_LINK_RATE_810 2 +#define DPLL_CTRL1_LINK_RATE_1620 3 +#define DPLL_CTRL1_LINK_RATE_1080 4 +#define DPLL_CTRL1_LINK_RATE_2160 5 +#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) +#define _PORT(port, a, b) _PICK_EVEN(port, a, b) +#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) + +/** + * roundup - round up to the next specified multiple + * @x: the value to up + * @y: multiple to round up to + * + * Rounds @x up to next multiple of @y. If @y will always be a power + * of 2, consider using the faster round_up(). + * + * The `const' here prevents gcc-3.3 from calling __divdi3 + */ +#define roundup(x, y) ( \ + { \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ + }) +/** + * rounddown - round down to next specified multiple + * @x: the value to round + * @y: multiple to round down to + * + * Rounds @x down to next multiple of @y. If @y will always be a power + * of 2, consider using the faster round_down(). + */ +#define rounddown(x, y) ( \ + { \ + typeof(x) __x = (x); \ + __x - (__x % (y)); \ + }) + +#define _DDI_BUF_TRANS_A 0x64E00 +#define _DDI_BUF_TRANS_B 0x64E60 +#define DDI_BUF_TRANS_LO(port, i) (_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i)*8) //Writes to DWORD 0 At the specified Port and Entry Num +#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) +#define DDI_BUF_TRANS_HI(port, i) (_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i)*8 + 4) //Writes to DWORD 1 At the specified Port and Entry Num +#define _DDI_BUF_CTL_A 0x64000 +#define _DDI_BUF_CTL_B 0x64100 +#define DDI_BUF_CTL(port) _PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) +#define DDI_BUF_CTL_ENABLE (1 << 31) +#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) +#define DDI_BUF_EMP_MASK (0xf << 24) +#define DDI_BUF_PORT_REVERSAL (1 << 16) +#define DDI_BUF_IS_IDLE (1 << 7) +#define DDI_A_4_LANES (1 << 4) +#define DDI_PORT_WIDTH(width) (((width)-1) << 1) +#define DDI_PORT_WIDTH_MASK (7 << 1) +#define DDI_PORT_WIDTH_SHIFT 1 +#define DDI_INIT_DISPLAY_DETECTED (1 << 0) +#define _DP_TP_CTL_A 0x64040 +#define _DP_TP_CTL_B 0x64140 +#define _TGL_DP_TP_CTL_A 0x60540 +#define DP_TP_CTL(port) _PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) +#define DPLL_STATUS (0x6C060) +#define DPLL_LOCK(id) (1 << ((id)*8)) + +#define PIPEA_DATA_M1 0x60030 +#define PIPEA_DATA_N1 0x60034 +#define PIPEA_LINK_M1 0x60040 +#define PIPEA_LINK_N1 0x60044 + +#define PIPEEDP_DATA_M1 0x6f030 +#define PIPEEDP_DATA_N1 0x6f034 +#define PIPEEDP_LINK_M1 0x6f040 +#define PIPEEDP_LINK_N1 0x6f044 + +#define BKL_GRAN_CTL 0xc2000 +#define SBLC_PWM_CTL1 0xc8250 +#define _BXT_BLC_PWM_CTL1 0xC8250 +#define BXT_BLC_PWM_ENABLE (1 << 31) +#define BXT_BLC_PWM_POLARITY (1 << 29) +#define _BXT_BLC_PWM_FREQ1 0xC8254 +#define _BXT_BLC_PWM_DUTY1 0xC8258 + +#define _BXT_BLC_PWM_CTL2 0xC8350 +#define _BXT_BLC_PWM_FREQ2 0xC8354 +#define _BXT_BLC_PWM_DUTY2 0xC8358 + +#define KHz(x) (1000 * (x)) +#define DIV_ROUND_CLOSEST(x, divisor) ( \ + { \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || (__x) > 0) \ + ? (((__x) + ((__d) / 2)) / (__d)) \ + : (((__x) - ((__d) / 2)) / (__d)); \ + }) + +#define LCPLL1_CTL (0x46010) +#define LCPLL2_CTL (0x46014) +#define LCPLL_PLL_ENABLE (1 << 31) +#define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 +#define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) +#define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) +#define DPLL_FPA1_P1_POST_DIV_SHIFT 0 +#define DPLL_FPA1_P1_POST_DIV_MASK 0xff + +#define _DPLL_A_MD (PCH_DISPLAY_BASE + 0x601c) +#define _DPLL_B_MD (PCH_DISPLAY_BASE + 0x6020) +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +/* + * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. + * This best be set to the default value (3) or the CRT won't work. No, + * I don't entirely understand what this does... + */ +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 + +#define DPLL_CTRL2 (0x6C05C) +#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) +#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port)*3 + 1)) +#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3 + 1) +#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port)*3 + 1)) +#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port)*3)) + +/* Pipe A timing regs */ +#define HTOTAL_A 0x60000 +#define HBLANK_A 0x60004 +#define HSYNC_A 0x60008 +#define VTOTAL_A 0x6000c +#define VBLANK_A 0x60010 +#define VSYNC_A 0x60014 +#define PIPEASRC 0x6001c +#define BCLRPAT_A 0x60020 +#define VSYNCSHIFT_A 0x60028 +#define PIPE_MULT_A 0x6002c + +/* Pipe B timing regs */ +#define HTOTAL_B 0x61000 +#define HBLANK_B 0x61004 +#define HSYNC_B 0x61008 +#define VTOTAL_B 0x6100c +#define VBLANK_B 0x61010 +#define VSYNC_B 0x61014 +#define PIPEBSRC 0x6101c +#define BCLRPAT_B 0x61020 +#define VSYNCSHIFT_B 0x61028 +#define PIPE_MULT_B 0x6102c + +/* Pipe eDP timing regs */ +#define HTOTAL_EDP 0x6f000 +#define HBLANK_EDP 0x6f004 +#define HSYNC_EDP 0x6f008 +#define VTOTAL_EDP 0x6f00c +#define VBLANK_EDP 0x6f010 +#define VSYNC_EDP 0x6f014 +#define PIPEEDPSRC 0x6f01c +#define BCLRPAT_EDP 0x6f020 +#define VSYNCSHIFT_EDP 0x6f028 +#define SFUSE_STRAP 0xc2014 +#define SFUSE_STRAP_FUSE_LOCK (1 << 13) +#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) +enum port +{ + PORT_NONE = -1, + + PORT_A = 0, + PORT_B, + PORT_C, + PORT_D, + PORT_E, + PORT_F, + PORT_G, + PORT_H, + PORT_I, + + I915_MAX_PORTS +}; + +typedef UINT8 u8; +typedef UINT16 u16; + +typedef UINT32 u32; +typedef UINT64 u64; +typedef BOOLEAN bool; +#define true TRUE +#define false FALSE +#define __packed __attribute__((packed)) + +#endif \ No newline at end of file diff --git a/i915ovmf.c b/i915ovmf.c index 5990075..b86e817 100755 --- a/i915ovmf.c +++ b/i915ovmf.c @@ -1,1810 +1,61 @@ -#include +#include #include +#include #include #include -#include -#include +#include +#include "QemuFwCfgLib.h" +#include "i915_display.h" +#include "i915_gop.h" +#include "i915ovmf.h" +#include +#include #include #include -#include -#include -#include +#include "i915_debug.h" #include #include #include -#include +#include +#include #include -#include "QemuFwCfgLib.h" - -#include -#include - -//registers are in bar 0 -//frame buffer is in bar 2 -#define PCH_DISPLAY_BASE 0xc0000u - -#define HSW_PWR_WELL_CTL1 (0x45400) -#define HSW_PWR_WELL_CTL2 (0x45404) -#define HSW_PWR_WELL_CTL3 (0x45408) -#define HSW_PWR_WELL_CTL4 (0x4540C) - -#define GMBUS0 (PCH_DISPLAY_BASE+0x5100) -#define gmbusSelect (PCH_DISPLAY_BASE+0x5100) -#define GMBUS_AKSV_SELECT (1 << 11) -#define GMBUS_RATE_100KHZ (0 << 8) -#define GMBUS_RATE_50KHZ (1 << 8) -#define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ -#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ -#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ -#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) -#define GMBUS_PIN_DISABLED 0 -#define GMBUS_PIN_SSC 1 -#define GMBUS_PIN_VGADDC 2 -#define GMBUS_PIN_PANEL 3 -#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ -#define GMBUS_PIN_DPC 4 /* HDMIC */ -#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ -#define GMBUS_PIN_DPD 6 /* HDMID */ -#define GMBUS_PIN_RESERVED 7 /* 7 reserved */ -#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */ -#define GMBUS_PIN_2_BXT 2 -#define GMBUS_PIN_3_BXT 3 -#define GMBUS_PIN_4_CNP 4 -#define GMBUS_PIN_9_TC1_ICP 9 -#define GMBUS_PIN_10_TC2_ICP 10 -#define GMBUS_PIN_11_TC3_ICP 11 -#define GMBUS_PIN_12_TC4_ICP 12 - -#define gmbusCommand (PCH_DISPLAY_BASE+0x5104) -#define GMBUS_SW_CLR_INT (1 << 31) -#define GMBUS_SW_RDY (1 << 30) -#define GMBUS_ENT (1 << 29) /* enable timeout */ -#define GMBUS_CYCLE_NONE (0 << 25) -#define GMBUS_CYCLE_WAIT (1 << 25) -#define GMBUS_CYCLE_INDEX (2 << 25) -#define GMBUS_CYCLE_STOP (4 << 25) -#define GMBUS_BYTE_COUNT_SHIFT 16 -#define GMBUS_BYTE_COUNT_MAX 256U -#define GEN9_GMBUS_BYTE_COUNT_MAX 511U -#define GMBUS_SLAVE_INDEX_SHIFT 8 -#define GMBUS_SLAVE_ADDR_SHIFT 1 -#define GMBUS_SLAVE_READ (1 << 0) -#define GMBUS_SLAVE_WRITE (0 << 0) - -#define gmbusStatus (PCH_DISPLAY_BASE+0x5108) -#define GMBUS_INUSE (1 << 15) -#define GMBUS_HW_WAIT_PHASE (1 << 14) -#define GMBUS_STALL_TIMEOUT (1 << 13) -#define GMBUS_INT (1 << 12) -#define GMBUS_HW_RDY (1 << 11) -#define GMBUS_SATOER (1 << 10) -#define GMBUS_ACTIVE (1 << 9) - -#define gmbusData (PCH_DISPLAY_BASE+0x510C) -#define GMBUS4 (PCH_DISPLAY_BASE+0x5110) - -#define _PCH_DP_B (0xe4100) -#define _PCH_DPB_AUX_CH_CTL (0xe4110) -#define _PCH_DPB_AUX_CH_DATA1 (0xe4114) -#define _PCH_DPB_AUX_CH_DATA2 (0xe4118) -#define _PCH_DPB_AUX_CH_DATA3 (0xe411c) -#define _PCH_DPB_AUX_CH_DATA4 (0xe4120) -#define _PCH_DPB_AUX_CH_DATA5 (0xe4124) - -#define _DPA_AUX_CH_CTL (0x64010) -#define _DPA_AUX_CH_DATA1 (0x64014) -#define _DPA_AUX_CH_DATA2 (0x64018) -#define _DPA_AUX_CH_DATA3 (0x6401c) -#define _DPA_AUX_CH_DATA4 (0x64020) -#define _DPA_AUX_CH_DATA5 (0x64024) - -#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) -#define DP_AUX_CH_CTL_DONE (1 << 30) -#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) -#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) -#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ -#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) -#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 -#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) -#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 -#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) -#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) -#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) -#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) -#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 -#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) -#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) -#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) -#define DP_AUX_CH_CTL_TBT_IO (1 << 11) -#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) -#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) -#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) - -#define AUX_NATIVE_WRITE 0x8 -#define AUX_NATIVE_READ 0x9 -#define AUX_I2C_WRITE 0x0 -#define AUX_I2C_READ 0x1 -#define AUX_I2C_STATUS 0x2 -#define AUX_I2C_MOT 0x4 -#define AUX_I2C_REPLY_ACK 0x0 - -#define VGACNTRL (0x71400) -#define VGA_DISP_DISABLE (1 << 31) -#define VGA_2X_MODE (1 << 30) - -/* Pipe A timing regs */ -#define HTOTAL_A 0x60000 -#define HBLANK_A 0x60004 -#define HSYNC_A 0x60008 -#define VTOTAL_A 0x6000c -#define VBLANK_A 0x60010 -#define VSYNC_A 0x60014 -#define PIPEASRC 0x6001c -#define BCLRPAT_A 0x60020 -#define VSYNCSHIFT_A 0x60028 -#define PIPE_MULT_A 0x6002c - -/* Pipe B timing regs */ -#define HTOTAL_B 0x61000 -#define HBLANK_B 0x61004 -#define HSYNC_B 0x61008 -#define VTOTAL_B 0x6100c -#define VBLANK_B 0x61010 -#define VSYNC_B 0x61014 -#define PIPEBSRC 0x6101c -#define BCLRPAT_B 0x61020 -#define VSYNCSHIFT_B 0x61028 -#define PIPE_MULT_B 0x6102c - -#define _PIPEACONF 0x70008 -#define _PIPEBCONF 0x71008 -#define PIPECONF_ENABLE (1 << 31) -#define PIPECONF_DISABLE 0 -#define PIPECONF_DOUBLE_WIDE (1 << 30) -#define I965_PIPECONF_ACTIVE (1 << 30) -#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */ -#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) -#define PIPECONF_SINGLE_WIDE 0 -#define PIPECONF_PIPE_UNLOCKED 0 -#define PIPECONF_PIPE_LOCKED (1 << 25) -#define PIPECONF_FORCE_BORDER (1 << 25) -#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */ -#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */ -#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */ -#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */ -#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */ -#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */ -#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */ -#define PIPECONF_GAMMA_MODE_SHIFT 24 -#define PIPECONF_INTERLACE_MASK (7 << 21) -#define PIPECONF_INTERLACE_MASK_HSW (3 << 21) -/* Note that pre-gen3 does not support interlaced display directly. Panel - * fitting must be disabled on pre-ilk for interlaced. */ -#define PIPECONF_PROGRESSIVE (0 << 21) -#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ -/* Ironlake and later have a complete new set of values for interlaced. PFIT - * means panel fitter required, PF means progressive fetch, DBL means power - * saving pixel doubling. */ -#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) -#define PIPECONF_INTERLACED_ILK (3 << 21) -#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ -#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ -#define PIPECONF_INTERLACE_MODE_MASK (7 << 21) -#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) -#define PIPECONF_CXSR_DOWNCLOCK (1 << 16) -#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) -#define PIPECONF_COLOR_RANGE_SELECT (1 << 13) -#define PIPECONF_BPC_MASK (0x7 << 5) -#define PIPECONF_8BPC (0 << 5) -#define PIPECONF_10BPC (1 << 5) -#define PIPECONF_6BPC (2 << 5) -#define PIPECONF_12BPC (3 << 5) -#define PIPECONF_DITHER_EN (1 << 4) -#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) -#define PIPECONF_DITHER_TYPE_SP (0 << 2) -#define PIPECONF_DITHER_TYPE_ST1 (1 << 2) -#define PIPECONF_DITHER_TYPE_ST2 (2 << 2) -#define PIPECONF_DITHER_TYPE_TEMP (3 << 2) -#define _PIPEASTAT 0x70024 -#define _PIPEBSTAT 0x71024 -#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) -#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) -#define PIPE_CRC_ERROR_ENABLE (1UL << 29) -#define PIPE_CRC_DONE_ENABLE (1UL << 28) -#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) -#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) -#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) -#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) -#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) -#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) -#define PIPE_DPST_EVENT_ENABLE (1UL << 23) -#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) -#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) -#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) -#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) -#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) -#define PERF_COUNTER_INTERRUPT_EN (1UL << 19) -#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ -#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) -#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) -#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) -#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) -#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) -#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) -#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) -#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) -#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) -#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) -#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) -#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) -#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) -#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) -#define PIPE_DPST_EVENT_STATUS (1UL << 7) -#define PIPE_A_PSR_STATUS_VLV (1UL << 6) -#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) -#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) -#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) -#define PIPE_B_PSR_STATUS_VLV (1UL << 3) -#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) -#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ -#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) -#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) -#define PIPE_HBLANK_INT_STATUS (1UL << 0) -#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) - -#define _DSPACNTR 0x70180 -#define DISPLAY_PLANE_ENABLE (1 << 31) -#define DISPLAY_PLANE_DISABLE 0 -#define PLANE_CTL_FORMAT_MASK (0xf << 24) -#define PLANE_CTL_FORMAT_YUV422 (0 << 24) -#define PLANE_CTL_FORMAT_NV12 (1 << 24) -#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) -#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) -#define PLANE_CTL_ORDER_BGRX (0 << 20) -#define PLANE_CTL_ORDER_RGBX (1 << 20) -#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ -#define PLANE_CTL_ALPHA_DISABLE (0 << 4) -#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4) -#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4) -#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) -#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */ - -#define DISPPLANE_PIXFORMAT_MASK (0xf << 26) -#define DISPPLANE_YUV422 (0x0 << 26) -#define DISPPLANE_8BPP (0x2 << 26) -#define DISPPLANE_BGRA555 (0x3 << 26) -#define DISPPLANE_BGRX555 (0x4 << 26) -#define DISPPLANE_BGRX565 (0x5 << 26) -#define DISPPLANE_BGRX888 (0x6 << 26) -#define DISPPLANE_BGRA888 (0x7 << 26) -#define DISPPLANE_RGBX101010 (0x8 << 26) -#define DISPPLANE_RGBA101010 (0x9 << 26) -#define DISPPLANE_BGRX101010 (0xa << 26) -#define DISPPLANE_RGBX161616 (0xc << 26) -#define DISPPLANE_RGBX888 (0xe << 26) -#define DISPPLANE_RGBA888 (0xf << 26) - -#define _DSPAADDR 0x70184 -#define _DSPASTRIDE 0x70188 -#define _DSPAPOS 0x7018C /* reserved */ -#define _DSPASIZE 0x70190 -#define _DSPASURF 0x7019C /* 965+ only */ -#define _DSPATILEOFF 0x701A4 /* 965+ only */ -#define _DSPAOFFSET 0x701A4 /* HSW */ -#define _DSPASURFLIVE 0x701AC - -#define _TRANSA_MSA_MISC 0x60410 -#define _TRANSB_MSA_MISC 0x61410 -#define _TRANSC_MSA_MISC 0x62410 -#define _TRANS_EDP_MSA_MISC 0x6f410 - -#define TRANS_MSA_SYNC_CLK (1 << 0) -#define TRANS_MSA_SAMPLING_444 (2 << 1) -#define TRANS_MSA_CLRSP_YCBCR (2 << 3) -#define TRANS_MSA_6_BPC (0 << 5) -#define TRANS_MSA_8_BPC (1 << 5) -#define TRANS_MSA_10_BPC (2 << 5) -#define TRANS_MSA_12_BPC (3 << 5) -#define TRANS_MSA_16_BPC (4 << 5) -#define TRANS_MSA_CEA_RANGE (1 << 3) - -#define _TRANS_DDI_FUNC_CTL_A 0x60400 -#define _TRANS_DDI_FUNC_CTL_B 0x61400 -#define _TRANS_DDI_FUNC_CTL_C 0x62400 -#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 -#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 -#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 - -#define TRANS_DDI_FUNC_ENABLE (1 << 31) -/* Those bits are ignored by pipe EDP since it can only connect to DDI A */ -#define TRANS_DDI_PORT_MASK (7 << 28) -#define TRANS_DDI_PORT_SHIFT 28 -#define TRANS_DDI_SELECT_PORT(x) ((x) << 28) -#define TRANS_DDI_PORT_NONE (0 << 28) -#define TRANS_DDI_MODE_SELECT_MASK (7 << 24) -#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) -#define TRANS_DDI_MODE_SELECT_DVI (1 << 24) -#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) -#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) -#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) -#define TRANS_DDI_BPC_MASK (7 << 20) -#define TRANS_DDI_BPC_8 (0 << 20) -#define TRANS_DDI_BPC_10 (1 << 20) -#define TRANS_DDI_BPC_6 (2 << 20) -#define TRANS_DDI_BPC_12 (3 << 20) -#define TRANS_DDI_PVSYNC (1 << 17) -#define TRANS_DDI_PHSYNC (1 << 16) -#define TRANS_DDI_EDP_INPUT_MASK (7 << 12) -#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) -#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) -#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) -#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) -#define TRANS_DDI_HDCP_SIGNALLING (1 << 9) -#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) -#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) -#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) -#define TRANS_DDI_BFI_ENABLE (1 << 4) -#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) -#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) -#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ - | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ - | TRANS_DDI_HDMI_SCRAMBLING) - -#define _TRANS_DDI_FUNC_CTL2_A 0x60404 -#define _TRANS_DDI_FUNC_CTL2_B 0x61404 -#define _TRANS_DDI_FUNC_CTL2_C 0x62404 -#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 -#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 -#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 -#define PORT_SYNC_MODE_ENABLE (1 << 4) -#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0) -#define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0) -#define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0 - -#define PORT_A 0 -#define PORT_B 1 -#define PORT_C 2 -#define PORT_D 3 -#define PORT_E 4 - -#define _FPA0 (PCH_DISPLAY_BASE+0x6040) -#define _FPA1 (PCH_DISPLAY_BASE+0x6044) -#define _FPB0 (PCH_DISPLAY_BASE+0x6048) -#define _FPB1 (PCH_DISPLAY_BASE+0x604c) -#define FP_N_DIV_MASK 0x003f0000 -#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 -#define FP_N_DIV_SHIFT 16 -#define FP_M1_DIV_MASK 0x00003f00 -#define FP_M1_DIV_SHIFT 8 -#define FP_M2_DIV_MASK 0x0000003f -#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff -#define FP_M2_DIV_SHIFT 0 - -#define _DPLL_A (PCH_DISPLAY_BASE + 0x6014) -#define _DPLL_B (PCH_DISPLAY_BASE + 0x6018) -#define DPLL_VCO_ENABLE (1 << 31) -#define DPLL_SDVO_HIGH_SPEED (1 << 30) -#define DPLL_DVO_2X_MODE (1 << 30) -#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) -#define DPLL_SYNCLOCK_ENABLE (1 << 29) -#define DPLL_REF_CLK_ENABLE_VLV (1 << 29) -#define DPLL_VGA_MODE_DIS (1 << 28) -#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ -#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ -#define DPLL_MODE_MASK (3 << 26) -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ -#define DPLL_LOCK_VLV (1 << 15) -#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) -#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) -#define DPLL_SSC_REF_CLK_CHV (1 << 13) -#define DPLL_PORTC_READY_MASK (0xf << 4) -#define DPLL_PORTB_READY_MASK (0xf) - -#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 -#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 - -#define PLL_P2_DIVIDE_BY_4 (1 << 23) -#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ -#define PLL_REF_INPUT_DREFCLK (0 << 13) -#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ -#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) -#define PLL_REF_INPUT_MASK (3 << 13) -#define PLL_LOAD_PULSE_PHASE_SHIFT 9 -/* Ironlake */ -#define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 -#define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) -#define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) -#define DPLL_FPA1_P1_POST_DIV_SHIFT 0 -#define DPLL_FPA1_P1_POST_DIV_MASK 0xff - -#define _DPLL_A_MD (PCH_DISPLAY_BASE + 0x601c) -#define _DPLL_B_MD (PCH_DISPLAY_BASE + 0x6020) -#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 -#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 -/* - * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. - * This best be set to the default value (3) or the CRT won't work. No, - * I don't entirely understand what this does... - */ -#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f -#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 - -#define DPLL_CTRL2 (0x6C05C) -#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) -#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) -#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) -#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) -#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) - -#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) -#define _PORT(port, a, b) _PICK_EVEN(port, a, b) - -#define _DDI_BUF_TRANS_A 0x64E00 -#define _DDI_BUF_TRANS_B 0x64E60 -#define DDI_BUF_TRANS_LO(port, i) (_PORT(port, _DDI_BUF_TRANS_A,_DDI_BUF_TRANS_B) + (i) * 8) -#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) -#define DDI_BUF_TRANS_HI(port, i) (_PORT(port, _DDI_BUF_TRANS_A,_DDI_BUF_TRANS_B) + (i) * 8 + 4) - -#define DISPIO_CR_TX_BMU_CR0 (0x6C00C) -/* I_boost values */ -#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) -#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) -/* Balance leg disable bits */ -#define BALANCE_LEG_DISABLE_SHIFT 23 -#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) - -#define _TRANS_CLK_SEL_A 0x46140 -#define _TRANS_CLK_SEL_B 0x46144 -/* For each transcoder, we need to select the corresponding port clock */ -#define TRANS_CLK_SEL_DISABLED (0x0 << 29) -#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) - -#define _LGC_PALETTE_A 0x4a000 -#define _LGC_PALETTE_B 0x4a800 - -#define _SKL_BOTTOM_COLOR_A 0x70034 -#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31) -#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30) - -#define _GAMMA_MODE_A 0x4a480 -#define _GAMMA_MODE_B 0x4ac80 -#define PRE_CSC_GAMMA_ENABLE (1 << 31) -#define POST_CSC_GAMMA_ENABLE (1 << 30) -#define GAMMA_MODE_MODE_8BIT (0 << 0) -#define GAMMA_MODE_MODE_10BIT (1 << 0) -#define GAMMA_MODE_MODE_12BIT (2 << 0) -#define GAMMA_MODE_MODE_SPLIT (3 << 0) - -#define SFUSE_STRAP (0xc2014) -#define SFUSE_STRAP_FUSE_LOCK (1 << 13) -#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) -#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) -#define SFUSE_STRAP_CRT_DISABLED (1 << 6) -#define SFUSE_STRAP_DDIF_DETECTED (1 << 3) -#define SFUSE_STRAP_DDIB_DETECTED (1 << 2) -#define SFUSE_STRAP_DDIC_DETECTED (1 << 1) -#define SFUSE_STRAP_DDID_DETECTED (1 << 0) - -#define _DDI_BUF_CTL_A 0x64000 -#define _DDI_BUF_CTL_B 0x64100 -#define DDI_BUF_CTL(port) _PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) -#define DDI_BUF_CTL_ENABLE (1 << 31) -#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) -#define DDI_BUF_EMP_MASK (0xf << 24) -#define DDI_BUF_PORT_REVERSAL (1 << 16) -#define DDI_BUF_IS_IDLE (1 << 7) -#define DDI_A_4_LANES (1 << 4) -#define DDI_PORT_WIDTH(width) (((width) - 1) << 1) -#define DDI_PORT_WIDTH_MASK (7 << 1) -#define DDI_PORT_WIDTH_SHIFT 1 -#define DDI_INIT_DISPLAY_DETECTED (1 << 0) - -#define CHICKEN_TRANS_A (0x420c0) -#define CHICKEN_TRANS_B (0x420c4) -#define CHICKEN_TRANS_C (0x420c8) -#define CHICKEN_TRANS_EDP (0x420cc) -#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ -#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) -#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) -#define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */ -#define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */ -#define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15) -#define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12) - -#define HSW_NDE_RSTWRN_OPT (0x46408) -#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) - -#define CDCLK_CTL (0x46000) -#define CDCLK_FREQ_SEL_MASK (3 << 26) -#define CDCLK_FREQ_450_432 (0 << 26) -#define CDCLK_FREQ_540 (1 << 26) -#define CDCLK_FREQ_337_308 (2 << 26) -#define CDCLK_FREQ_675_617 (3 << 26) -#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) -#define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) -#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) -#define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) -#define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) -#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) -#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) -#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) -#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) -#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) -#define CDCLK_FREQ_DECIMAL_MASK (0x7ff) - -#define DBUF_CTL (0x45008) -#define DBUF_CTL_S1 (0x45008) -#define DBUF_CTL_S2 (0x44FE8) -#define DBUF_POWER_REQUEST (1 << 31) -#define DBUF_POWER_STATE (1 << 30) - -#define MBUS_ABOX_CTL (0x45038) -#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) -#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) -#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) -#define MBUS_ABOX_B_CREDIT(x) ((x) << 16) -#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) -#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) -#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) -#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) - -#define _PLANE_BUF_CFG_1_A 0x7027c - -#define I915_READ read32 -#define I915_WRITE write32 - -STATIC EFI_GRAPHICS_OUTPUT_MODE_INFORMATION g_mode_info[] = { - { - 0, // Version - 1024, // HorizontalResolution - 768, // VerticalResolution - } -}; - -STATIC EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE g_mode = { - ARRAY_SIZE (g_mode_info), // MaxMode - 0, // Mode - g_mode_info, // Info - sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), // SizeOfInfo -}; - -#pragma pack(1) -typedef struct { - UINT8 magic[8]; - UINT16 vendorId; - UINT16 productId; - UINT32 serialNumber; - UINT8 manufactureWeek; - UINT8 manufactureYear; - UINT8 structVersion; - UINT8 structRevision; - UINT8 inputParameters; - UINT8 screenWidth; - UINT8 screenHeight; - UINT8 gamma; - UINT8 features; - UINT8 colorCoordinates[10]; - UINT8 estTimings1; - UINT8 estTimings2; - UINT8 vendorTimings; - struct { - UINT8 resolution; - UINT8 frequency; - } standardTimings[8]; - struct { - UINT16 pixelClock; - UINT8 horzActive; - UINT8 horzBlank; - UINT8 horzActiveBlankMsb; - UINT8 vertActive; - UINT8 vertBlank; - UINT8 vertActiveBlankMsb; - UINT8 horzSyncOffset; - UINT8 horzSyncPulse; - UINT8 vertSync; - UINT8 syncMsb; - UINT8 dimensionWidth; - UINT8 dimensionHeight; - UINT8 dimensionMsb; - UINT8 horzBorder; - UINT8 vertBorder; - UINT8 features; - } detailTimings[4]; - UINT8 numExtensions; - UINT8 checksum; -} EDID; -#pragma pack() - -typedef struct { - UINT64 Signature; - EFI_HANDLE Handle; - EFI_PCI_IO_PROTOCOL *PciIo; - EFI_GRAPHICS_OUTPUT_PROTOCOL GraphicsOutput; - EFI_DEVICE_PATH_PROTOCOL *GopDevicePath; - EDID edid; - EFI_PHYSICAL_ADDRESS FbBase; - UINT32 stride; - UINT32 gmadr; - UINT32 is_gvt; -} I915_VIDEO_PRIVATE_DATA; - -I915_VIDEO_PRIVATE_DATA g_private={SIGNATURE_32('i','9','1','5')}; - -static void write32(UINT64 reg, UINT32 data){ - g_private.PciIo->Mem.Write ( - g_private.PciIo, - EfiPciIoWidthFillUint32, - PCI_BAR_IDX0, - reg, - 1, - &data - ); -} - -static UINT32 read32(UINT64 reg){ - UINT32 data=0; - g_private.PciIo->Mem.Read ( - g_private.PciIo, - EfiPciIoWidthFillUint32, - PCI_BAR_IDX0, - reg, - 1, - &data - ); - return data; -} - -static UINT64 read64(UINT64 reg){ - UINT64 data=0; - g_private.PciIo->Mem.Read ( - g_private.PciIo, - EfiPciIoWidthFillUint64, - PCI_BAR_IDX0, - reg, - 1, - &data - ); - return data; -} - -static EFI_STATUS gmbusWait(UINT32 wanted){ - UINTN counter=0; - for(;;){ - UINT32 status=read32(gmbusStatus); - counter+=1; - if(counter>=1024){ - //failed - DebugPrint(EFI_D_ERROR,"i915: gmbus timeout\n"); - return EFI_DEVICE_ERROR; - } - if(status&GMBUS_SATOER){ - //failed - DebugPrint(EFI_D_ERROR,"i915: gmbus error\n"); - return EFI_DEVICE_ERROR; - } - if(status&wanted){ - //worked - return EFI_SUCCESS; - } - } -} - -static EFI_STATUS ReadEDID(EDID* result){ - UINT32 pin=0; - //it's an INTEL GPU, there's no way we could be big endian - UINT32* p=(UINT32*)result; - //try all the pins on GMBUS - for(pin=1;pin<=6;pin++){ - DebugPrint(EFI_D_ERROR,"i915: trying pin %d\n",pin); - write32(gmbusSelect, pin); - if(EFI_ERROR(gmbusWait(GMBUS_HW_RDY))){ - //it's DP, need to hack AUX_CHAN - continue; - } - //set read offset: i2cWrite(0x50, &offset, 1); - write32(gmbusData, 0); - write32(gmbusCommand, (0x50<>2]=read32(gmbusData); - } - //gmbusWait(GMBUS_HW_WAIT_PHASE); - gmbusWait(GMBUS_HW_RDY); - for(UINT32 i=0;i<16;i++){ - for(UINT32 j=0;j<8;j++){ - DebugPrint(EFI_D_ERROR,"%02x ",((UINT8*)(p))[i*8+j]); - } - DebugPrint(EFI_D_ERROR,"\n"); - } - if(i>=128&&*(UINT64*)result->magic==0x00FFFFFFFFFFFF00uLL){return EFI_SUCCESS;} - } - //try DP AUX CHAN - Skylake - //write32(_DPA_AUX_CH_CTL+(1<<8),0x1234) - //write32(_DPA_AUX_CH_CTL+(0x600),0x1234); - //write32(_DPA_AUX_CH_CTL+(0<<8),0x1234); - //write32(_DPA_AUX_CH_DATA1+(0<<8),0xabcd); - //write32(_DPA_AUX_CH_DATA2+(0<<8),0xabcd); - //write32(_DPA_AUX_CH_DATA3+(0<<8),0xabcd); - //DebugPrint(EFI_D_ERROR,"i915: SKL CTL %08x\n",read32(_DPA_AUX_CH_CTL+(0<<8))); - //DebugPrint(EFI_D_ERROR,"i915: SKL DATA %08x\n",read32(_DPA_AUX_CH_DATA1+(0<<8))); - //DebugPrint(EFI_D_ERROR,"i915: SKL DATA %08x\n",read32(_DPA_AUX_CH_DATA2+(0<<8))); - //DebugPrint(EFI_D_ERROR,"i915: SKL DATA %08x\n",read32(_DPA_AUX_CH_DATA3+(0<<8))); - //write32(_PCH_DP_B+(1<<8),0x1234); - //DebugPrint(EFI_D_ERROR,"i915: SKL %08x\n",read32(_DPA_AUX_CH_CTL+(1<<8))); - //DebugPrint(EFI_D_ERROR,"i915: PCH %08x\n",read32(_PCH_DP_B+(1<<8))); - for(pin=0;pin<=5;pin++){ - DebugPrint(EFI_D_ERROR,"i915: trying DP aux %d\n",pin); - //aux message header is 3-4 bytes: ctrl8 addr16 len8 - //the data is big endian - //len is receive buffer size-1 - //i2c init - UINT32 send_ctl=( - DP_AUX_CH_CTL_SEND_BUSY | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_TIME_OUT_MAX | - DP_AUX_CH_CTL_RECEIVE_ERROR | - (3 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | - DP_AUX_CH_CTL_SYNC_PULSE_SKL(32) - ); - /* Must try at least 3 times according to DP spec, WHICH WE DON'T CARE */ - write32(_DPA_AUX_CH_DATA1+(pin<<8), ((AUX_I2C_MOT|AUX_I2C_WRITE)<<28)|(0x50<<8)|0); - write32(_DPA_AUX_CH_CTL+(pin<<8), send_ctl); - UINT32 aux_status; - UINT32 counter=0; - for(;;){ - aux_status=read32(_DPA_AUX_CH_CTL+(pin<<8)); - if(!(aux_status&DP_AUX_CH_CTL_SEND_BUSY)){break;} - counter+=1; - if(counter>=16384){ - DebugPrint(EFI_D_ERROR,"i915:DP AUX channel timeout"); - break; - } - } - write32(_DPA_AUX_CH_CTL+(pin<<8), - aux_status | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR - ); - //i2c send 1 byte - send_ctl=( - DP_AUX_CH_CTL_SEND_BUSY | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_TIME_OUT_MAX | - DP_AUX_CH_CTL_RECEIVE_ERROR | - (5 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | - DP_AUX_CH_CTL_SYNC_PULSE_SKL(32) - ); - write32(_DPA_AUX_CH_DATA1+(pin<<8), (AUX_I2C_WRITE<<28)|(0x50<<8)|0); - write32(_DPA_AUX_CH_DATA2+(pin<<8), 0); - write32(_DPA_AUX_CH_CTL+(pin<<8), send_ctl); - counter=0; - for(;;){ - aux_status=read32(_DPA_AUX_CH_CTL+(pin<<8)); - if(!(aux_status&DP_AUX_CH_CTL_SEND_BUSY)){break;} - counter+=1; - if(counter>=16384){ - DebugPrint(EFI_D_ERROR,"i915:DP AUX channel timeout"); - break; - } - } - write32(_DPA_AUX_CH_CTL+(pin<<8), - aux_status | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR - ); - if (aux_status & (DP_AUX_CH_CTL_TIME_OUT_ERROR|DP_AUX_CH_CTL_RECEIVE_ERROR)){ - continue; - } - //i2c read 1 byte * 128 - DebugPrint(EFI_D_ERROR,"i915: reading DP aux %d\n",pin); - //aux message header is 3-4 bytes: ctrl8 addr16 len8 - //the data is big endian - //len is receive buffer size-1 - //i2c init - send_ctl=( - DP_AUX_CH_CTL_SEND_BUSY | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_TIME_OUT_MAX | - DP_AUX_CH_CTL_RECEIVE_ERROR | - (3 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | - DP_AUX_CH_CTL_SYNC_PULSE_SKL(32) - ); - /* Must try at least 3 times according to DP spec, WHICH WE DON'T CARE */ - write32(_DPA_AUX_CH_DATA1+(pin<<8), ((AUX_I2C_MOT|AUX_I2C_READ)<<28)|(0x50<<8)|0); - write32(_DPA_AUX_CH_CTL+(pin<<8), send_ctl); - counter=0; - for(;;){ - aux_status=read32(_DPA_AUX_CH_CTL+(pin<<8)); - if(!(aux_status&DP_AUX_CH_CTL_SEND_BUSY)){break;} - counter+=1; - if(counter>=16384){ - DebugPrint(EFI_D_ERROR,"i915: DP AUX channel timeout"); - break; - } - } - write32(_DPA_AUX_CH_CTL+(pin<<8), - aux_status | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR - ); - UINT32 i=0; - for(i=0;i<128;i++){ - send_ctl=( - DP_AUX_CH_CTL_SEND_BUSY | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_TIME_OUT_MAX | - DP_AUX_CH_CTL_RECEIVE_ERROR | - (4 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | - DP_AUX_CH_CTL_SYNC_PULSE_SKL(32) - ); - write32(_DPA_AUX_CH_DATA1+(pin<<8), (AUX_I2C_READ<<28)|(0x50<<8)|0); - write32(_DPA_AUX_CH_CTL+(pin<<8), send_ctl); - counter=0; - for(;;){ - aux_status=read32(_DPA_AUX_CH_CTL+(pin<<8)); - if(!(aux_status&DP_AUX_CH_CTL_SEND_BUSY)){break;} - counter+=1; - if(counter>=16384){ - DebugPrint(EFI_D_ERROR,"i915: DP AUX channel timeout"); - break; - } - } - write32(_DPA_AUX_CH_CTL+(pin<<8), - aux_status | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR - ); - UINT32 word=read32(_DPA_AUX_CH_DATA1+(pin<<8)); - ((UINT8*)p)[i]=(word>>16)&0xff; - } - for(UINT32 i=0;i<16;i++){ - for(UINT32 j=0;j<8;j++){ - DebugPrint(EFI_D_ERROR,"%02x ",((UINT8*)(p))[i*8+j]); - } - DebugPrint(EFI_D_ERROR,"\n"); - } - if(i>=128&&*(UINT64*)result->magic==0x00FFFFFFFFFFFF00uLL){return EFI_SUCCESS;} - } - return EFI_NOT_FOUND; -} - -STATIC EFI_STATUS EFIAPI i915GraphicsOutputQueryMode ( - IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, - IN UINT32 ModeNumber, - OUT UINTN *SizeOfInfo, - OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info - ) -{ - EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *ModeInfo; - DebugPrint(EFI_D_ERROR,"i915: query mode\n"); - - if (Info == NULL || SizeOfInfo == NULL || - ModeNumber >= g_mode.MaxMode) { - return EFI_INVALID_PARAMETER; - } - ModeInfo = &g_mode_info[ModeNumber]; - - *Info = AllocateCopyPool (sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), ModeInfo); - if (*Info == NULL) { - return EFI_OUT_OF_RESOURCES; - } - *SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); - - return EFI_SUCCESS; -} - -STATIC FRAME_BUFFER_CONFIGURE *g_i915FrameBufferBltConfigure=NULL; -STATIC UINTN g_i915FrameBufferBltConfigureSize=0; -STATIC INTN g_already_set=0; - -struct dpll { - /* given values */ - int n; - int m1, m2; - int p1, p2; - /* derived values */ - int dot; - int vco; - int m; - int p; -}; - -struct intel_limit { - struct { - int min, max; - } dot, vco, n, m, m1, m2, p, p1; - - struct { - int dot_limit; - int p2_slow, p2_fast; - } p2; -}; - -//intel_limits_i9xx_sdvo -//static const struct intel_limit g_limits = { -// .dot = { .min = 20000, .max = 400000 }, -// .vco = { .min = 1400000, .max = 2800000 }, -// .n = { .min = 1, .max = 6 }, -// .m = { .min = 70, .max = 120 }, -// .m1 = { .min = 8, .max = 18 }, -// .m2 = { .min = 3, .max = 7 }, -// .p = { .min = 5, .max = 80 }, -// .p1 = { .min = 1, .max = 8 }, -// .p2 = { .dot_limit = 200000, -// .p2_slow = 10, .p2_fast = 5 }, -//}; - -#define DPLL_CTRL1 (0x6C058) -#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) -#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) -#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) -#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) -#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) -#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) -#define DPLL_CTRL1_LINK_RATE_2700 0 -#define DPLL_CTRL1_LINK_RATE_1350 1 -#define DPLL_CTRL1_LINK_RATE_810 2 -#define DPLL_CTRL1_LINK_RATE_1620 3 -#define DPLL_CTRL1_LINK_RATE_1080 4 -#define DPLL_CTRL1_LINK_RATE_2160 5 - -#define DPLL_STATUS (0x6C060) -#define DPLL_LOCK(id) (1 << ((id) * 8)) - -#define LCPLL1_CTL (0x46010) -#define LCPLL2_CTL (0x46014) -#define LCPLL_PLL_ENABLE (1 << 31) - -/* DPLL cfg */ -#define _DPLL1_CFGCR1 0x6C040 -#define _DPLL2_CFGCR1 0x6C048 -#define _DPLL3_CFGCR1 0x6C050 -#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) -#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) -#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) -#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) - -#define _DPLL1_CFGCR2 0x6C044 -#define _DPLL2_CFGCR2 0x6C04C -#define _DPLL3_CFGCR2 0x6C054 -#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) -#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) -#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) -#define DPLL_CFGCR2_KDIV_MASK (3 << 5) -#define DPLL_CFGCR2_KDIV(x) ((x) << 5) -#define DPLL_CFGCR2_KDIV_5 (0 << 5) -#define DPLL_CFGCR2_KDIV_2 (1 << 5) -#define DPLL_CFGCR2_KDIV_3 (2 << 5) -#define DPLL_CFGCR2_KDIV_1 (3 << 5) -#define DPLL_CFGCR2_PDIV_MASK (7 << 2) -#define DPLL_CFGCR2_PDIV(x) ((x) << 2) -#define DPLL_CFGCR2_PDIV_1 (0 << 2) -#define DPLL_CFGCR2_PDIV_2 (1 << 2) -#define DPLL_CFGCR2_PDIV_3 (2 << 2) -#define DPLL_CFGCR2_PDIV_7 (4 << 2) -#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) - -struct skl_wrpll_params { - UINT32 dco_fraction; - UINT32 dco_integer; - UINT32 qdiv_ratio; - UINT32 qdiv_mode; - UINT32 kdiv; - UINT32 pdiv; - UINT32 central_freq; -}; - -static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, - 24, 28, 30, 32, 36, 40, 42, 44, - 48, 52, 54, 56, 60, 64, 66, 68, - 70, 72, 76, 78, 80, 84, 88, 90, - 92, 96, 98 }; -static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; -static const struct { - const int *list; - int n_dividers; -} dividers[] = { - { even_dividers, ARRAY_SIZE(even_dividers) }, - { odd_dividers, ARRAY_SIZE(odd_dividers) }, -}; - -struct skl_wrpll_context { - UINT64 min_deviation; /* current minimal deviation */ - UINT64 central_freq; /* chosen central freq */ - UINT64 dco_freq; /* chosen dco freq */ - UINT64 p; /* chosen divider */ -}; - -static void skl_wrpll_get_multipliers(UINT64 p, - UINT64 *p0 /* out */, - UINT64 *p1 /* out */, - UINT64 *p2 /* out */) -{ - /* even dividers */ - if (p % 2 == 0) { - UINT64 half = p / 2; - - if (half == 1 || half == 2 || half == 3 || half == 5) { - *p0 = 2; - *p1 = 1; - *p2 = half; - } else if (half % 2 == 0) { - *p0 = 2; - *p1 = half / 2; - *p2 = 2; - } else if (half % 3 == 0) { - *p0 = 3; - *p1 = half / 3; - *p2 = 2; - } else if (half % 7 == 0) { - *p0 = 7; - *p1 = half / 7; - *p2 = 2; - } - } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ - *p0 = 3; - *p1 = 1; - *p2 = p / 3; - } else if (p == 5 || p == 7) { - *p0 = p; - *p1 = 1; - *p2 = 1; - } else if (p == 15) { - *p0 = 3; - *p1 = 1; - *p2 = 5; - } else if (p == 21) { - *p0 = 7; - *p1 = 1; - *p2 = 3; - } else if (p == 35) { - *p0 = 7; - *p1 = 1; - *p2 = 5; - } -} +#include +#include "intel_opregion.h" -#define KHz(x) (1000 * (x)) -#define MHz(x) KHz(1000 * (x)) +i915_CONTROLLER g_private = {SIGNATURE_32('i', '9', '1', '5')}; -static void skl_wrpll_params_populate(struct skl_wrpll_params *params, - UINT64 afe_clock, - UINT64 central_freq, - UINT64 p0, UINT64 p1, UINT64 p2) +static void write32(UINT64 reg, UINT32 data) { - UINT64 dco_freq; - - switch (central_freq) { - case 9600000000ULL: - params->central_freq = 0; - break; - case 9000000000ULL: - params->central_freq = 1; - break; - case 8400000000ULL: - params->central_freq = 3; - } - - switch (p0) { - case 1: - params->pdiv = 0; - break; - case 2: - params->pdiv = 1; - break; - case 3: - params->pdiv = 2; - break; - case 7: - params->pdiv = 4; - break; - default: - DebugPrint(EFI_D_ERROR,"Incorrect PDiv\n"); - } - - switch (p2) { - case 5: - params->kdiv = 0; - break; - case 2: - params->kdiv = 1; - break; - case 3: - params->kdiv = 2; - break; - case 1: - params->kdiv = 3; - break; - default: - DebugPrint(EFI_D_ERROR,"Incorrect KDiv\n"); - } - - params->qdiv_ratio = p1; - params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; - - dco_freq = p0 * p1 * p2 * afe_clock; - - /* - * Intermediate values are in Hz. - * Divide by MHz to match bsepc - */ - params->dco_integer = (dco_freq)/(24 * MHz(1)); - params->dco_fraction = (((dco_freq)/(24) - params->dco_integer * MHz(1)) * 0x8000)/(MHz(1)); + g_private.PciIo->Mem.Write(g_private.PciIo, EfiPciIoWidthFillUint32, + PCI_BAR_IDX0, reg, 1, &data); } -/* DCO freq must be within +1%/-6% of the DCO central freq */ -#define SKL_DCO_MAX_PDEVIATION 100 -#define SKL_DCO_MAX_NDEVIATION 600 - -static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, - UINT64 central_freq, - UINT64 dco_freq, - UINT64 divider) +static UINT32 read32(UINT64 reg) { - UINT64 deviation; - INT64 abs_diff=(INT64)dco_freq-(INT64)central_freq; - if(abs_diff<0){abs_diff=-abs_diff;} - - deviation = (10000 * (UINT64)abs_diff)/(central_freq); - - /* positive deviation */ - if (dco_freq >= central_freq) { - if (deviation < SKL_DCO_MAX_PDEVIATION && - deviation < ctx->min_deviation) { - ctx->min_deviation = deviation; - ctx->central_freq = central_freq; - ctx->dco_freq = dco_freq; - ctx->p = divider; - } - /* negative deviation */ - } else if (deviation < SKL_DCO_MAX_NDEVIATION && - deviation < ctx->min_deviation) { - ctx->min_deviation = deviation; - ctx->central_freq = central_freq; - ctx->dco_freq = dco_freq; - ctx->p = divider; - } + UINT32 data = 0; + g_private.PciIo->Mem.Read(g_private.PciIo, EfiPciIoWidthFillUint32, + PCI_BAR_IDX0, reg, 1, &data); + return data; } -static UINT32 port=PORT_B; -static EFI_SYSTEM_TABLE *g_SystemTable=NULL; -STATIC EFI_STATUS EFIAPI i915GraphicsOutputSetMode ( - IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, - IN UINT32 ModeNumber - ) +static UINT64 read64(UINT64 reg) { - DebugPrint(EFI_D_ERROR,"i915: set mode %u\n",ModeNumber); - if(g_already_set){ - DebugPrint(EFI_D_ERROR,"i915: mode already set\n"); - return EFI_SUCCESS; - } - g_already_set=1; - - write32(_PIPEACONF,0); - - //setup DPLL (old GPU, doesn't apply here) - //UINT32 refclock = 96000; - //UINT32 pixel_clock = (UINT32)(g_private.edid.detailTimings[0].pixelClock) * 10; - //UINT32 multiplier = 1; - ////if(pixel_clock >= 100000) { - //// multiplier = 1; - ////}else if(pixel_clock >= 50000) { - //// multiplier = 2; - ////}else{ - //// //assert(pixel_clock >= 25000); - //// multiplier = 4; - ////} - //struct dpll final_params,params; - //INT32 target=(INT32)(pixel_clock * multiplier); - //INT32 best_err=target; - //DebugPrint(EFI_D_ERROR,"i915: before DPLL compute\n"); - //for(params.n=g_limits.n.min;params.n<=g_limits.n.max;params.n++) - //for(params.m1=g_limits.m1.max;params.m1>=g_limits.m1.min;params.m1--) - //for(params.m2=g_limits.m2.max;params.m2>=g_limits.m2.min;params.m2--) - //for(params.p1=g_limits.p1.max;params.p1>=g_limits.p1.min;params.p1--) - //for(params.p2=g_limits.p2.p2_slow;params.p2>=g_limits.p2.p2_fast;params.p2-=5){ - // if(params.p2!=5&¶ms.p2!=7&¶ms.p2!=10&¶ms.p2!=14){continue;} - // params.m = 5 * (params.m1 + 2) + (params.m2 + 2); - // params.p = params.p1*params.p2; - // if(params.m < g_limits.m.min || params.m > g_limits.m.max){continue;} - // if(params.p < g_limits.p.min || params.p > g_limits.p.max){continue;} - // params.vco = (refclock * params.m + (params.n + 2) / 2) / (params.n + 2); - // params.dot = (params.vco + params.p / 2) / params.p; - // if(params.dot < g_limits.dot.min || params.dot > g_limits.dot.max){continue;} - // if(params.vco < g_limits.vco.min || params.vco > g_limits.vco.max){continue;} - // INT32 err=(INT32)params.dot-target; - // if(err<0){err=-err;} - // if(best_err>err){ - // best_err=err; - // final_params=params; - // } - //} - - //params=final_params; - - //DebugPrint(EFI_D_ERROR,"i915: DPLL params: n=%d m1=%d m2=%d p1=%d p2=%d\n", - // params.n,params.m1,params.m2,params.p1,params.p2); - //DebugPrint(EFI_D_ERROR,"i915: DPLL params: m=%d p=%d vco=%d dot=%d, target=%d\n", - // params.m,params.p,params.vco,params.dot,target); - - //write32(_FPA0, params.n << 16 | params.m1 << 8 | params.m2); - //write32(_FPA1, params.n << 16 | params.m1 << 8 | params.m2); - - //write32(_DPLL_A, 0); - - ////UINT32 dplla=DPLLB_MODE_DAC_SERIAL | DPLL_VGA_MODE_DIS | DPLL_SDVO_HIGH_SPEED | DPLL_VCO_ENABLE; - //UINT32 dplla=DPLLB_MODE_DAC_SERIAL | DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE; - //dplla |= (1 << (params.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; - //switch (params.p2) { - //case 5: - // dplla |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; - // break; - //case 7: - // dplla |= DPLLB_LVDS_P2_CLOCK_DIV_7; - // break; - //case 10: - // dplla |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; - // break; - //case 14: - // dplla |= DPLLB_LVDS_P2_CLOCK_DIV_14; - // break; - //} - //dplla |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); - ////this is 0 anyway - //dplla |= PLL_REF_INPUT_DREFCLK; - - //write32(_DPLL_A, dplla); - //read32(_DPLL_A); - //DebugPrint(EFI_D_ERROR,"i915: DPLL set %08x, read %08x\n",dplla,read32(_DPLL_A)); - - ////it's pointless to wait in GVT-g - //if(!g_private.is_gvt){ - // //MicroSecondDelay is unusable - // for(UINT32 counter=0;counter<16384;counter++){ - // read32(_DPLL_A); - // } - //} - - //write32(_DPLL_A_MD, (multiplier-1)<>1 >=135000){ - // id=DPLL_CTRL1_LINK_RATE_1350; - //}else if(clock_khz>>1 >=270000){ - // id=DPLL_CTRL1_LINK_RATE_2700; - //} - //hack: anything else hangs - UINT32 id=DPLL_CTRL1_LINK_RATE_1350; - - val &= ~(DPLL_CTRL1_HDMI_MODE(id) | - DPLL_CTRL1_SSC(id) | - DPLL_CTRL1_LINK_RATE_MASK(id)); - val |= ctrl1 << (id * 6); - - //DPLL 1 - write32(DPLL_CTRL1, val); - read32(DPLL_CTRL1); - - write32(_DPLL1_CFGCR1, cfgcr1); - write32(_DPLL1_CFGCR2, cfgcr2); - read32(_DPLL1_CFGCR1); - read32(_DPLL1_CFGCR2); - - //845 80400173 3a5 - DebugPrint(EFI_D_ERROR,"i915: DPLL_CTRL1 = %08x\n", read32(DPLL_CTRL1)); - DebugPrint(EFI_D_ERROR,"i915: _DPLL1_CFGCR1 = %08x\n", read32(_DPLL1_CFGCR1)); - DebugPrint(EFI_D_ERROR,"i915: _DPLL1_CFGCR2 = %08x\n", read32(_DPLL1_CFGCR2)); - - /* the enable bit is always bit 31 */ - write32(LCPLL2_CTL, read32(LCPLL2_CTL) | LCPLL_PLL_ENABLE); - - for(UINT32 counter=0;;counter++){ - if(read32(DPLL_STATUS)&DPLL_LOCK(1)){ - DebugPrint(EFI_D_ERROR,"i915: DPLL %d locked\n", 1); - break; - } - if(counter>16384){ - DebugPrint(EFI_D_ERROR,"i915: DPLL %d not locked\n", 1); - break; - } - } - - //intel_encoders_pre_enable(crtc, pipe_config, old_state); - //could be intel_ddi_pre_enable_hdmi - //intel_ddi_clk_select(encoder, crtc_state); - DebugPrint(EFI_D_ERROR,"i915: port is %d\n", port); - { - UINT32 val = read32(DPLL_CTRL2); - - //val &= ~(DPLL_CTRL2_DDI_CLK_OFF(PORT_A) | - // DPLL_CTRL2_DDI_CLK_SEL_MASK(PORT_A)); - //val |= (DPLL_CTRL2_DDI_CLK_SEL(id, PORT_A) | - // DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_A)); - - val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | - DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); - val |= (DPLL_CTRL2_DDI_CLK_SEL(id, port) | - DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); - - write32(DPLL_CTRL2, val); - } - DebugPrint(EFI_D_ERROR,"i915: DPLL_CTRL2 = %08x\n", read32(DPLL_CTRL2)); - - //intel_prepare_hdmi_ddi_buffers(encoder, level); - //the driver doesn't seem to do this for port A - write32(DDI_BUF_TRANS_LO(port, 9), 0x80003015u); - write32(DDI_BUF_TRANS_HI(port, 9), 0xcdu); - - //intel_hdmi_prepare(encoder, pipe_config); - //hdmi_reg=DDI_BUF_CTL(port) - - DebugPrint(EFI_D_ERROR,"i915: progressed to line %d\n", __LINE__); - - //it's Type C - //icl_enable_phy_clock_gating(dig_port); - - //if (IS_GEN9_BC(dev_priv)) - // skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); - { - UINT32 tmp; - - tmp = read32(DISPIO_CR_TX_BMU_CR0); - tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); - tmp |= 1 << BALANCE_LEG_SHIFT(port); - write32(DISPIO_CR_TX_BMU_CR0, tmp); - } - - //intel_ddi_enable_pipe_clock(crtc_state); - write32(_TRANS_CLK_SEL_A, TRANS_CLK_SEL_PORT(port)); - DebugPrint(EFI_D_ERROR,"i915: progressed to line %d, TRANS_CLK_SEL_PORT(port) is %08x\n", __LINE__, TRANS_CLK_SEL_PORT(port)); - - //we got here - - //intel_dig_port->set_infoframes(encoder, - // crtc_state->has_infoframe, - // crtc_state, conn_state); - - //if (intel_crtc_has_dp_encoder(pipe_config)) - // intel_dp_set_m_n(pipe_config, M1_N1); - - //program PIPE_A - UINT32 horz_active = g_private.edid.detailTimings[0].horzActive - | ((UINT32)(g_private.edid.detailTimings[0].horzActiveBlankMsb >> 4) << 8); - UINT32 horz_blank = g_private.edid.detailTimings[0].horzBlank - | ((UINT32)(g_private.edid.detailTimings[0].horzActiveBlankMsb & 0xF) << 8); - UINT32 horz_sync_offset = g_private.edid.detailTimings[0].horzSyncOffset - | ((UINT32)(g_private.edid.detailTimings[0].syncMsb >> 6) << 8); - UINT32 horz_sync_pulse = g_private.edid.detailTimings[0].horzSyncPulse - | (((UINT32)(g_private.edid.detailTimings[0].syncMsb >> 4) & 0x3) << 8); - - UINT32 horizontal_active = horz_active; - UINT32 horizontal_syncStart = horz_active + horz_sync_offset; - UINT32 horizontal_syncEnd = horz_active + horz_sync_offset + horz_sync_pulse; - UINT32 horizontal_total = horz_active + horz_blank; - - UINT32 vert_active = g_private.edid.detailTimings[0].vertActive - | ((UINT32)(g_private.edid.detailTimings[0].vertActiveBlankMsb >> 4) << 8); - UINT32 vert_blank = g_private.edid.detailTimings[0].vertBlank - | ((UINT32)(g_private.edid.detailTimings[0].vertActiveBlankMsb & 0xF) << 8); - UINT32 vert_sync_offset = (g_private.edid.detailTimings[0].vertSync >> 4) - | (((UINT32)(g_private.edid.detailTimings[0].syncMsb >> 2) & 0x3) << 4); - UINT32 vert_sync_pulse = (g_private.edid.detailTimings[0].vertSync & 0xF) - | ((UINT32)(g_private.edid.detailTimings[0].syncMsb & 0x3) << 4); - - UINT32 vertical_active = vert_active; - UINT32 vertical_syncStart = vert_active + vert_sync_offset; - UINT32 vertical_syncEnd = vert_active + vert_sync_offset + vert_sync_pulse; - UINT32 vertical_total = vert_active + vert_blank; - - write32(VSYNCSHIFT_A, 0); - - write32(HTOTAL_A, - (horizontal_active - 1) | - ((horizontal_total - 1) << 16)); - write32(HBLANK_A, - (horizontal_active - 1) | - ((horizontal_total - 1) << 16)); - write32(HSYNC_A, - (horizontal_syncStart - 1) | - ((horizontal_syncEnd - 1) << 16)); - - write32(VTOTAL_A, - (vertical_active - 1) | - ((vertical_total - 1) << 16)); - write32(VBLANK_A, - (vertical_active - 1) | - ((vertical_total - 1) << 16)); - write32(VSYNC_A, - (vertical_syncStart - 1) | - ((vertical_syncEnd - 1) << 16)); - - write32(PIPEASRC,((horizontal_active-1)<<16)|(vertical_active-1)); - UINT32 multiplier=1; - write32(PIPE_MULT_A, multiplier - 1); - - DebugPrint(EFI_D_ERROR,"i915: HTOTAL_A (%x) = %08x\n",HTOTAL_A,read32(HTOTAL_A)); - DebugPrint(EFI_D_ERROR,"i915: HBLANK_A (%x) = %08x\n",HBLANK_A,read32(HBLANK_A)); - DebugPrint(EFI_D_ERROR,"i915: HSYNC_A (%x) = %08x\n",HSYNC_A,read32(HSYNC_A)); - DebugPrint(EFI_D_ERROR,"i915: VTOTAL_A (%x) = %08x\n",VTOTAL_A,read32(VTOTAL_A)); - DebugPrint(EFI_D_ERROR,"i915: VBLANK_A (%x) = %08x\n",VBLANK_A,read32(VBLANK_A)); - DebugPrint(EFI_D_ERROR,"i915: VSYNC_A (%x) = %08x\n",VSYNC_A,read32(VSYNC_A)); - DebugPrint(EFI_D_ERROR,"i915: PIPEASRC (%x) = %08x\n",PIPEASRC,read32(PIPEASRC)); - DebugPrint(EFI_D_ERROR,"i915: BCLRPAT_A (%x) = %08x\n",BCLRPAT_A,read32(BCLRPAT_A)); - DebugPrint(EFI_D_ERROR,"i915: VSYNCSHIFT_A (%x) = %08x\n",VSYNCSHIFT_A,read32(VSYNCSHIFT_A)); - DebugPrint(EFI_D_ERROR,"i915: PIPE_MULT_A (%x) = %08x\n",PIPE_MULT_A,read32(PIPE_MULT_A)); - - DebugPrint(EFI_D_ERROR,"i915: before pipe gamma\n"); - - //intel_color_load_luts(pipe_config); - //intel_color_commit(pipe_config); - DebugPrint(EFI_D_ERROR,"i915: before gamma\n"); - for (UINT32 i = 0; i < 256; i++) { - UINT32 word = (i << 16) | (i << 8) | i; - write32(_LGC_PALETTE_A+i*4, word); - } - DebugPrint(EFI_D_ERROR,"i915: before pipe gamma\n"); - //DebugPrint(EFI_D_ERROR,"i915: _PIPEACONF: %08x\n",read32(_PIPEACONF)); - //g_SystemTable->RuntimeServices->ResetSystem(EfiResetShutdown,0,0,NULL); - //return EFI_UNSUPPORTED; - write32(_PIPEACONF,PIPECONF_PROGRESSIVE|PIPECONF_GAMMA_MODE_8BIT); - //write32(_SKL_BOTTOM_COLOR_A,SKL_BOTTOM_COLOR_GAMMA_ENABLE); - //write32(_SKL_BOTTOM_COLOR_A,0); - //write32(_SKL_BOTTOM_COLOR_A,0x335577); - write32(_SKL_BOTTOM_COLOR_A,0); - write32(_GAMMA_MODE_A,GAMMA_MODE_MODE_8BIT); - - //bad setup causes hanging when enabling trans / pipe, but what is it? - //we got here - //ddi - DebugPrint(EFI_D_ERROR,"i915: before DDI\n"); - write32(_TRANSA_MSA_MISC, TRANS_MSA_SYNC_CLK|TRANS_MSA_8_BPC); - write32(_TRANS_DDI_FUNC_CTL_A, ( - TRANS_DDI_FUNC_ENABLE|TRANS_DDI_SELECT_PORT(port)|TRANS_DDI_PHSYNC|TRANS_DDI_PVSYNC|TRANS_DDI_BPC_8|TRANS_DDI_MODE_SELECT_HDMI - )); - DebugPrint(EFI_D_ERROR,"i915: after DDI\n"); - //g_SystemTable->RuntimeServices->ResetSystem(EfiResetShutdown,0,0,NULL); - //return EFI_UNSUPPORTED; - - //test: could be Windows hanging, it's not - //g_SystemTable->RuntimeServices->ResetSystem(EfiResetShutdown,0,0,NULL); - //we failed here - //return EFI_UNSUPPORTED; - - write32(_PIPEACONF,PIPECONF_ENABLE|PIPECONF_PROGRESSIVE|PIPECONF_GAMMA_MODE_8BIT); - UINT32 counter=0; - for(;;){ - counter+=1; - if(counter>=16384){ - DebugPrint(EFI_D_ERROR,"i915: failed to enable PIPE\n"); - break; - } - if(read32(_PIPEACONF)&I965_PIPECONF_ACTIVE){ - DebugPrint(EFI_D_ERROR,"i915: pipe enabled\n"); - break; - } - } - - //if (pipe_config->has_pch_encoder) - // lpt_pch_enable(old_intel_state, pipe_config); - - //if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) - // intel_ddi_set_vc_payload_alloc(pipe_config, true); - - //intel_encoders_enable(crtc, pipe_config, old_state); - /* Display WA #1143: skl,kbl,cfl */ - UINT32 saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); - - //if (IS_GEN9_BC(dev_priv)) - { - /* - * For some reason these chicken bits have been - * stuffed into a transcoder register, event though - * the bits affect a specific DDI port rather than - * a specific transcoder. - */ - UINT32 reg = CHICKEN_TRANS_A; - if(port==PORT_B){reg = CHICKEN_TRANS_A;} - if(port==PORT_C){reg = CHICKEN_TRANS_B;} - if(port==PORT_D){reg = CHICKEN_TRANS_C;} - //if(port==PORT_E){reg = CHICKEN_TRANS_A;} - UINT32 val; - - val = I915_READ(reg); - - if (port == PORT_E) - val |= DDIE_TRAINING_OVERRIDE_ENABLE | - DDIE_TRAINING_OVERRIDE_VALUE; - else - val |= DDI_TRAINING_OVERRIDE_ENABLE | - DDI_TRAINING_OVERRIDE_VALUE; - - I915_WRITE(reg, val); - read32(reg); - - //... don't have timer - for(UINT32 counter=0;;){ - read32(reg); - counter+=1; - if(counter>=16384){ - break; - } - } - //udelay(1); - - if (port == PORT_E) - val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | - DDIE_TRAINING_OVERRIDE_VALUE); - else - val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | - DDI_TRAINING_OVERRIDE_VALUE); - - I915_WRITE(reg, val); - } - - /* In HDMI/DVI mode, the port width, and swing/emphasis values - * are ignored so nothing special needs to be done besides - * enabling the port. - */ - I915_WRITE(DDI_BUF_CTL(port), saved_port_bits | DDI_BUF_CTL_ENABLE); - DebugPrint(EFI_D_ERROR,"DDI_BUF_CTL(port) = %08x\n",read32(DDI_BUF_CTL(port))); - - //plane - UINT32 stride=(horizontal_active*4+63)&-64; - g_private.stride=stride; - write32(_DSPAOFFSET,0); - write32(_DSPAPOS,0); - write32(_DSPASTRIDE,stride>>6); - write32(_DSPASIZE,(horizontal_active - 1) | ((vertical_active-1)<<16)); - write32(_DSPACNTR,DISPLAY_PLANE_ENABLE|PLANE_CTL_FORMAT_XRGB_8888|PLANE_CTL_PLANE_GAMMA_DISABLE); - write32(_DSPASURF,g_private.gmadr); - - //write32(_DSPAADDR,0); - //word=read32(_DSPACNTR); - //write32(_DSPACNTR,(word&~PLANE_CTL_FORMAT_MASK)|DISPLAY_PLANE_ENABLE|PLANE_CTL_FORMAT_XRGB_8888); - //|PLANE_CTL_ORDER_RGBX - g_mode.FrameBufferBase=g_private.FbBase; - g_mode.FrameBufferSize=stride*vertical_active; - - //test pattern - //there is just one page wrapping around... why? - //we have intel_vgpu_mmap in effect so the correct range is mmaped host vmem - //and the host vmem is actually one-page! - //((UINT32*)g_private.FbBase)[-1]=0x00010203; - //there is a mechanism called `get_pages` that seems to put main memory behind the aperture or sth - //the page is the scratch page that unmapped GTT entries point to - //we need to set up a GTT for our framebuffer: https://bwidawsk.net/blog/index.php/2014/06/the-global-gtt-part-1/ - //UINT32 cnt=0; - //for(cnt=0;cnt<256*16;cnt++){ - // ((UINT32*)g_private.FbBase)[cnt]=0x00010203; - //} - //for(cnt=0;cnt<256*4;cnt++){ - // UINT32 c=cnt&255; - // ((UINT32*)g_private.FbBase)[cnt]=((cnt+256)&256?c:0)+((cnt+256)&512?c<<8:0)+((cnt+256)&1024?c<<16:0); - //} - //DebugPrint(EFI_D_ERROR,"i915: wrap test %08x %08x %08x %08x\n",((UINT32*)g_private.FbBase)[1024],((UINT32*)g_private.FbBase)[1025],((UINT32*)g_private.FbBase)[1026],((UINT32*)g_private.FbBase)[1027]); - //// - //UINT32 cnt=0; - //for(UINT32 y=0;yMem.Read(g_private.PciIo, EfiPciIoWidthFillUint64, + PCI_BAR_IDX0, reg, 1, &data); + return data; } -STATIC EFI_STATUS EFIAPI i915GraphicsOutputBlt ( - IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, - IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL - IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, - IN UINTN SourceX, - IN UINTN SourceY, - IN UINTN DestinationX, - IN UINTN DestinationY, - IN UINTN Width, - IN UINTN Height, - IN UINTN Delta - ) -{ - EFI_STATUS Status=FrameBufferBlt ( - g_i915FrameBufferBltConfigure, - BltBuffer, - BltOperation, - SourceX, - SourceY, - DestinationX, - DestinationY, - Width, - Height, - Delta - ); - DebugPrint(EFI_D_ERROR,"i915: blt %d %d,%d %dx%d\n",Status,DestinationX,DestinationY,Width,Height); - return Status; -} - // // selector and size of ASSIGNED_IGD_FW_CFG_OPREGION // STATIC FIRMWARE_CONFIG_ITEM mOpRegionItem; -STATIC UINTN mOpRegionSize; +STATIC UINTN mOpRegionSize; // // value read from ASSIGNED_IGD_FW_CFG_BDSM_SIZE, converted to UINTN // -STATIC UINTN mBdsmSize; +STATIC UINTN mBdsmSize; /** Allocate memory in the 32-bit address space, with the requested UEFI memory @@ -1833,36 +84,37 @@ STATIC UINTN mBdsmSize; **/ STATIC EFI_STATUS -Allocate32BitAlignedPagesWithType ( - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN NumberOfPages, - IN UINTN AlignmentInPages, - OUT EFI_PHYSICAL_ADDRESS *Address - ) +Allocate32BitAlignedPagesWithType(IN EFI_MEMORY_TYPE MemoryType, + IN UINTN NumberOfPages, + IN UINTN AlignmentInPages, + OUT EFI_PHYSICAL_ADDRESS *Address) { - EFI_STATUS Status; + EFI_STATUS Status; EFI_PHYSICAL_ADDRESS PageAlignedAddress; EFI_PHYSICAL_ADDRESS FullyAlignedAddress; - UINTN BottomPages; - UINTN TopPages; + UINTN BottomPages; + UINTN TopPages; // // AlignmentInPages must be a power of two. // if (AlignmentInPages == 0 || - (AlignmentInPages & (AlignmentInPages - 1)) != 0) { + (AlignmentInPages & (AlignmentInPages - 1)) != 0) + { return EFI_INVALID_PARAMETER; } // // (NumberOfPages + (AlignmentInPages - 1)) must not overflow UINTN. // - if (AlignmentInPages - 1 > MAX_UINTN - NumberOfPages) { + if (AlignmentInPages - 1 > MAX_UINTN - NumberOfPages) + { return EFI_OUT_OF_RESOURCES; } // // EFI_PAGES_TO_SIZE (AlignmentInPages) must not overflow UINTN. // - if (AlignmentInPages > (MAX_UINTN >> EFI_PAGE_SHIFT)) { + if (AlignmentInPages > (MAX_UINTN >> EFI_PAGE_SHIFT)) + { return EFI_OUT_OF_RESOURCES; } @@ -1870,56 +122,56 @@ Allocate32BitAlignedPagesWithType ( // Allocate with sufficient padding for alignment. // PageAlignedAddress = BASE_4GB - 1; - //PageAlignedAddress = BASE_2GB - 1; - Status = gBS->AllocatePages ( - AllocateMaxAddress, - MemoryType, - NumberOfPages + (AlignmentInPages - 1), - &PageAlignedAddress - ); - if (EFI_ERROR (Status)) { + // PageAlignedAddress = BASE_2GB - 1; + Status = gBS->AllocatePages(AllocateMaxAddress, MemoryType, + NumberOfPages + (AlignmentInPages - 1), + &PageAlignedAddress); + if (EFI_ERROR(Status)) + { return Status; } - FullyAlignedAddress = ALIGN_VALUE ( - PageAlignedAddress, - (UINT64)EFI_PAGES_TO_SIZE (AlignmentInPages) - ); + FullyAlignedAddress = ALIGN_VALUE( + PageAlignedAddress, (UINT64)EFI_PAGES_TO_SIZE(AlignmentInPages)); // // Release bottom and/or top padding. // - BottomPages = EFI_SIZE_TO_PAGES ( - (UINTN)(FullyAlignedAddress - PageAlignedAddress) - ); + BottomPages = + EFI_SIZE_TO_PAGES((UINTN)(FullyAlignedAddress - PageAlignedAddress)); TopPages = (AlignmentInPages - 1) - BottomPages; - if (BottomPages > 0) { - Status = gBS->FreePages (PageAlignedAddress, BottomPages); - ASSERT_EFI_ERROR (Status); + if (BottomPages > 0) + { + Status = gBS->FreePages(PageAlignedAddress, BottomPages); + ASSERT_EFI_ERROR(Status); } - if (TopPages > 0) { - Status = gBS->FreePages ( - FullyAlignedAddress + EFI_PAGES_TO_SIZE (NumberOfPages), - TopPages - ); - ASSERT_EFI_ERROR (Status); + if (TopPages > 0) + { + Status = gBS->FreePages( + FullyAlignedAddress + EFI_PAGES_TO_SIZE(NumberOfPages), TopPages); + ASSERT_EFI_ERROR(Status); } *Address = FullyAlignedAddress; return EFI_SUCCESS; } -//CHAR8 OPREGION_SIGNATURE[]="IntelGraphicsMem"; +// CHAR8 OPREGION_SIGNATURE[]="IntelGraphicsMem"; -typedef struct { +typedef struct +{ UINT16 VendorId; - UINT8 ClassCode[3]; - UINTN Segment; - UINTN Bus; - UINTN Device; - UINTN Function; - CHAR8 Name[sizeof "0000:00:02.0"]; + UINT8 ClassCode[3]; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + CHAR8 Name[sizeof "0000:00:02.0"]; } CANDIDATE_PCI_INFO; +STATIC CHAR8 *GetPciName(IN CANDIDATE_PCI_INFO *PciInfo) +{ + return PciInfo->Name; +} /** Populate the CANDIDATE_PCI_INFO structure for a PciIo protocol instance. @@ -1937,43 +189,29 @@ typedef struct { **/ STATIC EFI_STATUS -InitPciInfo ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - OUT CANDIDATE_PCI_INFO *PciInfo - ) +InitPciInfo(IN EFI_PCI_IO_PROTOCOL *PciIo, OUT CANDIDATE_PCI_INFO *PciInfo) { EFI_STATUS Status; - Status = PciIo->Pci.Read ( - PciIo, - EfiPciIoWidthUint16, - PCI_VENDOR_ID_OFFSET, - 1, // Count - &PciInfo->VendorId - ); - if (EFI_ERROR (Status)) { + Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, + 1, // Count + &PciInfo->VendorId); + if (EFI_ERROR(Status)) + { return Status; } - Status = PciIo->Pci.Read ( - PciIo, - EfiPciIoWidthUint8, - PCI_CLASSCODE_OFFSET, - sizeof PciInfo->ClassCode, - PciInfo->ClassCode - ); - if (EFI_ERROR (Status)) { + Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint8, PCI_CLASSCODE_OFFSET, + sizeof PciInfo->ClassCode, PciInfo->ClassCode); + if (EFI_ERROR(Status)) + { return Status; } - Status = PciIo->GetLocation ( - PciIo, - &PciInfo->Segment, - &PciInfo->Bus, - &PciInfo->Device, - &PciInfo->Function - ); - if (EFI_ERROR (Status)) { + Status = PciIo->GetLocation(PciIo, &PciInfo->Segment, &PciInfo->Bus, + &PciInfo->Device, &PciInfo->Function); + if (EFI_ERROR(Status)) + { return Status; } @@ -1981,7 +219,7 @@ InitPciInfo ( return EFI_SUCCESS; } -#define ASSIGNED_IGD_FW_CFG_OPREGION "etc/igd-opregion" +#define ASSIGNED_IGD_FW_CFG_OPREGION "etc/igd-opregion" #define ASSIGNED_IGD_FW_CFG_BDSM_SIZE "etc/igd-bdsm-size" // @@ -2001,9 +239,9 @@ InitPciInfo ( // // PCI location and vendor // -#define ASSIGNED_IGD_PCI_BUS 0x00 -#define ASSIGNED_IGD_PCI_DEVICE 0x02 -#define ASSIGNED_IGD_PCI_FUNCTION 0x0 +#define ASSIGNED_IGD_PCI_BUS 0x00 +#define ASSIGNED_IGD_PCI_DEVICE 0x02 +#define ASSIGNED_IGD_PCI_FUNCTION 0x0 #define ASSIGNED_IGD_PCI_VENDOR_ID 0x8086 /** @@ -2024,36 +262,34 @@ InitPciInfo ( **/ STATIC EFI_STATUS -SetupOpRegion ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN OUT CANDIDATE_PCI_INFO *PciInfo - ) +SetupOpRegion(IN EFI_PCI_IO_PROTOCOL *PciIo, + IN OUT CANDIDATE_PCI_INFO *PciInfo) { - UINTN OpRegionPages; - UINTN OpRegionResidual; - EFI_STATUS Status; + UINTN OpRegionPages; + UINTN OpRegionResidual; + EFI_STATUS Status; EFI_PHYSICAL_ADDRESS Address; - UINT8 *BytePointer; - - if (mOpRegionSize == 0) { + UINT8 *BytePointer; + struct intel_opregion OpRegion; + if (mOpRegionSize == 0) + { return EFI_INVALID_PARAMETER; } - OpRegionPages = EFI_SIZE_TO_PAGES (mOpRegionSize<8192?8192:mOpRegionSize); - OpRegionResidual = EFI_PAGES_TO_SIZE (OpRegionPages) - mOpRegionSize; + OpRegionPages = + EFI_SIZE_TO_PAGES(mOpRegionSize < 8192 ? 8192 : mOpRegionSize); + OpRegionResidual = EFI_PAGES_TO_SIZE(OpRegionPages) - mOpRegionSize; // // While QEMU's "docs/igd-assign.txt" specifies reserved memory, Intel's IGD // OpRegion spec refers to ACPI NVS. // - Status = Allocate32BitAlignedPagesWithType ( - EfiACPIMemoryNVS, - OpRegionPages, - 1, // AlignmentInPages - &Address - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: %a: failed to allocate OpRegion: %r\n", - __FUNCTION__, GetPciName (PciInfo), Status)); + Status = Allocate32BitAlignedPagesWithType(EfiACPIMemoryNVS, OpRegionPages, + 1, // AlignmentInPages + &Address); + if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR, "%a: %a: failed to allocate OpRegion: %r\n", + __FUNCTION__, GetPciName(PciInfo), Status); return Status; } @@ -2061,43 +297,54 @@ SetupOpRegion ( // Download OpRegion contents from fw_cfg, zero out trailing portion. // BytePointer = (UINT8 *)(UINTN)Address; - QemuFwCfgSelectItem (mOpRegionItem); - QemuFwCfgReadBytes (mOpRegionSize, BytePointer); - if(OpRegionResidual){ - ZeroMem (BytePointer + mOpRegionSize, OpRegionResidual); + QemuFwCfgSelectItem(mOpRegionItem); + QemuFwCfgReadBytes(mOpRegionSize, BytePointer); + if (OpRegionResidual) + { + ZeroMem(BytePointer + mOpRegionSize, OpRegionResidual); } - - //for(int i=0;iPci.Write ( - PciIo, - EfiPciIoWidthUint32, - ASSIGNED_IGD_PCI_ASLS_OFFSET, - 1, // Count - &Address - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: %a: failed to write OpRegion address: %r\n", - __FUNCTION__, GetPciName (PciInfo), Status)); + Status = + PciIo->Pci.Write(PciIo, EfiPciIoWidthUint32, ASSIGNED_IGD_PCI_ASLS_OFFSET, + 1, // Count + &Address); + if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR, "%a: %a: failed to write OpRegion address: %r\n", + __FUNCTION__, GetPciName(PciInfo), Status); goto FreeOpRegion; } - DebugPrint(EFI_D_ERROR, "i915: %a: OpRegion @ 0x%Lx size 0x%Lx in %d pages\n", __FUNCTION__, - Address, (UINT64)mOpRegionSize,(int)OpRegionPages); + PRINT_DEBUG(EFI_D_ERROR, "%a: OpRegion @ 0x%Lx size 0x%Lx in %d pages\n", + __FUNCTION__, Address, (UINT64)mOpRegionSize, (int)OpRegionPages); return EFI_SUCCESS; FreeOpRegion: - gBS->FreePages (Address, OpRegionPages); + gBS->FreePages(Address, OpRegionPages); return Status; } - /** Set up stolen memory for the device identified by PciIo. @@ -2116,703 +363,591 @@ SetupOpRegion ( **/ STATIC EFI_STATUS -SetupStolenMemory ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN OUT CANDIDATE_PCI_INFO *PciInfo - ) +SetupStolenMemory(IN EFI_PCI_IO_PROTOCOL *PciIo, + IN OUT CANDIDATE_PCI_INFO *PciInfo) { - UINTN BdsmPages; - EFI_STATUS Status; + UINTN BdsmPages; + EFI_STATUS Status; EFI_PHYSICAL_ADDRESS Address; - if (mBdsmSize == 0) { + if (mBdsmSize == 0) + { return EFI_INVALID_PARAMETER; } - BdsmPages = EFI_SIZE_TO_PAGES (mBdsmSize); - - Status = Allocate32BitAlignedPagesWithType ( - EfiReservedMemoryType,// - BdsmPages, - EFI_SIZE_TO_PAGES ((UINTN)ASSIGNED_IGD_BDSM_ALIGN), - &Address - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: %a: failed to allocate stolen memory: %r\n", - __FUNCTION__, GetPciName (PciInfo), Status)); + BdsmPages = EFI_SIZE_TO_PAGES(mBdsmSize); + + Status = Allocate32BitAlignedPagesWithType( + EfiReservedMemoryType, // + BdsmPages, EFI_SIZE_TO_PAGES((UINTN)ASSIGNED_IGD_BDSM_ALIGN), &Address); + if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR, "%a: %a: failed to allocate stolen memory: %r\n", + __FUNCTION__, GetPciName(PciInfo), Status); return Status; } // // Zero out stolen memory. // - ZeroMem ((VOID *)(UINTN)Address, EFI_PAGES_TO_SIZE (BdsmPages)); + ZeroMem((VOID *)(UINTN)Address, EFI_PAGES_TO_SIZE(BdsmPages)); // // Write address of stolen memory to PCI config space. // - Status = PciIo->Pci.Write ( - PciIo, - EfiPciIoWidthUint32, - ASSIGNED_IGD_PCI_BDSM_OFFSET, - 1, // Count - &Address - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: %a: failed to write stolen memory address: %r\n", - __FUNCTION__, GetPciName (PciInfo), Status)); + Status = + PciIo->Pci.Write(PciIo, EfiPciIoWidthUint32, ASSIGNED_IGD_PCI_BDSM_OFFSET, + 1, // Count + &Address); + if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR, "%a: %a: failed to write stolen memory address: %r\n", + __FUNCTION__, GetPciName(PciInfo), Status); goto FreeStolenMemory; } - DEBUG ((DEBUG_INFO, "%a: %a: stolen memory @ 0x%Lx size 0x%Lx\n", - __FUNCTION__, GetPciName (PciInfo), Address, (UINT64)mBdsmSize)); + PRINT_DEBUG(EFI_D_ERROR, "%a: %a: stolen memory @ 0x%Lx size 0x%Lx\n", __FUNCTION__, + GetPciName(PciInfo), Address, (UINT64)mBdsmSize); return EFI_SUCCESS; FreeStolenMemory: - gBS->FreePages (Address, BdsmPages); + gBS->FreePages(Address, BdsmPages); return Status; } -STATIC UINT8 edid_fallback[]={ - //generic 1280x720 - 0,255,255,255,255,255,255,0,34,240,84,41,1,0,0,0,4,23,1,4,165,52,32,120,35,252,129,164,85,77,157,37,18,80,84,33,8,0,209,192,129,192,129,64,129,128,149,0,169,64,179,0,1,1,26,29,0,128,81,208,28,32,64,128,53,0,77,187,16,0,0,30,0,0,0,254,0,55,50,48,112,32,32,32,32,32,32,32,32,10,0,0,0,253,0,24,60,24,80,17,0,10,32,32,32,32,32,32,0,0,0,252,0,72,80,32,90,82,95,55,50,48,112,10,32,32,0,161 - //the test monitor - //0,255,255,255,255,255,255,0,6,179,192,39,141,30,0,0,49,26,1,3,128,60,34,120,42,83,165,167,86,82,156,38,17,80,84,191,239,0,209,192,179,0,149,0,129,128,129,64,129,192,113,79,1,1,2,58,128,24,113,56,45,64,88,44,69,0,86,80,33,0,0,30,0,0,0,255,0,71,67,76,77,84,74,48,48,55,56,50,49,10,0,0,0,253,0,50,75,24,83,17,0,10,32,32,32,32,32,32,0,0,0,252,0,65,83,85,83,32,86,90,50,55,57,10,32,32,1,153,2,3,34,113,79,1,2,3,17,18,19,4,20,5,14,15,29,30,31,144,35,9,23,7,131,1,0,0,101,3,12,0,32,0,140,10,208,138,32,224,45,16,16,62,150,0,86,80,33,0,0,24,1,29,0,114,81,208,30,32,110,40,85,0,86,80,33,0,0,30,1,29,0,188,82,208,30,32,184,40,85,64,86,80,33,0,0,30,140,10,208,144,32,64,49,32,12,64,85,0,86,80,33,0,0,24,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,237 -}; +STATIC EFI_STATUS SetupFwcfgStuff(EFI_PCI_IO_PROTOCOL *PciIo) +{ + EFI_STATUS OpRegionStatus = QemuFwCfgFindFile(ASSIGNED_IGD_FW_CFG_OPREGION, + &mOpRegionItem, &mOpRegionSize); + FIRMWARE_CONFIG_ITEM BdsmItem; + UINTN BdsmItemSize; + EFI_STATUS BdsmStatus = QemuFwCfgFindFile(ASSIGNED_IGD_FW_CFG_BDSM_SIZE, + &BdsmItem, &BdsmItemSize); + // + // If neither fw_cfg file is available, assume no IGD is assigned. + // -STATIC EFI_STATUS SetupFwcfgStuff(EFI_PCI_IO_PROTOCOL *PciIo){ - EFI_STATUS OpRegionStatus = QemuFwCfgFindFile ( - ASSIGNED_IGD_FW_CFG_OPREGION, - &mOpRegionItem, - &mOpRegionSize - ); - FIRMWARE_CONFIG_ITEM BdsmItem; - UINTN BdsmItemSize; - EFI_STATUS BdsmStatus = QemuFwCfgFindFile ( - ASSIGNED_IGD_FW_CFG_BDSM_SIZE, - &BdsmItem, - &BdsmItemSize - ); - // - // If neither fw_cfg file is available, assume no IGD is assigned. - // - if (EFI_ERROR (OpRegionStatus) && EFI_ERROR (BdsmStatus)) { - return EFI_UNSUPPORTED; - } - - // - // Require all fw_cfg files that are present to be well-formed. - // - if (!EFI_ERROR (OpRegionStatus) && mOpRegionSize == 0) { - DEBUG ((DEBUG_ERROR, "%a: %a: zero size\n", __FUNCTION__, - ASSIGNED_IGD_FW_CFG_OPREGION)); - return EFI_PROTOCOL_ERROR; - } - - if (!EFI_ERROR (BdsmStatus)) { - UINT64 BdsmSize; - - if (BdsmItemSize != sizeof BdsmSize) { - DEBUG ((DEBUG_ERROR, "%a: %a: invalid fw_cfg size: %Lu\n", __FUNCTION__, - ASSIGNED_IGD_FW_CFG_BDSM_SIZE, (UINT64)BdsmItemSize)); - return EFI_PROTOCOL_ERROR; - } - QemuFwCfgSelectItem (BdsmItem); - QemuFwCfgReadBytes (BdsmItemSize, &BdsmSize); - - if (BdsmSize == 0 || BdsmSize > MAX_UINTN) { - DEBUG ((DEBUG_ERROR, "%a: %a: invalid value: %Lu\n", __FUNCTION__, - ASSIGNED_IGD_FW_CFG_BDSM_SIZE, BdsmSize)); - return EFI_PROTOCOL_ERROR; - } - DEBUG((DEBUG_INFO,"BdsmSize=%Lu\n",BdsmSize)); - mBdsmSize = (UINTN)BdsmSize; - }else{ - //assume 64M - DEBUG((DEBUG_INFO,"BdsmSize not found\n")); - //mBdsmSize = (UINTN)(64<<20); - } - - CANDIDATE_PCI_INFO PciInfo={}; - InitPciInfo (PciIo, &PciInfo); - if (mOpRegionSize > 0) { - SetupOpRegion (PciIo, &PciInfo); - } - if (mBdsmSize > 0) { - SetupStolenMemory (PciIo, &PciInfo); - } - return EFI_SUCCESS; + if (EFI_ERROR(OpRegionStatus) && EFI_ERROR(BdsmStatus)) + { + PRINT_DEBUG(EFI_D_ERROR, "%a: bdsmStatus: %d OpRegionStatus: %d\n", __FUNCTION__, + BdsmStatus, OpRegionStatus); + return EFI_UNSUPPORTED; + } + + // + // Require all fw_cfg files that are present to be well-formed. + // + if (!EFI_ERROR(OpRegionStatus) && mOpRegionSize == 0) + { + PRINT_DEBUG(EFI_D_ERROR, "%a: %a: zero size\n", __FUNCTION__, + ASSIGNED_IGD_FW_CFG_OPREGION); + return EFI_PROTOCOL_ERROR; + } + + if (!EFI_ERROR(BdsmStatus)) + { + UINT64 BdsmSize; + + if (BdsmItemSize != sizeof BdsmSize) + { + PRINT_DEBUG(EFI_D_ERROR, "%a: %a: invalid fw_cfg size: %Lu\n", __FUNCTION__, + ASSIGNED_IGD_FW_CFG_BDSM_SIZE, (UINT64)BdsmItemSize); + return EFI_PROTOCOL_ERROR; + } + QemuFwCfgSelectItem(BdsmItem); + QemuFwCfgReadBytes(BdsmItemSize, &BdsmSize); + + if (BdsmSize == 0 || BdsmSize > MAX_UINTN) + { + PRINT_DEBUG(EFI_D_ERROR, "%a: %a: invalid value: %Lu\n", __FUNCTION__, + ASSIGNED_IGD_FW_CFG_BDSM_SIZE, BdsmSize); + return EFI_PROTOCOL_ERROR; + } + PRINT_DEBUG(EFI_D_ERROR, "BdsmSize=%Lu\n", BdsmSize); + mBdsmSize = (UINTN)BdsmSize; + } + else + { + // assume 64M + PRINT_DEBUG(EFI_D_ERROR, "BdsmSize not found\n"); + // mBdsmSize = (UINTN)(64<<20); + } + + CANDIDATE_PCI_INFO PciInfo = {}; + InitPciInfo(PciIo, &PciInfo); + if (mOpRegionSize > 0) + { + SetupOpRegion(PciIo, &PciInfo); + } + if (mBdsmSize > 0) + { + SetupStolenMemory(PciIo, &PciInfo); + } + return EFI_SUCCESS; } +////POWER EDP +EFI_STATUS EFIAPI i915ControllerDriverStart( + IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath) +{ + EFI_TPL OldTpl; + EFI_STATUS Status; + i915_CONTROLLER *Private; + PCI_TYPE00 Pci; + // SANITY CHECKS AND INTIALIZATION OF Driver + OldTpl = gBS->RaiseTPL(TPL_CALLBACK); + PRINT_DEBUG(EFI_D_ERROR, "start\n"); + + Private = &g_private; + + Private->Signature = SIGNATURE_32('i', '9', '1', '5'); + + Status = gBS->OpenProtocol( + Controller, &gEfiPciIoProtocolGuid, (VOID **)&Private->PciIo, + This->DriverBindingHandle, Controller, EFI_OPEN_PROTOCOL_BY_DRIVER); + if (EFI_ERROR(Status)) + { + goto RestoreTpl; + } + + Status = Private->PciIo->Pci.Read(Private->PciIo, EfiPciIoWidthUint32, 0, + sizeof(Pci) / sizeof(UINT32), &Pci); + if (EFI_ERROR(Status)) + { + goto ClosePciIo; + } + + Status = Private->PciIo->Attributes( + Private->PciIo, EfiPciIoAttributeOperationEnable, + EFI_PCI_DEVICE_ENABLE, // | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY, + NULL); + if (EFI_ERROR(Status)) + { + goto ClosePciIo; + } + + PRINT_DEBUG(EFI_D_ERROR, "set pci attrs\n"); + + // + // Get ParentDevicePath + // + EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath; + Status = gBS->HandleProtocol(Controller, &gEfiDevicePathProtocolGuid, + (VOID **)&ParentDevicePath); + if (EFI_ERROR(Status)) + { + goto ClosePciIo; + } + + // + // Set Gop Device Path + // + ACPI_ADR_DEVICE_PATH AcpiDeviceNode; + ZeroMem(&AcpiDeviceNode, sizeof(ACPI_ADR_DEVICE_PATH)); + AcpiDeviceNode.Header.Type = ACPI_DEVICE_PATH; + AcpiDeviceNode.Header.SubType = ACPI_ADR_DP; + AcpiDeviceNode.ADR = + ACPI_DISPLAY_ADR(1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_VGA, 0, 0); + SetDevicePathNodeLength(&AcpiDeviceNode.Header, sizeof(ACPI_ADR_DEVICE_PATH)); + + Private->GopDevicePath = AppendDevicePathNode( + ParentDevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&AcpiDeviceNode); + if (Private->GopDevicePath == NULL) + { + Status = EFI_OUT_OF_RESOURCES; + goto ClosePciIo; + } + PRINT_DEBUG(EFI_D_ERROR, "made gop path\n"); + + // + // Create new child handle and install the device path protocol on it. + // + Status = gBS->InstallMultipleProtocolInterfaces(&Private->Handle, + &gEfiDevicePathProtocolGuid, + Private->GopDevicePath, NULL); + if (EFI_ERROR(Status)) + { + goto FreeGopDevicePath; + } + PRINT_DEBUG(EFI_D_ERROR, "installed child handle\n"); + + g_private.write32 = write32; + g_private.read32 = read32; + g_private.read64 = read64; + g_private.rawclk_freq = 24000; //Should be the same for all compatible + + // setup OpRegion from fw_cfg (IgdAssignmentDxe) + PRINT_DEBUG(EFI_D_ERROR, "before QEMU shenanigans\n"); + + QemuFwCfgInitialize(); + + if ( + + QemuFwCfgIsAvailable() -EFI_STATUS EFIAPI i915ControllerDriverStart ( - IN EFI_DRIVER_BINDING_PROTOCOL *This, - IN EFI_HANDLE Controller, - IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath ) -{ - EFI_TPL OldTpl; - EFI_STATUS Status; - I915_VIDEO_PRIVATE_DATA *Private; - PCI_TYPE00 Pci; - - OldTpl = gBS->RaiseTPL (TPL_CALLBACK); - DebugPrint(EFI_D_ERROR,"i915: start\n"); - - Private = &g_private; - - Private->Signature = SIGNATURE_32('i','9','1','5'); - - Status = gBS->OpenProtocol ( - Controller, - &gEfiPciIoProtocolGuid, - (VOID **) &Private->PciIo, - This->DriverBindingHandle, - Controller, - EFI_OPEN_PROTOCOL_BY_DRIVER - ); - if (EFI_ERROR (Status)) { - goto RestoreTpl; - } - - Status = Private->PciIo->Pci.Read ( - Private->PciIo, - EfiPciIoWidthUint32, - 0, - sizeof (Pci) / sizeof (UINT32), - &Pci - ); - if (EFI_ERROR (Status)) { - goto ClosePciIo; - } - - Status = Private->PciIo->Attributes ( - Private->PciIo, - EfiPciIoAttributeOperationEnable, - EFI_PCI_DEVICE_ENABLE,// | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY, - NULL - ); - if (EFI_ERROR (Status)) { - goto ClosePciIo; - } - - DebugPrint(EFI_D_ERROR,"i915: set pci attrs\n"); - - // - // Get ParentDevicePath - // - EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath; - Status = gBS->HandleProtocol ( - Controller, - &gEfiDevicePathProtocolGuid, - (VOID **) &ParentDevicePath - ); - if (EFI_ERROR (Status)) { - goto ClosePciIo; - } - - // - // Set Gop Device Path - // - ACPI_ADR_DEVICE_PATH AcpiDeviceNode; - ZeroMem (&AcpiDeviceNode, sizeof (ACPI_ADR_DEVICE_PATH)); - AcpiDeviceNode.Header.Type = ACPI_DEVICE_PATH; - AcpiDeviceNode.Header.SubType = ACPI_ADR_DP; - AcpiDeviceNode.ADR = ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_VGA, 0, 0); - SetDevicePathNodeLength (&AcpiDeviceNode.Header, sizeof (ACPI_ADR_DEVICE_PATH)); - - Private->GopDevicePath = AppendDevicePathNode ( - ParentDevicePath, - (EFI_DEVICE_PATH_PROTOCOL *) &AcpiDeviceNode - ); - if (Private->GopDevicePath == NULL) { - Status = EFI_OUT_OF_RESOURCES; - goto ClosePciIo; - } - DebugPrint(EFI_D_ERROR,"i915: made gop path\n"); - - // - // Create new child handle and install the device path protocol on it. - // - Status = gBS->InstallMultipleProtocolInterfaces ( - &Private->Handle, - &gEfiDevicePathProtocolGuid, - Private->GopDevicePath, - NULL - ); - if (EFI_ERROR (Status)) { - goto FreeGopDevicePath; - } - DebugPrint(EFI_D_ERROR,"i915: installed child handle\n"); - - /* 1. Enable PCH reset handshake. */ - //intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); - write32(HSW_NDE_RSTWRN_OPT,read32(HSW_NDE_RSTWRN_OPT)|RESET_PCH_HANDSHAKE_ENABLE); - - //DOESN'T APPLY - ///* 2-3. */ - //icl_combo_phys_init(dev_priv); - - //if (resume && dev_priv->csr.dmc_payload) - // intel_csr_load_program(dev_priv); - - //power well enable, we are requesting these to be enabled - //#define SKL_PW_CTL_IDX_PW_2 15 - //#define SKL_PW_CTL_IDX_PW_1 14 - //#define SKL_PW_CTL_IDX_DDI_D 4 - //#define SKL_PW_CTL_IDX_DDI_C 3 - //#define SKL_PW_CTL_IDX_DDI_B 2 - //#define SKL_PW_CTL_IDX_DDI_A_E 1 - //#define SKL_PW_CTL_IDX_MISC_IO 0 - write32(HSW_PWR_WELL_CTL1,read32(HSW_PWR_WELL_CTL1)|0xA00002AAu); - for(UINT32 counter=0;;counter++){ - UINT32 stat=read32(HSW_PWR_WELL_CTL1); - if(counter>16384){ - DebugPrint(EFI_D_ERROR,"i915: power well enabling timed out %08x\n",stat); - break; - } - if(stat&0x50000155u){ - DebugPrint(EFI_D_ERROR,"i915: power well enabled %08x\n",stat); - break; - } - } - //disable VGA - UINT32 vgaword=read32(VGACNTRL); - write32(VGACNTRL,(vgaword&~VGA_2X_MODE)|VGA_DISP_DISABLE); - //DebugPrint(EFI_D_ERROR,"i915: bars %08x %08x %08x %08x\n",Pci.Device.Bar[0],Pci.Device.Bar[1],Pci.Device.Bar[2],Pci.Device.Bar[3]); - - ///* 5. Enable CDCLK. */ - //icl_init_cdclk(dev_priv); - //080002a1 on test machine - //DebugPrint(EFI_D_ERROR,"i915: CDCLK = %08x\n",read32(CDCLK_CTL)); - //there seems no need to do so - - ///* 6. Enable DBUF. */ - //icl_dbuf_enable(dev_priv); - I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST); - I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST); - read32(DBUF_CTL_S2); - for(UINT32 counter=0;;counter++){ - if(counter>16384){ - DebugPrint(EFI_D_ERROR,"i915: DBUF timeout\n"); - break; - } - if(read32(DBUF_CTL_S1)&read32(DBUF_CTL_S2)&DBUF_POWER_STATE){ - DebugPrint(EFI_D_ERROR,"i915: DBUF good\n"); - break; - } - } - - ///* 7. Setup MBUS. */ - //icl_mbus_init(dev_priv); - I915_WRITE(MBUS_ABOX_CTL, - MBUS_ABOX_BT_CREDIT_POOL1(16) | - MBUS_ABOX_BT_CREDIT_POOL2(16) | - MBUS_ABOX_B_CREDIT(1) | - MBUS_ABOX_BW_CREDIT(1) - ); - - //set up display buffer - //the value is from host - DebugPrint(EFI_D_ERROR,"i915: _PLANE_BUF_CFG_1_A = %08x\n",read32(_PLANE_BUF_CFG_1_A)); - write32(_PLANE_BUF_CFG_1_A,0x035b0000); - DebugPrint(EFI_D_ERROR,"i915: _PLANE_BUF_CFG_1_A = %08x (after)\n",read32(_PLANE_BUF_CFG_1_A)); - - //initialize output - //need workaround: always initialize DDI - //intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); - //intel_ddi_init(PORT_A); - UINT32 found = I915_READ(SFUSE_STRAP); - DebugPrint(EFI_D_ERROR,"i915: SFUSE_STRAP = %08x\n",found); - port=PORT_A; - if (found & SFUSE_STRAP_DDIB_DETECTED){ - port=PORT_B;//intel_ddi_init(PORT_B); - }else if (found & SFUSE_STRAP_DDIC_DETECTED){ - port=PORT_C;//intel_ddi_init(PORT_C); - }else if (found & SFUSE_STRAP_DDID_DETECTED){ - port=PORT_D;//intel_ddi_init(PORT_D); - } - //if (found & SFUSE_STRAP_DDIF_DETECTED) - // intel_ddi_init(dev_priv, PORT_F); - - //reset GMBUS - //intel_i2c_reset(dev_priv); - I915_WRITE(GMBUS0, 0); - I915_WRITE(GMBUS4, 0); - - // query EDID and initialize the mode - // it somehow fails on real hardware - Status = ReadEDID(&g_private.edid); - if (EFI_ERROR (Status)) { - DebugPrint(EFI_D_ERROR,"i915: failed to read EDID\n"); - for(UINT32 i=0;i<128;i++){ - ((UINT8*)&g_private.edid)[i]=edid_fallback[i]; - } - } - DebugPrint(EFI_D_ERROR,"i915: got EDID:\n"); - for(UINT32 i=0;i<16;i++){ - for(UINT32 j=0;j<8;j++){ - DebugPrint(EFI_D_ERROR,"%02x ",((UINT8*)(&g_private.edid))[i*8+j]); - } - DebugPrint(EFI_D_ERROR,"\n"); - } - UINT32 pixel_clock = (UINT32)(g_private.edid.detailTimings[0].pixelClock) * 10; - UINT32 x_active = g_private.edid.detailTimings[0].horzActive | ((UINT32)(g_private.edid.detailTimings[0].horzActiveBlankMsb >> 4) << 8); - UINT32 y_active = g_private.edid.detailTimings[0].vertActive | ((UINT32)(g_private.edid.detailTimings[0].vertActiveBlankMsb >> 4) << 8); - DebugPrint(EFI_D_ERROR,"i915: %ux%u clock=%u\n",x_active,y_active,pixel_clock); - g_mode_info[0].HorizontalResolution=x_active; - g_mode_info[0].VerticalResolution=y_active; - g_mode_info[0].PixelsPerScanLine = ((x_active*4+63)&-64)>>2; - g_mode_info[0].PixelFormat = PixelBlueGreenRedReserved8BitPerColor; - //get BAR 0 address and size - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *bar0Desc; - Private->PciIo->GetBarAttributes ( - Private->PciIo, - PCI_BAR_IDX0, - NULL, - (VOID**) &bar0Desc - ); - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *bar2Desc; - Private->PciIo->GetBarAttributes ( - Private->PciIo, - PCI_BAR_IDX1, - NULL, - (VOID**) &bar2Desc - ); - DebugPrint(EFI_D_ERROR,"i915: bar ranges - %llx %llx, %llx %llx\n", - bar0Desc->AddrRangeMin,bar0Desc->AddrLen, - bar2Desc->AddrRangeMin,bar2Desc->AddrLen); - UINT32 bar0Size=bar0Desc->AddrLen; - EFI_PHYSICAL_ADDRESS mmio_base = bar0Desc->AddrRangeMin; - - //get BAR 2 address - EFI_PHYSICAL_ADDRESS aperture_base = bar2Desc->AddrRangeMin; - DebugPrint(EFI_D_ERROR,"i915: aperture at %p\n",aperture_base); - //Private->PciIo->Pci.Write (Private->PciIo,EfiPciIoWidthUint32,0x18,1,&aperture_base); - //Private->PciIo->Pci.Read (Private->PciIo,EfiPciIoWidthUint32,0x18,1,&bar_work); - //DebugPrint(EFI_D_ERROR,"i915: aperture confirmed at %016x\n",bar_work); - //GVT-g gmadr issue - g_private.gmadr=0; - g_private.is_gvt=0; - if(read64(0x78000)==0x4776544776544776ULL){ - g_private.gmadr=read32(0x78040); - g_private.is_gvt=1; - //apertureSize=read32(0x78044); - } - DebugPrint(EFI_D_ERROR,"i915: gmadr = %08x, size = %08x, hgmadr = %08x, hsize = %08x\n", - g_private.gmadr,read32(0x78044),read32(0x78048),read32(0x7804c)); - - //create Global GTT entries to actually back the framebuffer - g_private.FbBase=aperture_base+(UINT64)(g_private.gmadr); - UINTN MaxFbSize=((x_active*4+64)&-64)*y_active; - UINTN Pages = EFI_SIZE_TO_PAGES ((MaxFbSize+65535)&-65536); - EFI_PHYSICAL_ADDRESS fb_backing=(EFI_PHYSICAL_ADDRESS)AllocateReservedPages(Pages); - if(!fb_backing){ - DebugPrint(EFI_D_ERROR,"i915: failed to allocate framebuffer\n"); - Status=EFI_OUT_OF_RESOURCES; - goto FreeGopDevicePath; - } - EFI_PHYSICAL_ADDRESS ggtt_base=mmio_base+(bar0Size>>1); - UINT64* ggtt=(UINT64*)ggtt_base; - DebugPrint(EFI_D_ERROR,"i915: ggtt_base at %p, entries: %08x %08x, backing fb: %p, %x bytes\n",ggtt_base,ggtt[0],ggtt[g_private.gmadr>>12],fb_backing,MaxFbSize); - for(UINTN i=0;i>12]=((UINT32)(addr>>32)&0x7F0u)|((UINT32)addr&0xFFFFF000u)|11; - } - - //setup OpRegion from fw_cfg (IgdAssignmentDxe) - DebugPrint(EFI_D_ERROR,"i915: before QEMU shenanigans\n"); - QemuFwCfgInitialize(); - if(QemuFwCfgIsAvailable()){ - //setup opregion - Status=SetupFwcfgStuff(Private->PciIo); - DebugPrint(EFI_D_ERROR,"i915: SetupFwcfgStuff returns %d\n",Status); - } - DebugPrint(EFI_D_ERROR,"i915: after QEMU shenanigans\n"); - - //TODO: turn on backlight if found in OpRegion, need eDP initialization first... - - // - // Start the GOP software stack. - // - EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput; - GraphicsOutput = &Private->GraphicsOutput; - GraphicsOutput->QueryMode = i915GraphicsOutputQueryMode; - GraphicsOutput->SetMode = i915GraphicsOutputSetMode; - GraphicsOutput->Blt = i915GraphicsOutputBlt; - GraphicsOutput->Mode = &g_mode; - Status = GraphicsOutput->SetMode (GraphicsOutput, 0); - if (EFI_ERROR (Status)) { - goto FreeGopDevicePath; - } - - - Status = gBS->InstallMultipleProtocolInterfaces ( - &Private->Handle, - &gEfiGraphicsOutputProtocolGuid, - &Private->GraphicsOutput, - NULL - ); - if (EFI_ERROR (Status)) { - goto Destructi915Graphics; - } - - // - // Reference parent handle from child handle. - // - EFI_PCI_IO_PROTOCOL *ChildPciIo; - Status = gBS->OpenProtocol ( - Controller, - &gEfiPciIoProtocolGuid, - (VOID **) &ChildPciIo, - This->DriverBindingHandle, - Private->Handle, - EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER - ); - if (EFI_ERROR (Status)) { - goto UninstallGop; - } - - DebugPrint(EFI_D_ERROR,"i915: gop ready\n"); - - gBS->RestoreTPL (OldTpl); - return EFI_SUCCESS; + { + // setup opregion + Status = SetupFwcfgStuff(Private->PciIo); + if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR, "SetupFwcfgStuff Error %d. Please see https://github.com/RotatingFans/i915ovmfPkg/wiki/Qemu-FwCFG-Workaround for more information\n", Status); + + return Status; //TODO Better cleanup + } + PRINT_DEBUG(EFI_D_ERROR, "SetupFwcfgStuff returns %d\n", Status); + } + PRINT_DEBUG(EFI_D_ERROR, "after QEMU shenanigans\n"); + + intel_bios_init(&g_private); + g_private.gmadr = 0; + g_private.is_gvt = 0; + if (read64(0x78000) == 0x4776544776544776ULL) + { + PRINT_DEBUG(EFI_D_ERROR, "GVT-G Enabled\n"); + g_private.gmadr = read32(0x78040); + g_private.is_gvt = 1; + // apertureSize=read32(0x78044); + } + // BEGIN IG AND DISPLAY CONFIG + Status = DisplayInit(&g_private); + if (EFI_ERROR(Status)) + { + PRINT_DEBUG(EFI_D_ERROR, "DisplayInit Error. %d\n", Status); + + return Status; //TODO Better cleanup + } + // get BAR 0 address and size + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *bar0Desc; + Private->PciIo->GetBarAttributes(Private->PciIo, PCI_BAR_IDX0, NULL, + (VOID **)&bar0Desc); + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *bar2Desc; + Private->PciIo->GetBarAttributes(Private->PciIo, PCI_BAR_IDX1, NULL, + (VOID **)&bar2Desc); + PRINT_DEBUG(EFI_D_ERROR, "bar ranges - %llx %llx, %llx %llx\n", + bar0Desc->AddrRangeMin, bar0Desc->AddrLen, bar2Desc->AddrRangeMin, + bar2Desc->AddrLen); + UINT32 bar0Size = bar0Desc->AddrLen; + EFI_PHYSICAL_ADDRESS mmio_base = bar0Desc->AddrRangeMin; + + // get BAR 2 address + EFI_PHYSICAL_ADDRESS aperture_base = bar2Desc->AddrRangeMin; + PRINT_DEBUG(EFI_D_ERROR, "aperture at %p\n", aperture_base); + // Private->PciIo->Pci.Write + // (Private->PciIo,EfiPciIoWidthUint32,0x18,1,&aperture_base); + // Private->PciIo->Pci.Read + // (Private->PciIo,EfiPciIoWidthUint32,0x18,1,&bar_work); + // DebugPrint(EFI_D_ERROR,"i915: aperture confirmed at %016x\n",bar_work); + // GVT-g gmadr issue + + PRINT_DEBUG(EFI_D_ERROR, + "i915: gmadr = %08x, size = %08x, hgmadr = %08x, hsize = %08x\n", + g_private.gmadr, read32(0x78044), read32(0x78048), + read32(0x7804c)); + + UINT32 x_active = + g_private.edid.detailTimings[DETAIL_TIME_SELCTION].horzActive | + ((UINT32)(g_private.edid.detailTimings[DETAIL_TIME_SELCTION] + .horzActiveBlankMsb >> + 4) + << 8); + UINT32 y_active = + g_private.edid.detailTimings[DETAIL_TIME_SELCTION].vertActive | + ((UINT32)(g_private.edid.detailTimings[DETAIL_TIME_SELCTION] + .vertActiveBlankMsb >> + 4) + << 8); + + UINT32 pixel_clock = + (UINT32)(g_private.edid.detailTimings[DETAIL_TIME_SELCTION].pixelClock) * + 10; + + PRINT_DEBUG(EFI_D_ERROR, "%ux%u clock=%u\n", x_active, y_active, + pixel_clock); + // create Global GTT entries to actually back the framebuffer + g_private.FbBase = aperture_base + (UINT64)(g_private.gmadr); + UINTN MaxFbSize = ((x_active * 4 + 64) & -64) * y_active; + UINTN Pages = EFI_SIZE_TO_PAGES((MaxFbSize + 65535) & -65536); + EFI_PHYSICAL_ADDRESS fb_backing = + (EFI_PHYSICAL_ADDRESS)AllocateReservedPages(Pages); + if (!fb_backing) + { + PRINT_DEBUG(EFI_D_ERROR, "failed to allocate framebuffer\n"); + Status = EFI_OUT_OF_RESOURCES; + goto FreeGopDevicePath; + } + EFI_PHYSICAL_ADDRESS ggtt_base = mmio_base + (bar0Size >> 1); + UINT64 *ggtt = (UINT64 *)ggtt_base; + PRINT_DEBUG(EFI_D_ERROR, + "i915: ggtt_base at %p, entries: %08x %08x, backing fb: %p, %x bytes\n", + ggtt_base, ggtt[0], ggtt[g_private.gmadr >> 12], fb_backing, MaxFbSize); + for (UINTN i = 0; i < MaxFbSize; i += 4096) + { + // create one PTE entry for each page + // cache is whatever cache used by the linux driver on my host + EFI_PHYSICAL_ADDRESS addr = fb_backing + i; + ggtt[(g_private.gmadr + i) >> 12] = + ((UINT32)(addr >> 32) & 0x7F0u) | ((UINT32)addr & 0xFFFFF000u) | 11; + } + + /* // setup OpRegion from fw_cfg (IgdAssignmentDxe) + PRINT_DEBUG(EFI_D_ERROR,"before QEMU shenanigans\n"); + + QemuFwCfgInitialize(); + + if ( + + QemuFwCfgIsAvailable() + + ) { + // setup opregion + Status = SetupFwcfgStuff(Private->PciIo); + PRINT_DEBUG(EFI_D_ERROR,"SetupFwcfgStuff returns %d\n", Status); + } + PRINT_DEBUG(EFI_D_ERROR,"after QEMU shenanigans\n"); */ + + // TODO: turn on backlight if found in OpRegion, need eDP initialization + // first... + + // + // Start the GOP software stack. + // + EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput; + GraphicsOutput = &g_private.GraphicsOutput; + PRINT_DEBUG(EFI_D_ERROR, "progressed to mline %d, status is %u\n", + __LINE__, Status); + Status = i915GraphicsSetupOutput(GraphicsOutput, x_active, y_active); + PRINT_DEBUG(EFI_D_ERROR, "progressed to mline %d, status is %u\n", + __LINE__, Status); + if (EFI_ERROR(Status)) + { + goto FreeGopDevicePath; + } + + Status = gBS->InstallMultipleProtocolInterfaces( + &Private->Handle, &gEfiGraphicsOutputProtocolGuid, + &Private->GraphicsOutput, NULL); + if (EFI_ERROR(Status)) + { + goto Destructi915Graphics; + } + + // + // Reference parent handle from child handle. + // + EFI_PCI_IO_PROTOCOL *ChildPciIo; + Status = + gBS->OpenProtocol(Controller, &gEfiPciIoProtocolGuid, + (VOID **)&ChildPciIo, This->DriverBindingHandle, + Private->Handle, EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER); + if (EFI_ERROR(Status)) + { + goto UninstallGop; + } + + PRINT_DEBUG(EFI_D_ERROR, "gop ready\n"); + + gBS->RestoreTPL(OldTpl); + return EFI_SUCCESS; UninstallGop: - gBS->UninstallProtocolInterface (Private->Handle, - &gEfiGraphicsOutputProtocolGuid, &Private->GraphicsOutput); + gBS->UninstallProtocolInterface(Private->Handle, + &gEfiGraphicsOutputProtocolGuid, + &Private->GraphicsOutput); Destructi915Graphics: ClosePciIo: - gBS->CloseProtocol (Controller, &gEfiPciIoProtocolGuid, - This->DriverBindingHandle, Controller); + gBS->CloseProtocol(Controller, &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, Controller); FreeGopDevicePath: - FreePool (Private->GopDevicePath); - + FreePool(Private->GopDevicePath); + RestoreTpl: - gBS->RestoreTPL (OldTpl); - return Status; + gBS->RestoreTPL(OldTpl); + return Status; } -EFI_STATUS EFIAPI i915ControllerDriverStop ( - IN EFI_DRIVER_BINDING_PROTOCOL *This, - IN EFI_HANDLE Controller, - IN UINTN NumberOfChildren, - IN EFI_HANDLE *ChildHandleBuffer - ) +EFI_STATUS EFIAPI i915ControllerDriverStop(IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer) { - DebugPrint(EFI_D_ERROR,"i915ControllerDriverStop\n"); - //we don't support this, Windows can clean up our mess without this anyway - return EFI_UNSUPPORTED; + PRINT_DEBUG(EFI_D_ERROR, "ControllerDriverStop\n"); + // we don't support this, Windows can clean up our mess without this anyway + return EFI_UNSUPPORTED; } - -EFI_STATUS EFIAPI i915ControllerDriverSupported ( - IN EFI_DRIVER_BINDING_PROTOCOL *This, - IN EFI_HANDLE Controller, - IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath - ) +EFI_STATUS EFIAPI i915ControllerDriverSupported( + IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath) { - EFI_STATUS Status; - EFI_PCI_IO_PROTOCOL *PciIo; - PCI_TYPE00 Pci; - EFI_DEV_PATH *Node; - - // - // Open the PCI I/O Protocol - // - Status = gBS->OpenProtocol ( - Controller, - &gEfiPciIoProtocolGuid, - (VOID **) &PciIo, - This->DriverBindingHandle, - Controller, - EFI_OPEN_PROTOCOL_BY_DRIVER - ); - if (EFI_ERROR (Status)) { - return Status; - } - - // - // Read the PCI Configuration Header from the PCI Device - // - Status = PciIo->Pci.Read ( - PciIo, - EfiPciIoWidthUint32, - 0, - sizeof (Pci) / sizeof (UINT32), - &Pci - ); - if (EFI_ERROR (Status)) { - goto Done; - } - - Status = EFI_UNSUPPORTED; - if (Pci.Hdr.VendorId == 0x8086&&IS_PCI_DISPLAY(&Pci)){ - Status = EFI_SUCCESS; - // - // If this is an Intel graphics controller, - // go further check RemainingDevicePath validation - // - if (RemainingDevicePath != NULL) { - Node = (EFI_DEV_PATH *) RemainingDevicePath; - // - // Check if RemainingDevicePath is the End of Device Path Node, - // if yes, return EFI_SUCCESS - // - if (!IsDevicePathEnd (Node)) { - // - // If RemainingDevicePath isn't the End of Device Path Node, - // check its validation - // - if (Node->DevPath.Type != ACPI_DEVICE_PATH || - Node->DevPath.SubType != ACPI_ADR_DP || - DevicePathNodeLength(&Node->DevPath) != sizeof(ACPI_ADR_DEVICE_PATH)) { - Status = EFI_UNSUPPORTED; - } - } - } - if(Status==EFI_SUCCESS){ - DebugPrint(EFI_D_ERROR,"i915: found device %04x-%04x %p\n",Pci.Hdr.VendorId,Pci.Hdr.DeviceId,RemainingDevicePath); - //DebugPrint(EFI_D_ERROR,"i915: bars %08x %08x %08x %08x\n",Pci.Device.Bar[0],Pci.Device.Bar[1],Pci.Device.Bar[2],Pci.Device.Bar[3]); - //Status=EFI_UNSUPPORTED; - } - } - + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + EFI_DEV_PATH *Node; + + // + // Open the PCI I/O Protocol + // + Status = gBS->OpenProtocol(Controller, &gEfiPciIoProtocolGuid, + (VOID **)&PciIo, This->DriverBindingHandle, + Controller, EFI_OPEN_PROTOCOL_BY_DRIVER); + if (EFI_ERROR(Status)) + { + return Status; + } + + // + // Read the PCI Configuration Header from the PCI Device + // + Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, 0, + sizeof(Pci) / sizeof(UINT32), &Pci); + if (EFI_ERROR(Status)) + { + goto Done; + } + + Status = EFI_UNSUPPORTED; + if (Pci.Hdr.VendorId == 0x8086 && IS_PCI_DISPLAY(&Pci)) + { + Status = EFI_SUCCESS; + // + // If this is an Intel graphics controller, + // go further check RemainingDevicePath validation + // + if (RemainingDevicePath != NULL) + { + Node = (EFI_DEV_PATH *)RemainingDevicePath; + // + // Check if RemainingDevicePath is the End of Device Path Node, + // if yes, return EFI_SUCCESS + // + if (!IsDevicePathEnd(Node)) + { + // + // If RemainingDevicePath isn't the End of Device Path Node, + // check its validation + // + if (Node->DevPath.Type != ACPI_DEVICE_PATH || + Node->DevPath.SubType != ACPI_ADR_DP || + DevicePathNodeLength(&Node->DevPath) != + sizeof(ACPI_ADR_DEVICE_PATH)) + { + Status = EFI_UNSUPPORTED; + } + } + } + if (Status == EFI_SUCCESS) + { + PRINT_DEBUG(EFI_D_ERROR, "found device %04x-%04x %p\n", + Pci.Hdr.VendorId, Pci.Hdr.DeviceId, RemainingDevicePath); + // DebugPrint(EFI_D_ERROR,"i915: bars %08x %08x %08x + // %08x\n",Pci.Device.Bar[0],Pci.Device.Bar[1],Pci.Device.Bar[2],Pci.Device.Bar[3]); + // Status=EFI_UNSUPPORTED; + } + } + Done: - gBS->CloseProtocol ( - Controller, - &gEfiPciIoProtocolGuid, - This->DriverBindingHandle, - Controller - ); - return Status; + gBS->CloseProtocol(Controller, &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, Controller); + return Status; } -EFI_DRIVER_BINDING_PROTOCOL gi915DriverBinding = { - i915ControllerDriverSupported, - i915ControllerDriverStart, - i915ControllerDriverStop, - 0x10, - NULL, - NULL -}; +EFI_DRIVER_BINDING_PROTOCOL gi915DriverBinding = {i915ControllerDriverSupported, + i915ControllerDriverStart, + i915ControllerDriverStop, + 0x10, + NULL, + NULL}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mi915DriverNameTable[] = { - { "eng;en", L"i915 Driver" }, - { NULL , NULL } -}; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE + mi915DriverNameTable[] = {{"eng;en", L"i915 Driver"}, {NULL, NULL}}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mi915ControllerNameTable[] = { - { "eng;en", L"i915 PCI Thing" }, - { NULL , NULL } -}; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE + mi915ControllerNameTable[] = {{"eng;en", L"i915 PCI Thing"}, {NULL, NULL}}; -GLOBAL_REMOVE_IF_UNREFERENCED extern EFI_COMPONENT_NAME_PROTOCOL gi915ComponentName; +GLOBAL_REMOVE_IF_UNREFERENCED extern EFI_COMPONENT_NAME_PROTOCOL + gi915ComponentName; EFI_STATUS EFIAPI -i915ComponentNameGetDriverName ( - IN EFI_COMPONENT_NAME_PROTOCOL *This, - IN CHAR8 *Language, - OUT CHAR16 **DriverName - ) +i915ComponentNameGetDriverName(IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, OUT CHAR16 **DriverName) { - return LookupUnicodeString2 ( - Language, - This->SupportedLanguages, - mi915DriverNameTable, - DriverName, - (BOOLEAN)(This == &gi915ComponentName) - ); + return LookupUnicodeString2(Language, This->SupportedLanguages, + mi915DriverNameTable, DriverName, + (BOOLEAN)(This == &gi915ComponentName)); } EFI_STATUS EFIAPI -i915ComponentNameGetControllerName ( - IN EFI_COMPONENT_NAME_PROTOCOL *This, - IN EFI_HANDLE ControllerHandle, - IN EFI_HANDLE ChildHandle OPTIONAL, - IN CHAR8 *Language, - OUT CHAR16 **ControllerName - ) +i915ComponentNameGetControllerName(IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName) { - EFI_STATUS Status; + EFI_STATUS Status; // // This is a device driver, so ChildHandle must be NULL. // - if (ChildHandle != NULL) { + if (ChildHandle != NULL) + { return EFI_UNSUPPORTED; } // // Make sure this driver is currently managing ControllHandle // - Status = EfiTestManagedDevice ( - ControllerHandle, - gi915DriverBinding.DriverBindingHandle, - &gEfiPciIoProtocolGuid - ); - if (EFI_ERROR (Status)) { + Status = EfiTestManagedDevice(ControllerHandle, + gi915DriverBinding.DriverBindingHandle, + &gEfiPciIoProtocolGuid); + if (EFI_ERROR(Status)) + { return Status; } - return LookupUnicodeString2 ( - Language, - This->SupportedLanguages, - mi915ControllerNameTable, - ControllerName, - (BOOLEAN)(This == &gi915ComponentName) - ); + return LookupUnicodeString2(Language, This->SupportedLanguages, + mi915ControllerNameTable, ControllerName, + (BOOLEAN)(This == &gi915ComponentName)); } -GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gi915ComponentName = { - i915ComponentNameGetDriverName, - i915ComponentNameGetControllerName, - "eng" -}; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gi915ComponentName = { + i915ComponentNameGetDriverName, i915ComponentNameGetControllerName, "eng"}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gi915ComponentName2 = { - (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) i915ComponentNameGetDriverName, - (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) i915ComponentNameGetControllerName, - "en" -}; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gi915ComponentName2 = + {(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)i915ComponentNameGetDriverName, + (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) + i915ComponentNameGetControllerName, + "en"}; -EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gi915SupportedEfiVersion = { - sizeof (EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL), // Size of Protocol structure. - 0 // Version number to be filled at start up. -}; +EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gi915SupportedEfiVersion = { + sizeof(EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL), // Size of Protocol + // structure. + 0 // Version number to be filled at start up. +}; +static EFI_SYSTEM_TABLE *g_SystemTable = NULL; -EFI_STATUS EFIAPI efi_main ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) +EFI_STATUS EFIAPI efi_main(IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable) { - //////////// - g_SystemTable=SystemTable; - DebugPrint (EFI_D_ERROR, "Driver starts!\n"); - EFI_STATUS Status; - Status = EfiLibInstallDriverBindingComponentName2 ( - ImageHandle, - SystemTable, - &gi915DriverBinding, - ImageHandle, - &gi915ComponentName, - &gi915ComponentName2 - ); - ASSERT_EFI_ERROR (Status); - - gi915SupportedEfiVersion.FirmwareVersion = PcdGet32 (PcdDriverSupportedEfiVersion); - Status = gBS->InstallMultipleProtocolInterfaces ( - &ImageHandle, - &gEfiDriverSupportedEfiVersionProtocolGuid, - &gi915SupportedEfiVersion, - NULL - ); - ASSERT_EFI_ERROR (Status); - - return EFI_SUCCESS; + //////////// + g_SystemTable = SystemTable; + PRINT_DEBUG(EFI_D_ERROR, "Driver starts!\n"); + EFI_STATUS Status; + Status = EfiLibInstallDriverBindingComponentName2( + ImageHandle, SystemTable, &gi915DriverBinding, ImageHandle, + &gi915ComponentName, &gi915ComponentName2); + ASSERT_EFI_ERROR(Status); + + gi915SupportedEfiVersion.FirmwareVersion = + PcdGet32(PcdDriverSupportedEfiVersion); + Status = gBS->InstallMultipleProtocolInterfaces( + &ImageHandle, &gEfiDriverSupportedEfiVersionProtocolGuid, + &gi915SupportedEfiVersion, NULL); + ASSERT_EFI_ERROR(Status); + + return EFI_SUCCESS; } diff --git a/i915ovmf.dsc b/i915ovmf.dsc index 262cbe9..c0a98c0 100755 --- a/i915ovmf.dsc +++ b/i915ovmf.dsc @@ -28,7 +28,8 @@ SUPPORTED_ARCHITECTURES = X64 BUILD_TARGETS = NOOPT|DEBUG|RELEASE SKUID_IDENTIFIER = DEFAULT - + + # # Flash size selection. Setting FD_SIZE_IN_KB on the command line directly to # one of the supported values, in place of any of the convenience macros, is @@ -91,53 +92,53 @@ # Library Class section - list of all Library Classes needed by this Platform. # ################################################################################ -[LibraryClasses.common] - UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf - UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf - UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf +[LibraryClasses.common] + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - UefiLib|MdePkg/Library/UefiLib/UefiLib.inf - BaseLib|MdePkg/Library/BaseLib/BaseLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf - - ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf - ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf - - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf - IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf - DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf - - QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf - MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf - CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf - CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf - FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf - TimerLib|OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf - -[Components] - i915ovmfPkg/i915ovmf.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + + QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf + MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf + TimerLib|OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf + +[Components] + i915ovmfPkg/i915ovmf.inf diff --git a/i915ovmf.h b/i915ovmf.h new file mode 100644 index 0000000..2e01243 --- /dev/null +++ b/i915ovmf.h @@ -0,0 +1,15 @@ +#ifndef i915_OVMFH +#define i915_OVMFH +#include "i915_reg.h" +//registers are in bar 0 +//frame buffer is in bar 2 + +#define HSW_PWR_WELL_CTL1 (0x45400) +#define HSW_PWR_WELL_CTL2 (0x45404) +#define HSW_PWR_WELL_CTL3 (0x45408) +#define HSW_PWR_WELL_CTL4 (0x4540C) + + +#define I915_READ read32 +#define I915_WRITE write32 +#endif \ No newline at end of file diff --git a/i915ovmf.inf b/i915ovmf.inf index c5c6136..7a9c750 100755 --- a/i915ovmf.inf +++ b/i915ovmf.inf @@ -31,15 +31,33 @@ ENTRY_POINT = efi_main [Sources] + i915_debug.h i915ovmf.c + i915ovmf.h QemuFwCfgLib.c QemuFwCfgPei.c + i915_ddi.c + i915_display.c + i915_dp.c + i915_hdmi.c + i915_gop.c + i915_ddi.h + i915_display.h + i915_dp.h + i915_hdmi.h + i915_gop.h + i915_gmbus.c + i915_gmbus.h + intel_opregion.h + intel_opregion.c + + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec OvmfPkg/OvmfPkg.dec - OptionRomPkg/OptionRomPkg.dec + Drivers/OptionRomPkg/OptionRomPkg.dec i915ovmfPkg/i915ovmf.dec [LibraryClasses] @@ -54,7 +72,8 @@ UefiBootServicesTableLib UefiDriverEntryPoint UefiLib - + MemEncryptSevLib + [Protocols] gEfiDriverSupportedEfiVersionProtocolGuid # PROTOCOL ALWAYS_PRODUCED gEfiGraphicsOutputProtocolGuid # PROTOCOL BY_START @@ -66,8 +85,8 @@ [Depex] TRUE - -[Pcd] - gOptionRomPkgTokenSpaceGuid.PcdDriverSupportedEfiVersion - gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId - gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask + +[Pcd] + gOptionRomPkgTokenSpaceGuid.PcdDriverSupportedEfiVersion + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId + gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask diff --git a/i915ovmfBuildPrep.sh b/i915ovmfBuildPrep.sh new file mode 100755 index 0000000..b2b287b --- /dev/null +++ b/i915ovmfBuildPrep.sh @@ -0,0 +1,501 @@ +#! /bin/bash +version="0.1.0-alpha" +OS="UnKnown" +OS_VER="0.0" +INSTALL_DIR="./i915Install" +declare -A gpus +declare PCILOC=0000:00:02.0 +PCIID=8086:9bca +COMMAND="setup" +InstallLibVirtStuff=1 +modulesLoadFile=/etc/modules-load.d/i915ovmf.conf +checkRoot() { + if ((EUID != 0)); then + echo "This script must be run as root" + exit 1 + fi + return 0 +} +displayHelp() { + echo "i915ovmf Download Script Version $version" + echo "Manages everything related to development, building, and testing of the i915ovmf ROM" + echo "Usage: ./i915ovmfBuildPrep.sh [setup | build | clean | update | kernel | GVT-G | GVT-D] [OPTIONS]" + echo "Options: " + echo " -V | --version: Prints the version" + echo " -d | --dir: the directory to setup the workspace in. Defaults to ./i915Install" + echo " -h | --help: Shows this help" + return 0 +} +readArgs() { + + COMMAND=$1 + echo "Running in $COMMAND mode" + shift + #Parse arguments; Taken from https://devhints.io/bash#miscellaneous + while [[ "$1" =~ ^- && ! "$1" == "--" ]]; do + case $1 in + -V | --version) + echo $version + exit + ;; + -d | --dir) + shift + INSTALL_DIR=$1 + ;; + -h | --help) + displayHelp + exit + ;; + *) + echo "Invalid Option: $1 specified" + ;; + esac + shift + done + if [[ "$1" == '--' ]]; then shift; fi + return 0 +} + +getDistroAndVersion() { + if [ -f /etc/os-release ]; then + # freedesktop.org and systemd + . /etc/os-release + OS=$NAME + OS_VER=$VERSION_ID + elif type lsb_release >/dev/null 2>&1; then + # linuxbase.org + OS=$(lsb_release -si) + OS_VER=$(lsb_release -sr) + elif [ -f /etc/lsb-release ]; then + # For some versions of Debian/Ubuntu without lsb_release command + . /etc/lsb-release + OS=$DISTRIB_ID + OS_VER=$DISTRIB_RELEASE + elif [ -f /etc/debian_version ]; then + # Older Debian/Ubuntu/etc. + OS=Debian + OS_VER=$(cat /etc/debian_version) + else + # Fall back to uname, e.g. "Linux ", also works for BSD, etc. + OS=$(uname -s) + OS_VER=$(uname -r) + fi + return 0 +} +installRequiredSoftware() { + echo "Installing pre-requisite software" + + case $OS in + Fedora* | fedora*) + echo "Detected Fedora $OS_VER" + if [[ "$OS_VER" != "32" ]]; then + echo "Untested version of Fedora. Continuing anyway. Failure may be imminent." + fi + dnf update + installSoftware="libuuid-devel iasl nasm clang lld-devel llvm-devel cmake automake git" + if (($InstallLibVirtStuff)); then + installSoftware+=" libvirt virt-install qemu-kvm bridge-utils libguestfs-tools virt-manager" + fi + dnf install $installSoftware + echo "Fedora Preparation Done" + ;; + Ubuntu* | ubuntu*) + echo "Detected Ubuntu $OS_VER" + if [[ "$OS_VER" != "20.04" ]]; then + echo "Untested version of Ubuntu. Continuing anyway. Failure may be imminent." + fi + installSoftware=" iasl nasm clang lld cmake automake build-essential uuid-dev git gcc python3-distutils python-is-python3" + if (($InstallLibVirtStuff)); then + installSoftware+=" libvirt-daemon qemu-kvm bridge-utils libguestfs-tools virt-manager" + fi + apt update + apt install $installSoftware + echo "Ubuntu Preparation Done" + ;; + *) + echo "Unkown OS: $OS $OS_VER" + echo "Please follow manual instructions here: https://github.com/patmagauran/i915ovmfPkg/wiki/Compiling" + exit 1 + ;; + esac + return 0 +} + +prepWorkspace() { + echo "$COMMAND" + if [[ -f $INSTALL_DIR ]]; then + echo "You selected a file as the installation directory. This is not supported. Please select a different directory with the -d option." + exit 1 + elif [[ -d $INSTALL_DIR ]] && [[ ! -z "$(ls -A $INSTALL_DIR)" ]] && [[ $COMMAND == "setup" ]]; then + echo "Selected install directory \"$INSTALL_DIR\" is not empty. Please rename it or select a different directory with the -d option" + exit 1 + fi + echo "Preparing Workspace" + mkdir -p $INSTALL_DIR + cd $INSTALL_DIR + INSTALL_DIR="$(pwd)" + echo "Installing to $INSTALL_DIR" + return 0 +} +downloadi915() { + echo "Downloading i915ovmfpkg main repo..." + git clone https://github.com/patmagauran/i915ovmfPkg.git + return 0 +} +downloadEdk2() { + echo "Downloading edk2 repo..." + + git clone https://github.com/tianocore/edk2.git + git clone https://github.com/tianocore/edk2-platforms.git + cd edk2-platforms/ + git submodule update --init + cd ../edk2 + git switch stable/202011 + git submodule update --init + cd .. + return 0 +} +setupEDK2() { + echo "Copying Config file..." + + cd $INSTALL_DIR + mkdir Conf + cp i915ovmfPkg/target.txt Conf/target.txt + return 0 +} +#Inspiration for GPU Prompting comes from https://github.com/hertg/egpu-switcher/blob/master/egpu-switcher +getGPUS() { + gpus=() + lines=$(lspci -mm -n -D -d 8086::0300 && lspci -mm -n -D -d 8086::0302 && lspci -mm -n -D -d 8086::0380) + + while read -r line; do + echo "DEBUG: GPU FOUND: $line" + lineElements=($line) + bus=${lineElements[0]} + vendor=${lineElements[2]} + temp="${vendor%\"}" + temp="${temp#\"}" + vendor=$temp + device=${lineElements[3]} + temp="${device%\"}" + temp="${temp#\"}" + device=$temp + pciID="${vendor}:${device}" + echo "DEBUG: GPU DECODED AS $bus $pciID" + gpus+=([$bus]=$pciID) + done <<<$lines + + return 0 +} +promptGPU() { + num_of_gpus=${#gpus[@]} + if (($num_of_gpus > 1)); then + gpu=0 + declare mapping=() + declare i=0 + echo "More than 2 Intel GPUs detected. Please select the correct one" + for key in ${!gpus[@]}; do + i=$((i + 1)) + mapping+=([${i}]=${key}) + echo " $i: $(lspci -s ${key}) (${key})" + done + echo "Please select which GPU the software should configure: " + read gpu + if ((gpu < 0 || gpu > $num_of_gpus)); then + echo "Invalid input. Please try again" + promptGPU + return 0 + fi + PCILOC=${mapping[$gpu]} + PCIID=${gpus[${PCILOC}]} + elif (($num_of_gpus == 1)); then + keys=${!gpus[@]} + PCILOC=${keys[0]} + echo "Using Intel GPU: $(lspci -s ${PCILOC})" + PCIID=${gpus[${PCILOC}]} + else + echo "No Intel GPUS detected. You can try a manual install if needed." + exit 1 + fi + return 0 +} +setupi915() { + cd $INSTALL_DIR/i915ovmfPkg + if ([[ -e config ]]); then + mv config config.bak.$(date +'%F_%T') + fi + echo "export PCIID=${PCIID}" >>config + echo "export PCILOC=${PCILOC}" >>config + echo "export WORKSPACE=${INSTALL_DIR}" >>config + echo "export DefaultGVTMODE=1" >>config + cd $INSTALL_DIR + dd if=/dev/zero of=disk bs=128M count=1 + sudo mkfs.vfat disk + mkdir i915_simple + cp disk i915_simple/ + case $OS in + Fedora* | fedora*) + cp /usr/share/edk2/ovmf/OVMF_CODE.fd ./ + ;; + Ubuntu* | ubuntu*) + cp /usr/share/OVMF/OVMF_CODE.fd ./ + ;; + esac + return 0 +} +buildi915() { + echo "Building edk2 and i915 with gcc $(gcc --version)" + cd $WORKSPACE + . edk2/edksetup.sh + if [ ! -f "$WORKSPACE/edk2/BaseTools/Source/C/bin" ]; then + make -C edk2/BaseTools + fi + build -v -b DEBUG -p i915ovmfPkg/i915ovmf.dsc || exit + return 0 +} +clean() { + cd $WORKSPACE + rm -rf Build + return 0 +} +checkKernelParam() { + + return 0 +} +buildKernelParams() { + currentParams=$(sed 's/GRUB_CMDLINE_LINUX_DEFAULT="\(.*\)"/\1/p' -n /etc/default/grub) + desiredParams=($1) + finalParams=$currentParams + for param in "${desiredParams[@]}"; do + if [[ ! $currentParams =~ $param ]]; then + finalParams="${finalParams} ${param}" + fi + done + echo $finalParams + return 0 +} +updateGrub() { + case $OS in + Fedora* | fedora*) + grub2-mkconfig + ;; + Ubuntu* | ubuntu*) + update-grub + ;; + esac + +} +kernel() { + #'s/GRUB_CMDLINE_LINUX_DEFAULT="\(.*\)"/\1/p' -n + # 's/GRUB_CMDLINE_LINUX_DEFAULT="\(.*\)"/GRUB_CMDLINE_LINUX_DEFAULT="\1 intel_iommu=on i915.enable_gvt=1 i915.enable_guc=0 iommu=pt"/g' + saveChange=N + backup=/etc/default/grub.bak.$(date +'%F_%T') + cp /etc/default/grub $backup + params="$(buildKernelParams 'intel_iommu=on i915.enable_gvt=1 i915.enable_guc=0 iommu=pt vfio-pci.ids='${PCIID}'')" + sed -i 's/GRUB_CMDLINE_LINUX_DEFAULT="\(.*\)"/GRUB_CMDLINE_LINUX_DEFAULT="'"${params}"'"/g' /etc/default/grub + echo "/etc/default/grub now reads as:" + cat /etc/default/grub + echo + read -p "Does this look good [Y/N]?" saveChange + case $saveChange in + Y | y) + updateGrub + ;; + *) + echo "Reverting kernel changes." + cp $backup /etc/default/grub + ;; + esac + + touch $modulesLoadFile + echo kvmgt >>$modulesLoadFile + echo vfio-iommu-type1 >>$modulesLoadFile + echo vfio-mdev >>$modulesLoadFile + echo vfio_pci >>$modulesLoadFile + + echo "You will need to reboot for changes to take effect. Would you like to reboot now? [Y/N]" + read saveChange + if [[ $saveChange == "Y" || $saveChange == "y" ]]; then + shutdown -r + fi + return 0 +} +update() { + cd $INSTALL_DIR + cd i915ovmfPkg + git pull + echo "Updates pulled. You must now build. Run ./i915ovmfBuildPrep.sh build" + return 0 +} + +promptGvtMode() { + mode=$DefaultGVTMODE + declare mapping=() + declare i=0 + directory="/sys/bus/pci/devices/$PCILOC/mdev_supported_types" + for key in "$directory"/*; do + key=${key##*/} + #echo $key + i=$((i + 1)) + mapping+=([${i}]=${key}) + echo " $i: (${key})" + cat /sys/bus/pci/devices/$PCILOC/mdev_supported_types/$key/description | sed 's/^/ /' + done + echo "Please select the GVT Mode to use. Will continue with default in 10 seconds: [${DefaultGVTMODE}] " + read -t 10 mode + if ((mode < 1 || mode > $i)); then + echo "Invalid input. Exiting" + exit 1 + fi + GVTMODE=${mapping[$mode]} + return 0 +} +gvt-g() { + cd $WORKSPACE + #buildi915 + #build -b RELEASE -p i915ovmfPkg/i915ovmf.dsc || exit + mkdir -p i915_simple + cd ./i915_simple + #cp ../Build/i915ovmf/RELEASE_GCC5/X64/i915ovmf.rom ./ || exit + cp ../Build/i915ovmf/DEBUG_GCC5/X64/i915ovmf.rom ./ || exit + + if [ -e /sys/bus/pci/devices/$PCILOC/2aee154e-7d0d-11e8-88b8-6f45320c7162 ]; then + true + else + modprobe kvmgt || exit + promptGvtMode + #sudo dd if=/sys/class/drm/card0-HDMI-A-1/edid of=/sys/class/drm/card0/gvt_edid bs=128 count=1 + echo 2aee154e-7d0d-11e8-88b8-6f45320c7162 >/sys/bus/pci/devices/$PCILOC/mdev_supported_types/$GVTMODE/create || exit + fi + + # Create an UEFI disk that immediately shuts down the VM when booted + mkdir -p tmpfat + mount disk tmpfat + mkdir -p tmpfat/EFI/BOOT + umount tmpfat + rmdir tmpfat + + qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -serial stdio -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios $WORKSPACE/OVMF_CODE.fd -display gtk,gl=on,grab-on-hover=on -full-screen -vga none -device vfio-pci,sysfsdev=/sys/bus/pci/devices/$PCILOC/2aee154e-7d0d-11e8-88b8-6f45320c7162,addr=02.0,display=on,x-igd-opregion=on,romfile=$(pwd)/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk + + return 0 +} +rebindi915() { + echo $PCILOC >/sys/bus/pci/devices/$PCILOC/driver/unbind || echo "Error unbinding igpu. Continuing." + echo "i915" >/sys/bus/pci/devices/$PCILOC/driver_override || echo "Error adding igpu to i915. Continuing." + echo 1 >/sys/bus/pci/devices/$PCILOC/reset || echo "Error resetting igpu. Continuing." + systemctl restart display-manager.service + return 0 +} +gvt-d() { + cd $WORKSPACE + buildi915 + mkdir -p i915_simple + cd ./i915_simple + #cp ../Build/i915ovmf/RELEASE_GCC5/X64/i915ovmf.rom ./ || exit + cp ../Build/i915ovmf/DEBUG_GCC5/X64/i915ovmf.rom ./ || exit + + # Create an UEFI disk that immediately shuts down the VM when booted + mkdir -p tmpfat + mount disk tmpfat + mkdir -p tmpfat/EFI/BOOT + umount tmpfat + rmdir tmpfat + systemctl stop display-manager.service + #echo $PCIID >/sys/bus/pci/drivers/vfio-pci/new_id + + echo $PCILOC >/sys/bus/pci/devices/$PCILOC/driver/unbind || echo "Error unbinding igpu. Continuing." + echo "vfio-pci" >/sys/bus/pci/devices/$PCILOC/driver_override || echo "Error adding igpu to vfio. Continuing." + echo $PCILOC >/sys/bus/pci/drivers/vfio-pci/bind || echo "Error binding igpu to vfio. Continuing." + #qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -nographic -vga none -serial stdio -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios $WORKSPACE/OVMF_CODE.fd -device vfio-pci,host=$PCILOC,romfile=`pwd`/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk -usb + timeout --foreground -k 1 4 qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -nographic -vga none -chardev stdio,id=char0,logfile=serial.log,signal=off \ + -serial chardev:char0 -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios $WORKSPACE/OVMF_CODE.fd -device vfio-pci,host=$PCILOC,romfile=$(pwd)/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk -usb + rebindi915 + return 0 +} + +promptKernel() { + resp=Y + read -p "Would you like to automatically configure your kernel settings for GVT-D/G? [Y/N]" resp + case $resp in + Y | y) + kernel + ;; + esac +} +checkConfig() { + if [[ ! -e $INSTALL_DIR/i915ovmfPkg/config ]]; then + echo "Could not find config file. Ensure the correct workspace directory is set with the -d option. Or if this is the first run, run the program in setup mode. i.e sudo $0 setup -d EXAMPLEINSTALLDIR" + exit 1 + fi + source $INSTALL_DIR/i915ovmfPkg/config + export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms + return 0 +} +main() { + set -o errexit + if [[ $# -eq 0 ]]; then + displayHelp + exit 0 + fi + checkRoot + readArgs $@ + getDistroAndVersion + prepWorkspace + case $COMMAND in + setup) + echo "Running Setup" + installRequiredSoftware + downloadi915 + downloadEdk2 + setupEDK2 + getGPUS + promptGPU + setupi915 + promptKernel + ;; + build) + echo "Running build" + checkConfig + buildi915 + ;; + clean) + echo "Running clean" + checkConfig + clean + ;; + kernel) + echo "Running kernel Setup" + checkConfig + kernel + ;; + update) + echo "Running update" + checkConfig + update + ;; + GVT-G) + echo "Running GVT-G Test" + checkConfig + gvt-g + ;; + GVT-D) + echo "Running GVT-D Test" + checkConfig + gvt-d + ;; + bind) + echo "rebinding igpu to i915" + checkConfig + rebindi915 + ;; + *) + echo "Invalid command entered. Please consult documentation" + checkConfig + displayHelp + exit + ;; + esac + return 0 +} + +main $@ diff --git a/intel_opregion.c b/intel_opregion.c new file mode 100644 index 0000000..065369d --- /dev/null +++ b/intel_opregion.c @@ -0,0 +1,1149 @@ + +#include "intel_opregion.h" +//TODO CONVVERT to EFI_STATUS RETURN TYPEs + +//#include +//#include + +/* Get BDB block size given a pointer to Block ID. */ +static UINT32 _get_blocksize(const UINT8 *block_base) +{ + /* The MIPI Sequence Block v3+ has a separate size field. */ + if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3) + return *((const UINT32 *)(block_base + 4)); + else + return *((const UINT16 *)(block_base + 1)); +} + +// /* Get BDB block size give a pointer to data after Block ID and Block Size. */ +// static u32 get_blocksize(const void *block_data) +// { +// return _get_blocksize(block_data - 3); +// } + +static const void * +find_section_vbt(const void *_bdb, int section_id) +{ + const struct bdb_header *bdb = _bdb; + const u8 *base = _bdb; + int index = 0; + u32 total, current_size; + u8 current_id; + + /* skip to first section */ + index += bdb->header_size; + total = bdb->bdb_size; + + /* walk the sections looking for section_id */ + while (index + 3 < total) + { + current_id = *(base + index); + current_size = _get_blocksize(base + index); + index += 3; + + if (index + current_size > total) + return NULL; + + if (current_id == section_id) + return base + index; + + index += current_size; + } + + return NULL; +} +static EFI_STATUS find_section(struct context *context, int section_id, struct bdb_block *block) +{ + const struct bdb_header *bdb = context->bdb; + int length = context->size; + const UINT8 *base = (const UINT8 *)bdb; + int index = 0; + UINT32 total, current_size; + unsigned char current_id; + + /* skip to first section */ + index += bdb->header_size; + total = bdb->bdb_size; + if (total > length) + total = length; + PRINT_DEBUG(EFI_D_ERROR, "finding section %d\n", section_id); + //block = malloc(sizeof(*block)); + + /* walk the sections looking for section_id */ + while (index + 3 < total) + { + current_id = *(base + index); + current_size = _get_blocksize(base + index); + index += 3; + //PRINT_DEBUG(EFI_D_ERROR,"current id %d; index: %d; location 0x%04x; current_size: %d\n", current_id, index, (base + index), current_size); + + if (index + current_size > total) + return EFI_NOT_FOUND; + + if (current_id == section_id) + { + if (!block) + { + PRINT_DEBUG(EFI_D_ERROR, "out of memory"); + //TODO CONVVERT to EFI_STATUS RETURN TYPEs + // exit(EXIT_FAILURE); + } + block->id = current_id; + block->size = current_size; + block->data = base + index; + return EFI_SUCCESS; + } + + index += current_size; + } + + return EFI_NOT_FOUND; +} +static const char *dvo_port_names[] = { + [DVO_PORT_HDMIA] = "HDMI-A", + [DVO_PORT_HDMIB] = "HDMI-B", + [DVO_PORT_HDMIC] = "HDMI-C", + [DVO_PORT_HDMID] = "HDMI-D", + [DVO_PORT_LVDS] = "LVDS", + [DVO_PORT_TV] = "TV", + [DVO_PORT_CRT] = "CRT", + [DVO_PORT_DPB] = "DP-B", + [DVO_PORT_DPC] = "DP-C", + [DVO_PORT_DPD] = "DP-D", + [DVO_PORT_DPA] = "DP-A", + [DVO_PORT_DPE] = "DP-E", + [DVO_PORT_HDMIE] = "HDMI-E", + [DVO_PORT_MIPIA] = "MIPI-A", + [DVO_PORT_MIPIB] = "MIPI-B", + [DVO_PORT_MIPIC] = "MIPI-C", + [DVO_PORT_MIPID] = "MIPI-D", +}; + +static const char *dvo_port(UINT8 type) +{ + if (type < ARRAY_SIZE(dvo_port_names) && dvo_port_names[type]) + return dvo_port_names[type]; + else + return "unknown"; +} +#define DEVICE_HANDLE_CRT 0x01 +#define DEVICE_HANDLE_EFP1 0x04 +#define DEVICE_HANDLE_EFP2 0x40 +#define DEVICE_HANDLE_EFP3 0x20 +#define DEVICE_HANDLE_EFP4 0x10 +#define DEVICE_HANDLE_LPF1 0x08 +#define DEVICE_HANDLE_LFP2 0x80 + +#define DEVICE_TYPE_DP_DVI 0x68d6 +#define DEVICE_TYPE_DVI 0x68d2 +#define DEVICE_TYPE_MIPI 0x7cc2 +static const struct +{ + unsigned char handle; + const char *name; +} child_device_handles[] = { + {DEVICE_HANDLE_CRT, "CRT"}, + {DEVICE_HANDLE_EFP1, "EFP 1 (HDMI/DVI/DP)"}, + {DEVICE_HANDLE_EFP2, "EFP 2 (HDMI/DVI/DP)"}, + {DEVICE_HANDLE_EFP3, "EFP 3 (HDMI/DVI/DP)"}, + {DEVICE_HANDLE_EFP4, "EFP 4 (HDMI/DVI/DP)"}, + {DEVICE_HANDLE_LPF1, "LFP 1 (eDP)"}, + {DEVICE_HANDLE_LFP2, "LFP 2 (eDP)"}, +}; +static const int num_child_device_handles = + sizeof(child_device_handles) / sizeof(child_device_handles[0]); + +static const char *child_device_handle(unsigned char handle) +{ + int i; + + for (i = 0; i < num_child_device_handles; i++) + if (child_device_handles[i].handle == handle) + return child_device_handles[i].name; + + return "unknown"; +} +static const struct +{ + unsigned short type; + const char *name; +} child_device_types[] = { + {DEVICE_TYPE_NONE, "none"}, + {DEVICE_TYPE_CRT, "CRT"}, + {DEVICE_TYPE_TV, "TV"}, + {DEVICE_TYPE_EFP, "EFP"}, + {DEVICE_TYPE_LFP, "LFP"}, + {DEVICE_TYPE_CRT_DPMS, "CRT"}, + {DEVICE_TYPE_CRT_DPMS_HOTPLUG, "CRT"}, + {DEVICE_TYPE_TV_COMPOSITE, "TV composite"}, + {DEVICE_TYPE_TV_MACROVISION, "TV"}, + {DEVICE_TYPE_TV_RF_COMPOSITE, "TV"}, + {DEVICE_TYPE_TV_SVIDEO_COMPOSITE, "TV S-Video"}, + {DEVICE_TYPE_TV_SCART, "TV SCART"}, + {DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR, "TV"}, + {DEVICE_TYPE_EFP_HOTPLUG_PWR, "EFP"}, + {DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR, "DVI"}, + {DEVICE_TYPE_EFP_DVI_I, "DVI-I"}, + {DEVICE_TYPE_EFP_DVI_D_DUAL, "DL-DVI-D"}, + {DEVICE_TYPE_EFP_DVI_D_HDCP, "DVI-D"}, + {DEVICE_TYPE_OPENLDI_HOTPLUG_PWR, "OpenLDI"}, + {DEVICE_TYPE_OPENLDI_DUALPIX, "OpenLDI"}, + {DEVICE_TYPE_LFP_PANELLINK, "PanelLink"}, + {DEVICE_TYPE_LFP_CMOS_PWR, "CMOS LFP"}, + {DEVICE_TYPE_LFP_LVDS_PWR, "LVDS"}, + {DEVICE_TYPE_LFP_LVDS_DUAL, "LVDS"}, + {DEVICE_TYPE_LFP_LVDS_DUAL_HDCP, "LVDS"}, + {DEVICE_TYPE_INT_LFP, "LFP"}, + {DEVICE_TYPE_INT_TV, "TV"}, + {DEVICE_TYPE_DP, "DisplayPort"}, + {DEVICE_TYPE_DP_DUAL_MODE, "DisplayPort/HDMI/DVI"}, + {DEVICE_TYPE_DP_DVI, "DisplayPort/DVI"}, + {DEVICE_TYPE_HDMI, "HDMI/DVI"}, + {DEVICE_TYPE_DVI, "DVI"}, + {DEVICE_TYPE_eDP, "eDP"}, + {DEVICE_TYPE_MIPI, "MIPI"}, +}; +static const int num_child_device_types = + sizeof(child_device_types) / sizeof(child_device_types[0]); + +static const char *child_device_type(unsigned short type) +{ + int i; + + for (i = 0; i < num_child_device_types; i++) + if (child_device_types[i].type == type) + return child_device_types[i].name; + + return "unknown"; +} +static const struct +{ + unsigned short mask; + const char *name; +} child_device_type_bits[] = { + {DEVICE_TYPE_CLASS_EXTENSION, "Class extension"}, + {DEVICE_TYPE_POWER_MANAGEMENT, "Power management"}, + {DEVICE_TYPE_HOTPLUG_SIGNALING, "Hotplug signaling"}, + {DEVICE_TYPE_INTERNAL_CONNECTOR, "Internal connector"}, + {DEVICE_TYPE_NOT_HDMI_OUTPUT, "HDMI output"}, /* decoded as inverse */ + {DEVICE_TYPE_MIPI_OUTPUT, "MIPI output"}, + {DEVICE_TYPE_COMPOSITE_OUTPUT, "Composite output"}, + {DEVICE_TYPE_DUAL_CHANNEL, "Dual channel"}, + {1 << 7, "Content protection"}, + {DEVICE_TYPE_HIGH_SPEED_LINK, "High speed link"}, + {DEVICE_TYPE_LVDS_SIGNALING, "LVDS signaling"}, + {DEVICE_TYPE_TMDS_DVI_SIGNALING, "TMDS/DVI signaling"}, + {DEVICE_TYPE_VIDEO_SIGNALING, "Video signaling"}, + {DEVICE_TYPE_DISPLAYPORT_OUTPUT, "DisplayPort output"}, + {DEVICE_TYPE_DIGITAL_OUTPUT, "Digital output"}, + {DEVICE_TYPE_ANALOG_OUTPUT, "Analog output"}, +}; + +static void dump_child_device_type_bits(UINT16 type) +{ + int i; + + type ^= DEVICE_TYPE_NOT_HDMI_OUTPUT; + + for (i = 0; i < ARRAY_SIZE(child_device_type_bits); i++) + { + if (child_device_type_bits[i].mask & type) + PRINT_DEBUG(EFI_D_ERROR, "\t\t\t%s\n", child_device_type_bits[i].name); + } +} +static const char *mipi_bridge_type(UINT8 type) +{ + switch (type) + { + case 1: + return "ASUS"; + case 2: + return "Toshiba"; + case 3: + return "Renesas"; + default: + return "unknown"; + } +} +static void dump_child_device(struct context *context, + const struct child_device_config *child) +{ + //if (!child->device_type) + return; + + PRINT_DEBUG(EFI_D_ERROR, "Child device info:\n"); + PRINT_DEBUG(EFI_D_ERROR, "\tDevice handle: 0x%04x (%s)\n", child->handle, + child_device_handle(child->handle)); + PRINT_DEBUG(EFI_D_ERROR, "\tDevice type: 0x%04x (%s)\n", child->device_type, + child_device_type(child->device_type)); + dump_child_device_type_bits(child->device_type); + + if (context->bdb->version < 152) + { + PRINT_DEBUG(EFI_D_ERROR, "\tSignature: %.*s\n", (int)sizeof(child->device_id), child->device_id); + } + else + { + PRINT_DEBUG(EFI_D_ERROR, "\tI2C speed: 0x%02x\n", child->i2c_speed); + PRINT_DEBUG(EFI_D_ERROR, "\tDP onboard redriver: 0x%02x\n", child->dp_onboard_redriver); + PRINT_DEBUG(EFI_D_ERROR, "\tDP ondock redriver: 0x%02x\n", child->dp_ondock_redriver); + PRINT_DEBUG(EFI_D_ERROR, "\tHDMI level shifter value: 0x%02x\n", child->hdmi_level_shifter_value); + // dump_hmdi_max_data_rate(child->hdmi_max_data_rate); + PRINT_DEBUG(EFI_D_ERROR, "\tOffset to DTD buffer for edidless CHILD: 0x%02x\n", child->dtd_buf_ptr); + PRINT_DEBUG(EFI_D_ERROR, "\tEdidless EFP: %s\n", YESNO(child->edidless_efp)); + PRINT_DEBUG(EFI_D_ERROR, "\tCompression enable: %s\n", YESNO(child->compression_enable)); + PRINT_DEBUG(EFI_D_ERROR, "\tCompression method CPS: %s\n", YESNO(child->compression_method)); + PRINT_DEBUG(EFI_D_ERROR, "\tDual pipe ganged eDP: %s\n", YESNO(child->ganged_edp)); + PRINT_DEBUG(EFI_D_ERROR, "\tCompression structure index: 0x%02x)\n", child->compression_structure_index); + PRINT_DEBUG(EFI_D_ERROR, "\tSlave DDI port: 0x%02x (%s)\n", child->slave_port, dvo_port(child->slave_port)); + } + + PRINT_DEBUG(EFI_D_ERROR, "\tAIM offset: %d\n", child->addin_offset); + PRINT_DEBUG(EFI_D_ERROR, "\tDVO Port: 0x%02x (%s)\n", child->dvo_port, dvo_port(child->dvo_port)); + + PRINT_DEBUG(EFI_D_ERROR, "\tAIM I2C pin: 0x%02x\n", child->i2c_pin); + PRINT_DEBUG(EFI_D_ERROR, "\tAIM Slave address: 0x%02x\n", child->slave_addr); + PRINT_DEBUG(EFI_D_ERROR, "\tDDC pin: 0x%02x\n", child->ddc_pin); + PRINT_DEBUG(EFI_D_ERROR, "\tEDID buffer ptr: 0x%02x\n", child->edid_ptr); + PRINT_DEBUG(EFI_D_ERROR, "\tDVO config: 0x%02x\n", child->dvo_cfg); + + if (context->bdb->version < 155) + { + PRINT_DEBUG(EFI_D_ERROR, "\tDVO2 Port: 0x%02x (%s)\n", child->dvo2_port, dvo_port(child->dvo2_port)); + PRINT_DEBUG(EFI_D_ERROR, "\tI2C2 pin: 0x%02x\n", child->i2c2_pin); + PRINT_DEBUG(EFI_D_ERROR, "\tSlave2 address: 0x%02x\n", child->slave2_addr); + PRINT_DEBUG(EFI_D_ERROR, "\tDDC2 pin: 0x%02x\n", child->ddc2_pin); + } + else + { + PRINT_DEBUG(EFI_D_ERROR, "\tEFP routed through dock: %s\n", YESNO(child->efp_routed)); + PRINT_DEBUG(EFI_D_ERROR, "\tLane reversal: %s\n", YESNO(child->lane_reversal)); + PRINT_DEBUG(EFI_D_ERROR, "\tOnboard LSPCON: %s\n", YESNO(child->lspcon)); + PRINT_DEBUG(EFI_D_ERROR, "\tIboost enable: %s\n", YESNO(child->iboost)); + PRINT_DEBUG(EFI_D_ERROR, "\tHPD sense invert: %s\n", YESNO(child->hpd_invert)); + PRINT_DEBUG(EFI_D_ERROR, "\tHDMI compatible? %s\n", YESNO(child->hdmi_support)); + PRINT_DEBUG(EFI_D_ERROR, "\tDP compatible? %s\n", YESNO(child->dp_support)); + PRINT_DEBUG(EFI_D_ERROR, "\tTMDS compatible? %s\n", YESNO(child->tmds_support)); + PRINT_DEBUG(EFI_D_ERROR, "\tAux channel: 0x%02x\n", child->aux_channel); + PRINT_DEBUG(EFI_D_ERROR, "\tDongle detect: 0x%02x\n", child->dongle_detect); + } + + PRINT_DEBUG(EFI_D_ERROR, "\tPipe capabilities: 0x%02x\n", child->pipe_cap); + PRINT_DEBUG(EFI_D_ERROR, "\tSDVO stall signal available: %s\n", YESNO(child->sdvo_stall)); + PRINT_DEBUG(EFI_D_ERROR, "\tHotplug connect status: 0x%02x\n", child->hpd_status); + PRINT_DEBUG(EFI_D_ERROR, "\tIntegrated encoder instead of SDVO: %s\n", YESNO(child->integrated_encoder)); + PRINT_DEBUG(EFI_D_ERROR, "\tDVO wiring: 0x%02x\n", child->dvo_wiring); + + if (context->bdb->version < 171) + { + PRINT_DEBUG(EFI_D_ERROR, "\tDVO2 wiring: 0x%02x\n", child->dvo2_wiring); + } + else + { + PRINT_DEBUG(EFI_D_ERROR, "\tMIPI bridge type: %02x (%s)\n", child->mipi_bridge_type, + mipi_bridge_type(child->mipi_bridge_type)); + } + + PRINT_DEBUG(EFI_D_ERROR, "\tDevice class extension: 0x%02x\n", child->extended_type); + PRINT_DEBUG(EFI_D_ERROR, "\tDVO function: 0x%02x\n", child->dvo_function); + + if (context->bdb->version >= 195) + { + PRINT_DEBUG(EFI_D_ERROR, "\tDP USB type C support: %s\n", YESNO(child->dp_usb_type_c)); + PRINT_DEBUG(EFI_D_ERROR, "\t2X DP GPIO index: 0x%02x\n", child->dp_gpio_index); + PRINT_DEBUG(EFI_D_ERROR, "\t2X DP GPIO pin number: 0x%02x\n", child->dp_gpio_pin_num); + } + + if (context->bdb->version >= 196) + { + PRINT_DEBUG(EFI_D_ERROR, "\tIBoost level for HDMI: 0x%02x\n", child->hdmi_iboost_level); + PRINT_DEBUG(EFI_D_ERROR, "\tIBoost level for DP/eDP: 0x%02x\n", child->dp_iboost_level); + } +} +#define min(a, b) (((a) < (b)) ? (a) : (b)) +#define max(a, b) (((a) > (b)) ? (a) : (b)) + +static EFI_STATUS get_child_devices(struct context *context, const UINT8 *devices, + UINT8 child_dev_num, UINT8 child_dev_size) +{ + struct child_device_config *child; + struct child_device_config *children = (struct child_device_config *)AllocateZeroPool(child_dev_num * sizeof(*child)); + int i; + + /* + * Use a temp buffer so dump_child_device() doesn't have to worry about + * accessing the struct beyond child_dev_size. The tail, if any, remains + * initialized to zero. + */ + child = (struct child_device_config *)AllocateZeroPool(sizeof(*child)); + + //child = calloc(1, sizeof(*child)); + + for (i = 0; i < child_dev_num; i++) + { + CopyMem(child, devices + i * child_dev_size, + min(sizeof(*child), child_dev_size)); + children[i] = *child; + //dump_child_device(context, child); + } + context->children = children; + context->numChildren = child_dev_num; + FreePool(child); + return EFI_SUCCESS; +} + +static void +parse_edp(i915_CONTROLLER *controller, const struct bdb_header *bdb) +{ + const struct bdb_edp *edp; + const struct edp_power_seq *edp_pps; + const struct edp_fast_link_params *edp_link_params; + int panel_type = controller->vbt.panel_type; + + edp = find_section_vbt(bdb, BDB_EDP); + if (!edp) + return; + + switch ((edp->color_depth >> (panel_type * 2)) & 3) + { + case EDP_18BPP: + controller->vbt.edp.bpp = 18; + break; + case EDP_24BPP: + controller->vbt.edp.bpp = 24; + break; + case EDP_30BPP: + controller->vbt.edp.bpp = 30; + break; + } + + /* Get the eDP sequencing and link info */ + edp_pps = &edp->power_seqs[panel_type]; + edp_link_params = &edp->fast_link_params[panel_type]; + + controller->vbt.edp.pps = *edp_pps; + + switch (edp_link_params->rate) + { + case EDP_RATE_1_62: + controller->vbt.edp.rate = DP_LINK_BW_1_62; + break; + case EDP_RATE_2_7: + controller->vbt.edp.rate = DP_LINK_BW_2_7; + break; + default: + PRINT_DEBUG(EFI_D_ERROR, "VBT has unknown eDP link rate value %u\n", + edp_link_params->rate); + break; + } + + switch (edp_link_params->lanes) + { + case EDP_LANE_1: + controller->vbt.edp.lanes = 1; + break; + case EDP_LANE_2: + controller->vbt.edp.lanes = 2; + break; + case EDP_LANE_4: + controller->vbt.edp.lanes = 4; + break; + default: + PRINT_DEBUG(EFI_D_ERROR, "VBT has unknown eDP lane count value %u\n", + edp_link_params->lanes); + break; + } + + switch (edp_link_params->preemphasis) + { + case EDP_PREEMPHASIS_NONE: + controller->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; + break; + case EDP_PREEMPHASIS_3_5dB: + controller->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; + break; + case EDP_PREEMPHASIS_6dB: + controller->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; + break; + case EDP_PREEMPHASIS_9_5dB: + controller->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; + break; + default: + PRINT_DEBUG(EFI_D_ERROR, "VBT has unknown eDP pre-emphasis value %u\n", + edp_link_params->preemphasis); + break; + } + + switch (edp_link_params->vswing) + { + case EDP_VSWING_0_4V: + controller->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; + break; + case EDP_VSWING_0_6V: + controller->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; + break; + case EDP_VSWING_0_8V: + controller->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; + break; + case EDP_VSWING_1_2V: + controller->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; + break; + default: + PRINT_DEBUG(EFI_D_ERROR, "VBT has unknown eDP voltage swing value %u\n", + edp_link_params->vswing); + break; + } + + if (bdb->version >= 173) + { + u8 vswing; + + /* Don't read from VBT if module parameter has valid value*/ + // if (i915_modparams.edp_vswing) + // { + // controller->vbt.edp.low_vswing = + // i915_modparams.edp_vswing == 1; + // } + // else + { + vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; + controller->vbt.edp.low_vswing = vswing == 0; + } + } +} + +static enum port get_port_by_ddc_pin(i915_CONTROLLER *i915, u8 ddc_pin) +{ + const struct ddi_vbt_port_info *info; + enum port port; + + for_each_port(port) + { + info = &i915->vbt.ddi_port_info[port]; + + if (info->child && ddc_pin == info->alternate_ddc_pin) + return port; + } + + return PORT_NONE; +} + +static void sanitize_ddc_pin(i915_CONTROLLER *controller, + enum port port) +{ + struct ddi_vbt_port_info *info = &controller->vbt.ddi_port_info[port]; + enum port p; + + if (!info->alternate_ddc_pin) + return; + + p = get_port_by_ddc_pin(controller, info->alternate_ddc_pin); + if (p != PORT_NONE) + { + PRINT_DEBUG(EFI_D_ERROR, + "port %c trying to use the same DDC pin (0x%x) as port %c, " + "disabling port %c DVI/HDMI support\n", + port_name(port), info->alternate_ddc_pin, + port_name(p), port_name(p)); + + /* + * If we have multiple ports supposedly sharing the + * pin, then dvi/hdmi couldn't exist on the shared + * port. Otherwise they share the same ddc bin and + * system couldn't communicate with them separately. + * + * Give inverse child device order the priority, + * last one wins. Yes, there are real machines + * (eg. Asrock B250M-HDV) where VBT has both + * port A and port E with the same AUX ch and + * we must pick port E :( + */ + info = &controller->vbt.ddi_port_info[p]; + + info->supports_dvi = false; + info->supports_hdmi = false; + info->alternate_ddc_pin = 0; + } +} + +static enum port get_port_by_aux_ch(i915_CONTROLLER *i915, u8 aux_ch) +{ + const struct ddi_vbt_port_info *info; + enum port port; + + for_each_port(port) + { + info = &i915->vbt.ddi_port_info[port]; + + if (info->child && aux_ch == info->alternate_aux_channel) + return port; + } + + return PORT_NONE; +} + +static void sanitize_aux_ch(i915_CONTROLLER *controller, + enum port port) +{ + struct ddi_vbt_port_info *info = &controller->vbt.ddi_port_info[port]; + enum port p; + + if (!info->alternate_aux_channel) + return; + + p = get_port_by_aux_ch(controller, info->alternate_aux_channel); + if (p != PORT_NONE) + { + PRINT_DEBUG(EFI_D_ERROR, + "port %c trying to use the same AUX CH (0x%x) as port %c, disabling port %c DP support\n", + port_name(port), info->alternate_aux_channel, + port_name(p), port_name(p)); + + /* + * If we have multiple ports supposedlt sharing the + * aux channel, then DP couldn't exist on the shared + * port. Otherwise they share the same aux channel + * and system couldn't communicate with them separately. + * + * Give inverse child device order the priority, + * last one wins. Yes, there are real machines + * (eg. Asrock B250M-HDV) where VBT has both + * port A and port E with the same AUX ch and + * we must pick port E :( + */ + info = &controller->vbt.ddi_port_info[p]; + + info->supports_dp = false; + info->alternate_aux_channel = 0; + } +} + +// static const u8 cnp_ddc_pin_map[] = { +// [0] = 0, /* N/A */ +// [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT, +// [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT, +// [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */ +// [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ +// }; + +/* static const u8 icp_ddc_pin_map[] = { + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, + [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, + [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT, + [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, + [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, + [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, + [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, + [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP, + [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, +}; */ + +static u8 map_ddc_pin(i915_CONTROLLER *controller, u8 vbt_pin) +{ + return vbt_pin; +} + +static enum port __dvo_port_to_port(int n_ports, int n_dvo, + const int port_mapping[][3], u8 dvo_port) +{ + enum port port; + int i; + + for (port = PORT_A; port < n_ports; port++) + { + for (i = 0; i < n_dvo; i++) + { + if (port_mapping[port][i] == -1) + break; + + if (dvo_port == port_mapping[port][i]) + return port; + } + } + + return PORT_NONE; +} +static u8 translate_iboost(u8 val) +{ + static const u8 mapping[] = {1, 3, 7}; /* See VBT spec */ + + if (val >= ARRAY_SIZE(mapping)) + { + PRINT_DEBUG(EFI_D_ERROR, "Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); + return 0; + } + return mapping[val]; +} +static enum port dvo_port_to_port(i915_CONTROLLER *controller, + u8 dvo_port) +{ + /* + * Each DDI port can have more than one value on the "DVO Port" field, + * so look for all the possible values for each port. + */ + static const int port_mapping[][3] = { + [PORT_A] = {DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, + [PORT_B] = {DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, + [PORT_C] = {DVO_PORT_HDMIC, DVO_PORT_DPC, -1}, + [PORT_D] = {DVO_PORT_HDMID, DVO_PORT_DPD, -1}, + [PORT_E] = {DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT}, + [PORT_F] = {DVO_PORT_HDMIF, DVO_PORT_DPF, -1}, + [PORT_G] = {DVO_PORT_HDMIG, DVO_PORT_DPG, -1}, + [PORT_H] = {DVO_PORT_HDMIH, DVO_PORT_DPH, -1}, + [PORT_I] = {DVO_PORT_HDMII, DVO_PORT_DPI, -1}, + }; + /* + * Bspec lists the ports as A, B, C, D - however internally in our + * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the + * registers in Display Engine match the right offsets. Apply the + * mapping here to translate from VBT to internal convention. + */ + /* static const int rkl_port_mapping[][3] = { + [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, + [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, + [PORT_C] = { -1 }, + [PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, + [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, + }; + */ + + return __dvo_port_to_port(ARRAY_SIZE(port_mapping), + ARRAY_SIZE(port_mapping[0]), + port_mapping, + dvo_port); +} + +static void parse_ddi_port(i915_CONTROLLER *controller, + const struct child_device_config *child, + UINT8 bdb_version) +{ + struct ddi_vbt_port_info *info; + BOOLEAN is_dvi, is_hdmi, is_dp, is_edp, is_crt; + enum port port; + port = dvo_port_to_port(controller, child->dvo_port); + if (port == PORT_NONE) + return; + + info = &controller->vbt.ddi_port_info[port]; + info->port = port; + + if (info->child) + { + PRINT_DEBUG(EFI_D_ERROR, + "More than one child device for port %c in VBT, using the first.\n", + port_name(port)); + return; + } + + is_dvi = (child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING) != 0; + is_dp = (child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT) != 0; + is_crt = (child->device_type & DEVICE_TYPE_ANALOG_OUTPUT) != 0; + is_hdmi = is_dvi && ((child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0); + is_edp = is_dp && ((child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR) != 0); + + if (port == PORT_A && is_dvi) + { + PRINT_DEBUG(EFI_D_ERROR, + "VBT claims port A supports DVI%s, ignoring\n", + is_hdmi ? "/HDMI" : ""); + is_dvi = FALSE; + is_hdmi = FALSE; + } + + info->supports_dvi = is_dvi; + info->supports_hdmi = is_hdmi; + info->supports_dp = is_dp; + info->supports_edp = is_edp; + + if (bdb_version >= 195) + info->supports_typec_usb = child->dp_usb_type_c; + + if (bdb_version >= 209) + info->supports_tbt = child->tbt; + + PRINT_DEBUG(EFI_D_ERROR, + "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d USB-Type-C:%d TBT:%d type:%04x\n", + port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, + info->supports_typec_usb, info->supports_tbt, child->device_type); + + if (is_dvi) + { + UINT8 ddc_pin; + + ddc_pin = map_ddc_pin(controller, child->ddc_pin); + // if (intel_gmbus_is_valid_pin(controller, ddc_pin)) { + info->alternate_ddc_pin = ddc_pin; + sanitize_ddc_pin(controller, port); + /* } else { + DebugPrint(EFI_D_ERROR, + "Port %c has invalid DDC pin %d, " + "sticking to defaults\n", + port_name(port), ddc_pin); + } */ + } + + if (is_dp) + { + info->alternate_aux_channel = child->aux_channel; + + sanitize_aux_ch(controller, port); + } + + if (bdb_version >= 158) + { + /* The VBT HDMI level shift values match the table we have. */ + UINT8 hdmi_level_shift = child->hdmi_level_shifter_value; + PRINT_DEBUG(EFI_D_ERROR, + "VBT HDMI level shift for port %c: %d\n", + port_name(port), + hdmi_level_shift); + info->hdmi_level_shift = hdmi_level_shift; + info->hdmi_level_shift_set = TRUE; + } + + /* if (bdb_version >= 204) { + int max_tmds_clock; + + switch (child->hdmi_max_data_rate) { + default: + MISSING_CASE(child->hdmi_max_data_rate); + fallthrough; + case HDMI_MAX_DATA_RATE_PLATFORM: + max_tmds_clock = 0; + break; + case HDMI_MAX_DATA_RATE_297: + max_tmds_clock = 297000; + break; + case HDMI_MAX_DATA_RATE_165: + max_tmds_clock = 165000; + break; + } + + if (max_tmds_clock) + DebugPrint(EFI_D_ERROR, + "VBT HDMI max TMDS clock for port %c: %d kHz\n", + port_name(port), max_tmds_clock); + info->max_tmds_clock = max_tmds_clock; + } */ + + /* Parse the I_boost config for SKL and above */ + if (bdb_version >= 196 && child->iboost) + { + info->dp_boost_level = translate_iboost(child->dp_iboost_level); + PRINT_DEBUG(EFI_D_ERROR, + "VBT (e)DP boost level for port %c: %d\n", + port_name(port), info->dp_boost_level); + info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level); + PRINT_DEBUG(EFI_D_ERROR, + "VBT HDMI boost level for port %c: %d\n", + port_name(port), info->hdmi_boost_level); + } + + /* DP max link rate for CNL+ */ + if (bdb_version >= 216) + { + switch (child->dp_max_link_rate) + { + default: + case VBT_DP_MAX_LINK_RATE_HBR3: + info->dp_max_link_rate = 810000; + break; + case VBT_DP_MAX_LINK_RATE_HBR2: + info->dp_max_link_rate = 540000; + break; + case VBT_DP_MAX_LINK_RATE_HBR: + info->dp_max_link_rate = 270000; + break; + case VBT_DP_MAX_LINK_RATE_LBR: + info->dp_max_link_rate = 162000; + break; + } + PRINT_DEBUG(EFI_D_ERROR, + "VBT DP max link rate for port %c: %d\n", + port_name(port), info->dp_max_link_rate); + } + + info->child = child; +} + +void parse_ddi_ports(i915_CONTROLLER *controller, UINT8 bdb_version) +{ + /* struct display_device_data *devdata; + + if (!HAS_DDI(controller) && !IS_CHERRYVIEW(controller)) + return; + */ + if (bdb_version < 155) + return; + struct context context; + struct bdb_header bdb; + bdb.version = bdb_version; + context.bdb = &bdb; + for (int i = 0; i < controller->opRegion->numChildren; i++) + { + dump_child_device(&context, &controller->opRegion->children[i]); + parse_ddi_port(controller, &controller->opRegion->children[i], bdb_version); //TODO Update to dyn version + } + //list_for_each_entry(devdata, &controller->vbt.display_devices, node) +} +/* Common defaults which may be overridden by VBT. */ +static void +init_vbt_defaults(i915_CONTROLLER *controller) +{ + //enum port port; + + // controller->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; + + // /* Default to having backlight */ + // controller->vbt.backlight.present = true; + + // /* LFP panel data */ + // controller->vbt.lvds_dither = 1; + + // /* SDVO panel data */ + // controller->vbt.sdvo_lvds_vbt_mode = NULL; + + // /* general features */ + // controller->vbt.int_tv_support = 1; + // controller->vbt.int_crt_support = 1; + + // /* driver features */ + // controller->vbt.int_lvds_support = 1; + + // /* Default to using SSC */ + // controller->vbt.lvds_use_ssc = 1; + // /* + // * Core/SandyBridge/IvyBridge use alternative (120MHz) reference + // * clock for LVDS. + // */ + // controller->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(controller, + // !HAS_PCH_SPLIT(controller)); + // PRINT_DEBUG(EFI_D_ERROR,"Set default to SSC at %d kHz\n", controller->vbt.lvds_ssc_freq); + + // for (port = PORT_A; port < I915_MAX_PORTS; port++) + // { + // struct ddi_vbt_port_info *info = + // &controller->vbt.ddi_port_info[port]; + + // info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN; + // } +} +static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) +{ + const void *_vbt = vbt; + + return _vbt + vbt->bdb_offset; +} + +/** + * intel_bios_init - find VBT and initialize settings from the BIOS + * @controller: i915 device instance + * + * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT + * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also + * initialize some defaults if the VBT is not present at all. + */ +void intel_bios_init(i915_CONTROLLER *controller) +{ + //struct pci_dev *pdev = controller->drm.pdev; + const struct vbt_header *vbt = controller->opRegion->vbt; + const struct bdb_header *bdb; + // u8 *bios = NULL; + + // if (!HAS_DISPLAY(controller)) + // { + // PRINT_DEBUG(EFI_D_ERROR,"Skipping VBT init due to disabled display.\n"); + // return; + // } + + init_vbt_defaults(controller); + + // /* If the OpRegion does not have VBT, look in PCI ROM. */ + // if (!vbt) + // { + // size_t size; + + // bios = pci_map_rom(pdev, &size); + // if (!bios) + // goto out; + + // vbt = find_vbt(bios, size); + // if (!vbt) + // goto out; + + // PRINT_DEBUG(EFI_D_ERROR,"Found valid VBT in PCI ROM\n"); + // } + + bdb = get_bdb_header(vbt); + + PRINT_DEBUG(EFI_D_ERROR, "VBT signature \"%.*s\", BDB version %d\n", + (int)sizeof(vbt->signature), vbt->signature, bdb->version); + + /* Grab useful general definitions */ + // parse_general_features(controller, bdb); + // parse_general_definitions(controller, bdb); + // parse_lfp_panel_data(controller, bdb); + // parse_lfp_backlight(controller, bdb); + // parse_sdvo_panel_data(controller, bdb); + // parse_driver_features(controller, bdb); + parse_edp(controller, bdb); + //parse_psr(controller, bdb); + // parse_mipi_config(controller, bdb); + // parse_mipi_sequence(controller, bdb); + + /* Further processing on pre-parsed data */ + // parse_sdvo_device_mapping(controller, bdb->version); + parse_ddi_ports(controller, bdb->version); + + if (!vbt) + { + PRINT_DEBUG(EFI_D_ERROR, "Failed to find VBIOS tables"); + } + // if (!vbt) + // { + // DRM_INFO("Failed to find VBIOS tables (VBT)\n"); + // init_vbt_missing_defaults(controller); + // } + + // if (bios) + // pci_unmap_rom(pdev, bios); +} +static EFI_STATUS decode_vbt_child_blocks(struct context *context, + const struct bdb_block *block) +{ + EFI_STATUS status = EFI_SUCCESS; + const struct bdb_general_definitions *defs = block->data; + int child_dev_num; + + child_dev_num = (block->size - sizeof(*defs)) / defs->child_dev_size; + /* + PRINT_DEBUG(EFI_D_ERROR,"CRT DDC GMBUS addr: 0x%02x\n", defs->crt_ddc_gmbus_pin); + PRINT_DEBUG(EFI_D_ERROR,"Use ACPI DPMS CRT power states: %s\n", + YESNO(defs->dpms_acpi)); + PRINT_DEBUG(EFI_D_ERROR,"Skip CRT detect at boot: %s\n", + YESNO(defs->skip_boot_crt_detect)); + PRINT_DEBUG(EFI_D_ERROR,"Use DPMS on AIM devices: %s\n", YESNO(defs->dpms_aim)); */ + if (block->id == BDB_GENERAL_DEFINITIONS) + { + PRINT_DEBUG(EFI_D_ERROR, "Boot display type: 0x%02x%02x\n", defs->boot_display[1], + defs->boot_display[0]); + } + PRINT_DEBUG(EFI_D_ERROR, "Child device size: %d\n", defs->child_dev_size); + PRINT_DEBUG(EFI_D_ERROR, "Child device count: %d\n", child_dev_num); + + status = get_child_devices(context, defs->devices, + child_dev_num, defs->child_dev_size); + int i; + + for (i = 0; i < child_dev_num; i++) + { + + //children[i] = *child; + dump_child_device(context, &(context->children[i])); + } + return status; +} + +EFI_STATUS decodeVBT(struct intel_opregion *opRegion, int vbt_off) +{ + struct vbt_header *vbt = opRegion->vbt; + UINT8 *VBIOS = (UINT8 *)opRegion->header; + EFI_STATUS status = EFI_SUCCESS; + //UINT8 *VBIOS; + // int index; + // int fd; + //struct vbt_header *vbt = NULL; + int bdb_off; + // const char *filename = NULL; + //int size = 8192; + struct context context = { + .panel_type = -1, + }; + + context.vbt = vbt; + bdb_off = vbt_off + vbt->bdb_offset; + + context.bdb = (const struct bdb_header *)(VBIOS + bdb_off); + context.size = 8192; + PRINT_DEBUG(EFI_D_ERROR, "vbt: 0x%04x, bdb: 0x%04x, sig: %s, bsig: %s \n", context.vbt, context.bdb, context.vbt->signature, context.bdb->signature); + + struct bdb_block *block = (struct bdb_block *)AllocatePool(sizeof(block)); + + status = find_section(&context, BDB_GENERAL_DEFINITIONS, block); + if (!EFI_ERROR(status)) + { + status = decode_vbt_child_blocks(&context, block); + } + else + { + status = find_section(&context, BDB_CHILD_DEVICE_TABLE, block); + if (!EFI_ERROR(status)) + { + + status = decode_vbt_child_blocks(&context, block); + } + } + if (!EFI_ERROR(status)) + { + opRegion->children = context.children; + opRegion->numChildren = context.numChildren; + } + return status; +} + +enum aux_ch intel_bios_port_aux_ch(i915_CONTROLLER *dev_priv, + enum port port) +{ + const struct ddi_vbt_port_info *info = + &dev_priv->vbt.ddi_port_info[port]; + enum aux_ch aux_ch; + + if (!info->alternate_aux_channel) + { + aux_ch = (enum aux_ch)port; + + PRINT_DEBUG(EFI_D_ERROR, + "using AUX %c for port %c (platform default)\n", + aux_ch_name(aux_ch), port_name(port)); + return aux_ch; + } + + switch (info->alternate_aux_channel) + { + case DP_AUX_A: + aux_ch = AUX_CH_A; + break; + case DP_AUX_B: + aux_ch = AUX_CH_B; + break; + case DP_AUX_C: + aux_ch = AUX_CH_C; + break; + case DP_AUX_D: + aux_ch = AUX_CH_D; + break; + case DP_AUX_E: + aux_ch = AUX_CH_E; + break; + case DP_AUX_F: + aux_ch = AUX_CH_F; + break; + case DP_AUX_G: + aux_ch = AUX_CH_G; + break; + // case DP_AUX_H: + // aux_ch = AUX_CH_H; + // break; + // case DP_AUX_I: + // aux_ch = AUX_CH_I; + // break; + default: + aux_ch = AUX_CH_A; + break; + } + + PRINT_DEBUG(EFI_D_ERROR, "using AUX %c for port %c (VBT)\n", + aux_ch_name(aux_ch), port_name(port)); + + return aux_ch; +} \ No newline at end of file diff --git a/intel_opregion.h b/intel_opregion.h new file mode 100644 index 0000000..37010f1 --- /dev/null +++ b/intel_opregion.h @@ -0,0 +1,1121 @@ +/* + * Copyright 2008 Intel Corporation + * Copyright 2008 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL INTEL AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include "QemuFwCfgLib.h" +#include "i915_display.h" +#include "i915ovmf.h" +#include +#include +#include +#include +#include "i915_debug.h" +#include +#include +#include +#include +#include +#include +#include +#include "i915_controller.h" + +#ifndef INTEL_OPREGION +#define INTEL_OPREGION + +#define OPREGION_HEADER_OFFSET 0 +#define OPREGION_ACPI_OFFSET 0x100 +#define ACPI_CLID 0x01ac /* current lid state indicator */ +#define ACPI_CDCK 0x01b0 /* current docking state indicator */ +#define OPREGION_SWSCI_OFFSET 0x200 +#define OPREGION_ASLE_OFFSET 0x300 +#define OPREGION_VBT_OFFSET 0x400 +#define OPREGION_ASLE_EXT_OFFSET 0x1C00 + +#define OPREGION_SIGNATURE "IntelGraphicsMem" +#define MBOX_ACPI (1 << 0) +#define MBOX_SWSCI (1 << 1) +#define MBOX_ASLE (1 << 2) +#define MBOX_ASLE_EXT (1 << 4) + +struct context +{ + const struct vbt_header *vbt; + const struct bdb_header *bdb; + int size; + struct child_device_config *children; + UINT8 numChildren; + UINT32 devid; + int panel_type; + BOOLEAN dump_all_panel_types; + BOOLEAN hexdump; +}; + +struct bdb_block +{ + UINT8 id; + UINT32 size; + const void *data; +}; + +struct dumper +{ + UINT8 id; + const char *name; + void (*dump)(struct context *context, + const struct bdb_block *block); +}; + +enum bdb_block_id +{ + BDB_GENERAL_FEATURES = 1, + BDB_GENERAL_DEFINITIONS = 2, + BDB_OLD_TOGGLE_LIST = 3, + BDB_MODE_SUPPORT_LIST = 4, + BDB_GENERIC_MODE_TABLE = 5, + BDB_EXT_MMIO_REGS = 6, + BDB_SWF_IO = 7, + BDB_SWF_MMIO = 8, + BDB_PSR = 9, + BDB_MODE_REMOVAL_TABLE = 10, + BDB_CHILD_DEVICE_TABLE = 11, + BDB_DRIVER_FEATURES = 12, + BDB_DRIVER_PERSISTENCE = 13, + BDB_EXT_TABLE_PTRS = 14, + BDB_DOT_CLOCK_OVERRIDE = 15, + BDB_DISPLAY_SELECT = 16, + BDB_DRIVER_ROTATION = 18, + BDB_DISPLAY_REMOVE = 19, + BDB_OEM_CUSTOM = 20, + BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ + BDB_SDVO_LVDS_OPTIONS = 22, + BDB_SDVO_PANEL_DTDS = 23, + BDB_SDVO_LVDS_PNP_IDS = 24, + BDB_SDVO_LVDS_POWER_SEQ = 25, + BDB_TV_OPTIONS = 26, + BDB_EDP = 27, + BDB_LVDS_OPTIONS = 40, + BDB_LVDS_LFP_DATA_PTRS = 41, + BDB_LVDS_LFP_DATA = 42, + BDB_LVDS_BACKLIGHT = 43, + BDB_LVDS_POWER = 44, + BDB_MIPI_CONFIG = 52, + BDB_MIPI_SEQUENCE = 53, + BDB_COMPRESSION_PARAMETERS = 56, + BDB_SKIP = 254, /* VBIOS private block, ignore */ +}; +#define port_name(p) ((p) + 'A') + +#define for_each_port(__port) \ + for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) + +/* Get to bdb section of vbt. THen Scan through to read off the ids of the blocks until we find general definitions or legacy child devices. THen read them +* +*/ +struct bdb_legacy_child_devices +{ + UINT8 child_dev_size; + UINT8 devices[0]; /* presumably 7 * 33 */ +} __attribute__((packed)); +/* Driver readiness indicator */ +#define ASLE_ARDY_READY (1 << 0) +#define ASLE_ARDY_NOT_READY (0 << 0) + +/* ASLE Interrupt Command (ASLC) bits */ +#define ASLC_SET_ALS_ILLUM (1 << 0) +#define ASLC_SET_BACKLIGHT (1 << 1) +#define ASLC_SET_PFIT (1 << 2) +#define ASLC_SET_PWM_FREQ (1 << 3) +#define ASLC_SUPPORTED_ROTATION_ANGLES (1 << 4) +#define ASLC_BUTTON_ARRAY (1 << 5) +#define ASLC_CONVERTIBLE_INDICATOR (1 << 6) +#define ASLC_DOCKING_INDICATOR (1 << 7) +#define ASLC_ISCT_STATE_CHANGE (1 << 8) +#define ASLC_REQ_MSK 0x1ff +/* response bits */ +#define ASLC_ALS_ILLUM_FAILED (1 << 10) +#define ASLC_BACKLIGHT_FAILED (1 << 12) +#define ASLC_PFIT_FAILED (1 << 14) +#define ASLC_PWM_FREQ_FAILED (1 << 16) +#define ASLC_ROTATION_ANGLES_FAILED (1 << 18) +#define ASLC_BUTTON_ARRAY_FAILED (1 << 20) +#define ASLC_CONVERTIBLE_FAILED (1 << 22) +#define ASLC_DOCKING_FAILED (1 << 24) +#define ASLC_ISCT_STATE_FAILED (1 << 26) + +/* Technology enabled indicator */ +#define ASLE_TCHE_ALS_EN (1 << 0) +#define ASLE_TCHE_BLC_EN (1 << 1) +#define ASLE_TCHE_PFIT_EN (1 << 2) +#define ASLE_TCHE_PFMB_EN (1 << 3) + +/* ASLE backlight brightness to set */ +#define ASLE_BCLP_VALID (1 << 31) +#define ASLE_BCLP_MSK (~(1 << 31)) + +/* ASLE panel fitting request */ +#define ASLE_PFIT_VALID (1 << 31) +#define ASLE_PFIT_CENTER (1 << 0) +#define ASLE_PFIT_STRETCH_TEXT (1 << 1) +#define ASLE_PFIT_STRETCH_GFX (1 << 2) + +/* PWM frequency and minimum brightness */ +#define ASLE_PFMB_BRIGHTNESS_MASK (0xff) +#define ASLE_PFMB_BRIGHTNESS_VALID (1 << 8) +#define ASLE_PFMB_PWM_MASK (0x7ffffe00) +#define ASLE_PFMB_PWM_VALID (1 << 31) + +#define ASLE_CBLV_VALID (1 << 31) + +/* IUER */ +#define ASLE_IUER_DOCKING (1 << 7) +#define ASLE_IUER_CONVERTIBLE (1 << 6) +#define ASLE_IUER_ROTATION_LOCK_BTN (1 << 4) +#define ASLE_IUER_VOLUME_DOWN_BTN (1 << 3) +#define ASLE_IUER_VOLUME_UP_BTN (1 << 2) +#define ASLE_IUER_WINDOWS_BTN (1 << 1) +#define ASLE_IUER_POWER_BTN (1 << 0) + +/* Software System Control Interrupt (SWSCI) */ +#define SWSCI_SCIC_INDICATOR (1 << 0) +#define SWSCI_SCIC_MAIN_FUNCTION_SHIFT 1 +#define SWSCI_SCIC_MAIN_FUNCTION_MASK (0xf << 1) +#define SWSCI_SCIC_SUB_FUNCTION_SHIFT 8 +#define SWSCI_SCIC_SUB_FUNCTION_MASK (0xff << 8) +#define SWSCI_SCIC_EXIT_PARAMETER_SHIFT 8 +#define SWSCI_SCIC_EXIT_PARAMETER_MASK (0xff << 8) +#define SWSCI_SCIC_EXIT_STATUS_SHIFT 5 +#define SWSCI_SCIC_EXIT_STATUS_MASK (7 << 5) +#define SWSCI_SCIC_EXIT_STATUS_SUCCESS 1 + +#define SWSCI_FUNCTION_CODE(main, sub) \ + ((main) << SWSCI_SCIC_MAIN_FUNCTION_SHIFT | \ + (sub) << SWSCI_SCIC_SUB_FUNCTION_SHIFT) + +/* SWSCI: Get BIOS Data (GBDA) */ +#define SWSCI_GBDA 4 +#define SWSCI_GBDA_SUPPORTED_CALLS SWSCI_FUNCTION_CODE(SWSCI_GBDA, 0) +#define SWSCI_GBDA_REQUESTED_CALLBACKS SWSCI_FUNCTION_CODE(SWSCI_GBDA, 1) +#define SWSCI_GBDA_BOOT_DISPLAY_PREF SWSCI_FUNCTION_CODE(SWSCI_GBDA, 4) +#define SWSCI_GBDA_PANEL_DETAILS SWSCI_FUNCTION_CODE(SWSCI_GBDA, 5) +#define SWSCI_GBDA_TV_STANDARD SWSCI_FUNCTION_CODE(SWSCI_GBDA, 6) +#define SWSCI_GBDA_INTERNAL_GRAPHICS SWSCI_FUNCTION_CODE(SWSCI_GBDA, 7) +#define SWSCI_GBDA_SPREAD_SPECTRUM SWSCI_FUNCTION_CODE(SWSCI_GBDA, 10) + +/* SWSCI: System BIOS Callbacks (SBCB) */ +#define SWSCI_SBCB 6 +#define SWSCI_SBCB_SUPPORTED_CALLBACKS SWSCI_FUNCTION_CODE(SWSCI_SBCB, 0) +#define SWSCI_SBCB_INIT_COMPLETION SWSCI_FUNCTION_CODE(SWSCI_SBCB, 1) +#define SWSCI_SBCB_PRE_HIRES_SET_MODE SWSCI_FUNCTION_CODE(SWSCI_SBCB, 3) +#define SWSCI_SBCB_POST_HIRES_SET_MODE SWSCI_FUNCTION_CODE(SWSCI_SBCB, 4) +#define SWSCI_SBCB_DISPLAY_SWITCH SWSCI_FUNCTION_CODE(SWSCI_SBCB, 5) +#define SWSCI_SBCB_SET_TV_FORMAT SWSCI_FUNCTION_CODE(SWSCI_SBCB, 6) +#define SWSCI_SBCB_ADAPTER_POWER_STATE SWSCI_FUNCTION_CODE(SWSCI_SBCB, 7) +#define SWSCI_SBCB_DISPLAY_POWER_STATE SWSCI_FUNCTION_CODE(SWSCI_SBCB, 8) +#define SWSCI_SBCB_SET_BOOT_DISPLAY SWSCI_FUNCTION_CODE(SWSCI_SBCB, 9) +#define SWSCI_SBCB_SET_PANEL_DETAILS SWSCI_FUNCTION_CODE(SWSCI_SBCB, 10) +#define SWSCI_SBCB_SET_INTERNAL_GFX SWSCI_FUNCTION_CODE(SWSCI_SBCB, 11) +#define SWSCI_SBCB_POST_HIRES_TO_DOS_FS SWSCI_FUNCTION_CODE(SWSCI_SBCB, 16) +#define SWSCI_SBCB_SUSPEND_RESUME SWSCI_FUNCTION_CODE(SWSCI_SBCB, 17) +#define SWSCI_SBCB_SET_SPREAD_SPECTRUM SWSCI_FUNCTION_CODE(SWSCI_SBCB, 18) +#define SWSCI_SBCB_POST_VBE_PM SWSCI_FUNCTION_CODE(SWSCI_SBCB, 19) +#define SWSCI_SBCB_ENABLE_DISABLE_AUDIO SWSCI_FUNCTION_CODE(SWSCI_SBCB, 21) + +#define MAX_DSLP 1500 + +#define OPREGION_SIZE (8 * 1024) + +/* + * Copyright © 2006-2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +/* + * This information is private to VBT parsing in intel_bios.c. + * + * Please do NOT include anywhere else. + */ + +/* + * There are several types of BIOS data blocks (BDBs), each block has + * an ID and size in the first 3 bytes (ID in first, size in next 2). + * Known types are listed below. + */ + +/* + * Block 1 - General Bit Definitions + */ + +struct bdb_general_features +{ + /* bits 1 */ + UINT8 panel_fitting : 2; + UINT8 flexaim : 1; + UINT8 msg_enable : 1; + UINT8 clear_screen : 3; + UINT8 color_flip : 1; + + /* bits 2 */ + UINT8 download_ext_vbt : 1; + UINT8 enable_ssc : 1; + UINT8 ssc_freq : 1; + UINT8 enable_lfp_on_override : 1; + UINT8 disable_ssc_ddt : 1; + UINT8 underscan_vga_timings : 1; + UINT8 display_clock_mode : 1; + UINT8 vbios_hotplug_support : 1; + + /* bits 3 */ + UINT8 disable_smooth_vision : 1; + UINT8 single_dvi : 1; + UINT8 rotate_180 : 1; /* 181 */ + UINT8 fdi_rx_polarity_inverted : 1; + UINT8 vbios_extended_mode : 1; /* 160 */ + UINT8 copy_ilfp_dtd_to_sdvo_lvds_dtd : 1; /* 160 */ + UINT8 panel_best_fit_timing : 1; /* 160 */ + UINT8 ignore_strap_state : 1; /* 160 */ + + /* bits 4 */ + UINT8 legacy_monitor_detect; + + /* bits 5 */ + UINT8 int_crt_support : 1; + UINT8 int_tv_support : 1; + UINT8 int_efp_support : 1; + UINT8 dp_ssc_enable : 1; /* PCH attached eDP supports SSC */ + UINT8 dp_ssc_freq : 1; /* SSC freq for PCH attached eDP */ + UINT8 dp_ssc_dongle_supported : 1; + UINT8 rsvd11 : 2; /* finish byte */ +} __packed; + +/* + * Block 2 - General Bytes Definition + */ + +/* pre-915 */ +#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ +#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ +#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ +#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ + +/* Pre 915 */ +#define DEVICE_TYPE_NONE 0x00 +#define DEVICE_TYPE_CRT 0x01 +#define DEVICE_TYPE_TV 0x09 +#define DEVICE_TYPE_EFP 0x12 +#define DEVICE_TYPE_LFP 0x22 +/* On 915+ */ +#define DEVICE_TYPE_CRT_DPMS 0x6001 +#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 +#define DEVICE_TYPE_TV_COMPOSITE 0x0209 +#define DEVICE_TYPE_TV_MACROVISION 0x0289 +#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c +#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 +#define DEVICE_TYPE_TV_SCART 0x0209 +#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 +#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 +#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 +#define DEVICE_TYPE_EFP_DVI_I 0x6053 +#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 +#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 +#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 +#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 +#define DEVICE_TYPE_LFP_PANELLINK 0x5012 +#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 +#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 +#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 +#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 + +/* Add the device class for LFP, TV, HDMI */ +#define DEVICE_TYPE_INT_LFP 0x1022 +#define DEVICE_TYPE_INT_TV 0x1009 +#define DEVICE_TYPE_HDMI 0x60D2 +#define DEVICE_TYPE_DP 0x68C6 +#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 +#define DEVICE_TYPE_eDP 0x78C6 + +#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) +#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) +#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) +#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) +#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) +#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) +#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) +#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) +#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) +#define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) +#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) +#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) +#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) +#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) +#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) + +/* + * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the + * system, the other bits may or may not be set for eDP outputs. + */ +#define DEVICE_TYPE_eDP_BITS \ + (DEVICE_TYPE_INTERNAL_CONNECTOR | \ + DEVICE_TYPE_MIPI_OUTPUT | \ + DEVICE_TYPE_COMPOSITE_OUTPUT | \ + DEVICE_TYPE_DUAL_CHANNEL | \ + DEVICE_TYPE_LVDS_SIGNALING | \ + DEVICE_TYPE_TMDS_DVI_SIGNALING | \ + DEVICE_TYPE_VIDEO_SIGNALING | \ + DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ + DEVICE_TYPE_ANALOG_OUTPUT) + +#define DEVICE_TYPE_DP_DUAL_MODE_BITS \ + (DEVICE_TYPE_INTERNAL_CONNECTOR | \ + DEVICE_TYPE_MIPI_OUTPUT | \ + DEVICE_TYPE_COMPOSITE_OUTPUT | \ + DEVICE_TYPE_LVDS_SIGNALING | \ + DEVICE_TYPE_TMDS_DVI_SIGNALING | \ + DEVICE_TYPE_VIDEO_SIGNALING | \ + DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ + DEVICE_TYPE_DIGITAL_OUTPUT | \ + DEVICE_TYPE_ANALOG_OUTPUT) + +#define DEVICE_CFG_NONE 0x00 +#define DEVICE_CFG_12BIT_DVOB 0x01 +#define DEVICE_CFG_12BIT_DVOC 0x02 +#define DEVICE_CFG_24BIT_DVOBC 0x09 +#define DEVICE_CFG_24BIT_DVOCB 0x0a +#define DEVICE_CFG_DUAL_DVOB 0x11 +#define DEVICE_CFG_DUAL_DVOC 0x12 +#define DEVICE_CFG_DUAL_DVOBC 0x13 +#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 +#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a + +#define DEVICE_WIRE_NONE 0x00 +#define DEVICE_WIRE_DVOB 0x01 +#define DEVICE_WIRE_DVOC 0x02 +#define DEVICE_WIRE_DVOBC 0x03 +#define DEVICE_WIRE_DVOBB 0x05 +#define DEVICE_WIRE_DVOCC 0x06 +#define DEVICE_WIRE_DVOB_MASTER 0x0d +#define DEVICE_WIRE_DVOC_MASTER 0x0e + +/* dvo_port pre BDB 155 */ +#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ +#define DEVICE_PORT_DVOB 0x01 +#define DEVICE_PORT_DVOC 0x02 + +/* dvo_port BDB 155+ */ +/* dvo_port BDB 155+ */ +#define DVO_PORT_HDMIA 0 +#define DVO_PORT_HDMIB 1 +#define DVO_PORT_HDMIC 2 +#define DVO_PORT_HDMID 3 +#define DVO_PORT_LVDS 4 +#define DVO_PORT_TV 5 +#define DVO_PORT_CRT 6 +#define DVO_PORT_DPB 7 +#define DVO_PORT_DPC 8 +#define DVO_PORT_DPD 9 +#define DVO_PORT_DPA 10 +#define DVO_PORT_DPE 11 /* 193 */ +#define DVO_PORT_HDMIE 12 /* 193 */ +#define DVO_PORT_DPF 13 /* N/A */ +#define DVO_PORT_HDMIF 14 /* N/A */ +#define DVO_PORT_DPG 15 /* 217 */ +#define DVO_PORT_HDMIG 16 /* 217 */ +#define DVO_PORT_DPH 17 /* 217 */ +#define DVO_PORT_HDMIH 18 /* 217 */ +#define DVO_PORT_DPI 19 /* 217 */ +#define DVO_PORT_HDMII 20 /* 217 */ +#define DVO_PORT_MIPIA 21 /* 171 */ +#define DVO_PORT_MIPIB 22 /* 171 */ +#define DVO_PORT_MIPIC 23 /* 171 */ +#define DVO_PORT_MIPID 24 /* 171 */ + +#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */ +#define HDMI_MAX_DATA_RATE_297 1 /* 204 */ +#define HDMI_MAX_DATA_RATE_165 2 /* 204 */ + +#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 + +/* DDC Bus DDI Type 155+ */ +enum vbt_gmbus_ddi +{ + DDC_BUS_DDI_B = 0x1, + DDC_BUS_DDI_C, + DDC_BUS_DDI_D, + DDC_BUS_DDI_F, + ICL_DDC_BUS_DDI_A = 0x1, + ICL_DDC_BUS_DDI_B, + TGL_DDC_BUS_DDI_C, + ICL_DDC_BUS_PORT_1 = 0x4, + ICL_DDC_BUS_PORT_2, + ICL_DDC_BUS_PORT_3, + ICL_DDC_BUS_PORT_4, + TGL_DDC_BUS_PORT_5, + TGL_DDC_BUS_PORT_6, +}; + +#define DP_AUX_A 0x40 +#define DP_AUX_B 0x10 +#define DP_AUX_C 0x20 +#define DP_AUX_D 0x30 +#define DP_AUX_E 0x50 +#define DP_AUX_F 0x60 +#define DP_AUX_G 0x70 + +#define VBT_DP_MAX_LINK_RATE_HBR3 0 +#define VBT_DP_MAX_LINK_RATE_HBR2 1 +#define VBT_DP_MAX_LINK_RATE_HBR 2 +#define VBT_DP_MAX_LINK_RATE_LBR 3 +#define _H_ACTIVE(x) (x[2] + ((x[4] & 0xF0) << 4)) +#define _H_SYNC_OFF(x) (x[8] + ((x[11] & 0xC0) << 2)) +#define _H_SYNC_WIDTH(x) (x[9] + ((x[11] & 0x30) << 4)) +#define _H_BLANK(x) (x[3] + ((x[4] & 0x0F) << 8)) +#define _V_ACTIVE(x) (x[5] + ((x[7] & 0xF0) << 4)) +#define _V_SYNC_OFF(x) ((x[10] >> 4) + ((x[11] & 0x0C) << 2)) +#define _V_SYNC_WIDTH(x) ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)) +#define _V_BLANK(x) (x[6] + ((x[7] & 0x0F) << 8)) +#define _PIXEL_CLOCK(x) (x[0] + (x[1] << 8)) * 10000 + +#define YESNO(val) ((val) ? "yes" : "no") + +struct bdb_general_definitions +{ + /* DDC GPIO */ + UINT8 crt_ddc_gmbus_pin; + + /* DPMS bits */ + UINT8 dpms_acpi : 1; + UINT8 skip_boot_crt_detect : 1; + UINT8 dpms_aim : 1; + UINT8 rsvd1 : 5; /* finish byte */ + + /* boot device bits */ + UINT8 boot_display[2]; + UINT8 child_dev_size; + + /* + * Device info: + * If TV is present, it'll be at devices[0]. + * LVDS will be next, either devices[0] or [1], if present. + * On some platforms the number of device is 6. But could be as few as + * 4 if both TV and LVDS are missing. + * And the device num is related with the size of general definition + * block. It is obtained by using the following formula: + * number = (block_size - sizeof(bdb_general_definitions))/ + * defs->child_dev_size; + */ + UINT8 devices[0]; +} __packed; + +/* + * Block 9 - SRD Feature Block + */ + +struct psr_table +{ + /* Feature bits */ + UINT8 full_link : 1; + UINT8 require_aux_to_wakeup : 1; + UINT8 feature_bits_rsvd : 6; + + /* Wait times */ + UINT8 idle_frames : 4; + UINT8 lines_to_wait : 3; + UINT8 wait_times_rsvd : 1; + + /* TP wake up time in multiple of 100 */ + UINT16 tp1_wakeup_time; + UINT16 tp2_tp3_wakeup_time; +} __packed; + +struct bdb_psr +{ + struct psr_table psr_table[16]; + + /* PSR2 TP2/TP3 wakeup time for 16 panels */ + UINT32 psr2_tp2_tp3_wakeup_time; +} __packed; + +/* + * Block 12 - Driver Features Data Block + */ + +#define BDB_DRIVER_FEATURE_NO_LVDS 0 +#define BDB_DRIVER_FEATURE_INT_LVDS 1 +#define BDB_DRIVER_FEATURE_SDVO_LVDS 2 +#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 + +struct bdb_driver_features +{ + UINT8 boot_dev_algorithm : 1; + UINT8 block_display_switch : 1; + UINT8 allow_display_switch : 1; + UINT8 hotplug_dvo : 1; + UINT8 dual_view_zoom : 1; + UINT8 int15h_hook : 1; + UINT8 sprite_in_clone : 1; + UINT8 primary_lfp_id : 1; + + UINT16 boot_mode_x; + UINT16 boot_mode_y; + UINT8 boot_mode_bpp; + UINT8 boot_mode_refresh; + + UINT16 enable_lfp_primary : 1; + UINT16 selective_mode_pruning : 1; + UINT16 dual_frequency : 1; + UINT16 render_clock_freq : 1; /* 0: high freq; 1: low freq */ + UINT16 nt_clone_support : 1; + UINT16 power_scheme_ui : 1; /* 0: CUI; 1: 3rd party */ + UINT16 sprite_display_assign : 1; /* 0: secondary; 1: primary */ + UINT16 cui_aspect_scaling : 1; + UINT16 preserve_aspect_ratio : 1; + UINT16 sdvo_device_power_down : 1; + UINT16 crt_hotplug : 1; + UINT16 lvds_config : 2; + UINT16 tv_hotplug : 1; + UINT16 hdmi_config : 2; + + UINT8 static_display : 1; + UINT8 reserved2 : 7; + UINT16 legacy_crt_max_x; + UINT16 legacy_crt_max_y; + UINT8 legacy_crt_max_refresh; + + UINT8 hdmi_termination; + UINT8 custom_vbt_version; + /* Driver features data block */ + UINT16 rmpm_enabled : 1; + UINT16 s2ddt_enabled : 1; + UINT16 dpst_enabled : 1; + UINT16 bltclt_enabled : 1; + UINT16 adb_enabled : 1; + UINT16 drrs_enabled : 1; + UINT16 grs_enabled : 1; + UINT16 gpmt_enabled : 1; + UINT16 tbt_enabled : 1; + UINT16 psr_enabled : 1; + UINT16 ips_enabled : 1; + UINT16 reserved3 : 4; + UINT16 pc_feature_valid : 1; +} __packed; + +/* + * Block 22 - SDVO LVDS General Options + */ + +struct bdb_sdvo_lvds_options +{ + UINT8 panel_backlight; + UINT8 h40_set_panel_type; + UINT8 panel_type; + UINT8 ssc_clk_freq; + UINT16 als_low_trip; + UINT16 als_high_trip; + UINT8 sclalarcoeff_tab_row_num; + UINT8 sclalarcoeff_tab_row_size; + UINT8 coefficient[8]; + UINT8 panel_misc_bits_1; + UINT8 panel_misc_bits_2; + UINT8 panel_misc_bits_3; + UINT8 panel_misc_bits_4; +} __packed; + +/* + * Block 23 - SDVO LVDS Panel DTDs + */ + +struct lvds_dvo_timing +{ + UINT16 clock; /**< In 10khz */ + UINT8 hactive_lo; + UINT8 hblank_lo; + UINT8 hblank_hi : 4; + UINT8 hactive_hi : 4; + UINT8 vactive_lo; + UINT8 vblank_lo; + UINT8 vblank_hi : 4; + UINT8 vactive_hi : 4; + UINT8 hsync_off_lo; + UINT8 hsync_pulse_width_lo; + UINT8 vsync_pulse_width_lo : 4; + UINT8 vsync_off_lo : 4; + UINT8 vsync_pulse_width_hi : 2; + UINT8 vsync_off_hi : 2; + UINT8 hsync_pulse_width_hi : 2; + UINT8 hsync_off_hi : 2; + UINT8 himage_lo; + UINT8 vimage_lo; + UINT8 vimage_hi : 4; + UINT8 himage_hi : 4; + UINT8 h_border; + UINT8 v_border; + UINT8 rsvd1 : 3; + UINT8 digital : 2; + UINT8 vsync_positive : 1; + UINT8 hsync_positive : 1; + UINT8 non_interlaced : 1; +} __packed; + +struct bdb_sdvo_panel_dtds +{ + struct lvds_dvo_timing dtds[4]; +} __packed; + +/* + * Block 27 - eDP VBT Block + */ +enum aux_ch +{ + AUX_CH_A, + AUX_CH_B, + AUX_CH_C, + AUX_CH_D, + AUX_CH_E, /* ICL+ */ + AUX_CH_F, + AUX_CH_G, + AUX_CH_H, + AUX_CH_I, +}; +#define aux_ch_name(a) ((a) + 'A') + +#define EDP_18BPP 0 +#define EDP_24BPP 1 +#define EDP_30BPP 2 +#define EDP_RATE_1_62 0 +#define EDP_RATE_2_7 1 +#define EDP_LANE_1 0 +#define EDP_LANE_2 1 +#define EDP_LANE_4 3 +#define EDP_PREEMPHASIS_NONE 0 +#define EDP_PREEMPHASIS_3_5dB 1 +#define EDP_PREEMPHASIS_6dB 2 +#define EDP_PREEMPHASIS_9_5dB 3 +#define EDP_VSWING_0_4V 0 +#define EDP_VSWING_0_6V 1 +#define EDP_VSWING_0_8V 2 +#define EDP_VSWING_1_2V 3 + +struct edp_fast_link_params +{ + UINT8 rate : 4; + UINT8 lanes : 4; + UINT8 preemphasis : 4; + UINT8 vswing : 4; +} __packed; + +struct edp_pwm_delays +{ + UINT16 pwm_on_to_backlight_enable; + UINT16 backlight_disable_to_pwm_off; +} __packed; + +struct edp_full_link_params +{ + UINT8 preemphasis : 4; + UINT8 vswing : 4; +} __packed; + +struct bdb_edp +{ + struct edp_power_seq power_seqs[16]; + UINT32 color_depth; + struct edp_fast_link_params fast_link_params[16]; + UINT32 sdrrs_msa_timing_delay; + + /* ith bit indicates enabled/disabled for (i+1)th panel */ + UINT16 edp_s3d_feature; /* 162 */ + UINT16 edp_t3_optimization; /* 165 */ + UINT64 edp_vswing_preemph; /* 173 */ + UINT16 fast_link_training; /* 182 */ + UINT16 dpcd_600h_write_required; /* 185 */ + struct edp_pwm_delays pwm_delays[16]; /* 186 */ + UINT16 full_link_params_provided; /* 199 */ + struct edp_full_link_params full_link_params[16]; /* 199 */ +} __packed; + +/* + * Block 40 - LFP Data Block + */ + +/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ +#define MODE_MASK 0x3 + +struct bdb_lvds_options +{ + UINT8 panel_type; + UINT8 panel_type2; /* 212 */ + /* LVDS capabilities, stored in a dword */ + UINT8 pfit_mode : 2; + UINT8 pfit_text_mode_enhanced : 1; + UINT8 pfit_gfx_mode_enhanced : 1; + UINT8 pfit_ratio_auto : 1; + UINT8 pixel_dither : 1; + UINT8 lvds_edid : 1; + UINT8 rsvd2 : 1; + UINT8 rsvd4; + /* LVDS Panel channel bits stored here */ + UINT32 lvds_panel_channel_bits; + /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ + UINT16 ssc_bits; + UINT16 ssc_freq; + UINT16 ssc_ddt; + /* Panel color depth defined here */ + UINT16 panel_color_depth; + /* LVDS panel type bits stored here */ + UINT32 dps_panel_type_bits; + /* LVDS backlight control type bits stored here */ + UINT32 blt_control_type_bits; + + UINT16 lcdvcc_s0_enable; /* 200 */ + UINT32 rotation; /* 228 */ +} __packed; + +/* + * Block 41 - LFP Data Table Pointers + */ + +/* LFP pointer table contains entries to the struct below */ +struct lvds_lfp_data_ptr +{ + UINT16 fp_timing_offset; /* offsets are from start of bdb */ + UINT8 fp_table_size; + UINT16 dvo_timing_offset; + UINT8 dvo_table_size; + UINT16 panel_pnp_id_offset; + UINT8 pnp_table_size; +} __packed; + +struct bdb_lvds_lfp_data_ptrs +{ + UINT8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ + struct lvds_lfp_data_ptr ptr[16]; +} __packed; + +/* + * Block 42 - LFP Data Tables + */ + +/* LFP data has 3 blocks per entry */ +struct lvds_fp_timing +{ + UINT16 x_res; + UINT16 y_res; + UINT32 lvds_reg; + UINT32 lvds_reg_val; + UINT32 pp_on_reg; + UINT32 pp_on_reg_val; + UINT32 pp_off_reg; + UINT32 pp_off_reg_val; + UINT32 pp_cycle_reg; + UINT32 pp_cycle_reg_val; + UINT32 pfit_reg; + UINT32 pfit_reg_val; + UINT16 terminator; +} __packed; + +struct lvds_pnp_id +{ + UINT16 mfg_name; + UINT16 product_code; + UINT32 serial; + UINT8 mfg_week; + UINT8 mfg_year; +} __packed; + +struct lvds_lfp_data_entry +{ + struct lvds_fp_timing fp_timing; + struct lvds_dvo_timing dvo_timing; + struct lvds_pnp_id pnp_id; +} __packed; + +struct bdb_lvds_lfp_data +{ + struct lvds_lfp_data_entry data[16]; +} __packed; + +/* + * Block 43 - LFP Backlight Control Data Block + */ + +#define BDB_BACKLIGHT_TYPE_NONE 0 +#define BDB_BACKLIGHT_TYPE_PWM 2 + +struct lfp_backlight_data_entry +{ + UINT8 type : 2; + UINT8 active_low_pwm : 1; + UINT8 obsolete1 : 5; + UINT16 pwm_freq_hz; + UINT8 min_brightness; + UINT8 obsolete2; + UINT8 obsolete3; +} __packed; + +struct lfp_backlight_control_method +{ + UINT8 type : 4; + UINT8 controller : 4; +} __packed; + +struct bdb_lfp_backlight_data +{ + UINT8 entry_size; + struct lfp_backlight_data_entry data[16]; + UINT8 level[16]; + struct lfp_backlight_control_method backlight_control[16]; +} __packed; + +/* Block 52 contains MiPi Panel info + * 6 such enteries will there. Index into correct + * entery is based on the panel_index in #40 LFP + */ +#define MAX_MIPI_CONFIGURATIONS 6 +struct mipi_config +{ + UINT16 panel_id; + + /* General Params */ + UINT32 dithering : 1; + UINT32 rsvd1 : 1; + UINT32 panel_type : 1; + UINT32 panel_arch_type : 2; + UINT32 cmd_mode : 1; + UINT32 vtm : 2; + UINT32 cabc : 1; + UINT32 pwm_blc : 1; + + /* Bit 13:10 + * 000 - Reserved, 001 - RGB565, 002 - RGB666, + * 011 - RGB666Loosely packed, 100 - RGB888, + * others - rsvd + */ + UINT32 videomode_color_format : 4; + + /* Bit 15:14 + * 0 - No rotation, 1 - 90 degree + * 2 - 180 degree, 3 - 270 degree + */ + UINT32 rotation : 2; + UINT32 bta : 1; + UINT32 rsvd2 : 15; + + /* 2 byte Port Description */ + UINT16 dual_link : 2; + UINT16 lane_cnt : 2; + UINT16 pixel_overlap : 3; + UINT16 rsvd3 : 9; + + /* 2 byte DSI COntroller params */ + /* 0 - Using DSI PHY, 1 - TE usage */ + UINT16 dsi_usage : 1; + UINT16 rsvd4 : 15; + + UINT8 rsvd5[5]; + UINT32 dsi_ddr_clk; + UINT32 bridge_ref_clk; + + UINT8 byte_clk_sel : 2; + UINT8 rsvd6 : 6; + + /* DPHY Flags */ + UINT16 dphy_param_valid : 1; + UINT16 eot_disabled : 1; + UINT16 clk_stop : 1; + UINT16 rsvd7 : 13; + + UINT32 hs_tx_timeout; + UINT32 lp_rx_timeout; + UINT32 turn_around_timeout; + UINT32 device_reset_timer; + UINT32 master_init_timer; + UINT32 dbi_bw_timer; + UINT32 lp_byte_clk_val; + + /* 4 byte Dphy Params */ + UINT32 prepare_cnt : 6; + UINT32 rsvd8 : 2; + UINT32 clk_zero_cnt : 8; + UINT32 trail_cnt : 5; + UINT32 rsvd9 : 3; + UINT32 exit_zero_cnt : 6; + UINT32 rsvd10 : 2; + + UINT32 clk_lane_switch_cnt; + UINT32 hl_switch_cnt; + + UINT32 rsvd11[6]; + + /* timings based on dphy spec */ + UINT8 tclk_miss; + UINT8 tclk_post; + UINT8 rsvd12; + UINT8 tclk_pre; + UINT8 tclk_prepare; + UINT8 tclk_settle; + UINT8 tclk_term_enable; + UINT8 tclk_trail; + UINT16 tclk_prepare_clkzero; + UINT8 rsvd13; + UINT8 td_term_enable; + UINT8 teot; + UINT8 ths_exit; + UINT8 ths_prepare; + UINT16 ths_prepare_hszero; + UINT8 rsvd14; + UINT8 ths_settle; + UINT8 ths_skip; + UINT8 ths_trail; + UINT8 tinit; + UINT8 tlpx; + UINT8 rsvd15[3]; + + /* GPIOs */ + UINT8 panel_enable; + UINT8 bl_enable; + UINT8 pwm_enable; + UINT8 reset_r_n; + UINT8 pwr_down_r; + UINT8 stdby_r_n; + +} __attribute__((packed)); + +/* Block 52 contains MiPi configuration block + * 6 * bdb_mipi_config, followed by 6 pps data + * block below + */ +struct mipi_pps_data +{ + UINT16 panel_on_delay; + UINT16 bl_enable_delay; + UINT16 bl_disable_delay; + UINT16 panel_off_delay; + UINT16 panel_power_cycle_delay; +} __attribute__((packed)); + +struct bdb_mipi_config +{ + struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; + struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; +} __packed; + +/* + * Block 53 - MIPI Sequence Block + */ + +struct bdb_mipi_sequence +{ + UINT8 version; + UINT8 data[0]; /* up to 6 variable length blocks */ +} __packed; + +/* + * Block 56 - Compression Parameters + */ + +#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 +#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 +#define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 +#define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 + +#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ +#define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value)*2) + +struct dsc_compression_parameters_entry +{ + UINT8 version_major : 4; + UINT8 version_minor : 4; + + UINT8 rc_buffer_block_size : 2; + UINT8 reserved1 : 6; + + /* + * Buffer size in bytes: + * + * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes + */ + UINT8 rc_buffer_size; + UINT32 slices_per_line; + + UINT8 line_buffer_depth : 4; + UINT8 reserved2 : 4; + + /* Flag Bits 1 */ + UINT8 block_prediction_enable : 1; + UINT8 reserved3 : 7; + + UINT8 max_bpp; /* mapping */ + + /* Color depth capabilities */ + UINT8 reserved4 : 1; + UINT8 support_8bpc : 1; + UINT8 support_10bpc : 1; + UINT8 support_12bpc : 1; + UINT8 reserved5 : 4; + + UINT16 slice_height; +} __packed; + +struct bdb_compression_parameters +{ + UINT16 entry_size; + struct dsc_compression_parameters_entry data[16]; +} __packed; +void intel_bios_init(i915_CONTROLLER *controller); + +EFI_STATUS decodeVBT(struct intel_opregion *opRegion, int vbt_off); +void parse_ddi_ports(i915_CONTROLLER *dev_priv, UINT8 bdb_version); +enum aux_ch intel_bios_port_aux_ch(i915_CONTROLLER *dev_priv, + enum port port); +#endif diff --git a/intel_vbt.c b/intel_vbt.c new file mode 100644 index 0000000..acd7c8f --- /dev/null +++ b/intel_vbt.c @@ -0,0 +1,24 @@ +#include +#include +#include +#include +#include +#include + +#include "QemuFwCfgLib.h" +#include "i915_display.h" +#include "i915_gop.h" +#include "i915ovmf.h" +#include +#include +#include +#include +#include "i915_debug.h" +#include +#include +#include +#include +#include +#include +#include +#include "intel_opregion.h" diff --git a/intel_vbt.h b/intel_vbt.h new file mode 100644 index 0000000..e69de29 diff --git a/iommu.sh b/iommu.sh new file mode 100755 index 0000000..e3559fb --- /dev/null +++ b/iommu.sh @@ -0,0 +1,8 @@ +#!/bin/bash +shopt -s nullglob +for g in /sys/kernel/iommu_groups/*; do + echo "IOMMU Group ${g##*/}:" + for d in $g/devices/*; do + echo -e "\t$(lspci -nns ${d##*/})" + done; +done; \ No newline at end of file diff --git a/log.txt b/log.txt new file mode 100755 index 0000000..0c329a3 --- /dev/null +++ b/log.txt @@ -0,0 +1,841 @@ +Loading previous configuration from /home/patrick/i915dev/Conf/BuildEnv.sh +WORKSPACE: /home/patrick/i915dev +EDK_TOOLS_PATH: /home/patrick/i915dev/edk2/BaseTools +CONF_PATH: /home/patrick/i915dev/Conf +make: Entering directory '/home/patrick/i915dev/edk2/BaseTools' +make -C Source/C +make[1]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C' +Attempting to detect HOST_ARCH from 'uname -m': x86_64 +Detected HOST_ARCH of X64 using uname. +mkdir -p . +make -C Common +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/Common' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/Common' +make -C BrotliCompress +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/BrotliCompress' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/BrotliCompress' +make -C VfrCompile +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/VfrCompile' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/VfrCompile' +make -C EfiRom +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/EfiRom' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/EfiRom' +make -C GenFfs +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenFfs' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenFfs' +make -C GenFv +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenFv' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenFv' +make -C GenFw +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenFw' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenFw' +make -C GenSec +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenSec' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenSec' +make -C GenCrc32 +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenCrc32' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/GenCrc32' +make -C LzmaCompress +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/LzmaCompress' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/LzmaCompress' +make -C Split +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/Split' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/Split' +make -C TianoCompress +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/TianoCompress' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/TianoCompress' +make -C VolInfo +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/VolInfo' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/VolInfo' +make -C DevicePath +make[2]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/DevicePath' +make[2]: Nothing to be done for 'all'. +make[2]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C/DevicePath' +Finished building BaseTools C Tools with HOST_ARCH=X64 +make[1]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/C' +make -C Source/Python +make[1]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Source/Python' +make[1]: Nothing to be done for 'all'. +make[1]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Source/Python' +make -C Tests +make[1]: Entering directory '/home/patrick/i915dev/edk2/BaseTools/Tests' +make[1]: Leaving directory '/home/patrick/i915dev/edk2/BaseTools/Tests' +make: Leaving directory '/home/patrick/i915dev/edk2/BaseTools' + + +Processing meta-data . +Architecture(s) = X64 +Build target = DEBUG +Toolchain = GCC5 + +Active Platform = /home/patrick/i915dev/i915ovmfPkg/i915ovmf.dsc + +FLASH_DEFINITION = None + +Library instances of module [/home/patrick/i915dev/i915ovmfPkg/i915ovmf.inf] [X64]: + BaseLib : /home/patrick/i915dev/edk2/MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib : /home/patrick/i915dev/edk2/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + DebugLib : /home/patrick/i915dev/edk2/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + DevicePathLib : /home/patrick/i915dev/edk2/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf + FrameBufferBltLib : /home/patrick/i915dev/edk2/MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf + MemoryAllocationLib : /home/patrick/i915dev/edk2/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + PcdLib : /home/patrick/i915dev/edk2/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PciLib : /home/patrick/i915dev/edk2/OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + UefiBootServicesTableLib : /home/patrick/i915dev/edk2/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiDriverEntryPoint : /home/patrick/i915dev/edk2/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiLib : /home/patrick/i915dev/edk2/MdePkg/Library/UefiLib/UefiLib.inf + MemEncryptSevLib : /home/patrick/i915dev/edk2/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf + CacheMaintenanceLib : /home/patrick/i915dev/edk2/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + CpuLib : /home/patrick/i915dev/edk2/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PrintLib : /home/patrick/i915dev/edk2/MdePkg/Library/BasePrintLib/BasePrintLib.inf + UefiRuntimeServicesTableLib : /home/patrick/i915dev/edk2/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + PciCf8Lib : /home/patrick/i915dev/edk2/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciExpressLib : /home/patrick/i915dev/edk2/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + IoLib : /home/patrick/i915dev/edk2/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + SerialPortLib : /home/patrick/i915dev/edk2/PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf + DebugPrintErrorLevelLib : /home/patrick/i915dev/edk2/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +.DEPEX[i915ovmf] (+i915ovmf) = ['(', 'TRUE', ')'] + + + + + + + + + + + + + + + + + + + +DEPEX[i915ovmf] (+UefiDriverEntryPoint) = ['(', 'TRUE', ')', 'AND', '(', '{ 0x665E3FF6, 0x46CC, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }}', 'AND', '{ 0x26BACCB1, 0x6F42, 0x11D4, { 0xBC, 0xE7, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }}', 'AND', '{ 0x26BACCB2, 0x6F42, 0x11D4, { 0xBC, 0xE7, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }}', 'AND', '{ 0x1DA97072, 0xBDDC, 0x4B30, { 0x99, 0xF1, 0x72, 0xA0, 0xB5, 0x6F, 0xFF, 0x2A }}', 'AND', '{ 0x27CFAC87, 0x46CC, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }}', 'AND', '{ 0x27CFAC88, 0x46CC, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }}', 'AND', '{ 0xb7dfb4e1, 0x052f, 0x449f, { 0x87, 0xbe, 0x98, 0x18, 0xfc, 0x91, 0xb7, 0x33 }}', 'AND', '{ 0xA46423E3, 0x4617, 0x49F1, { 0xB9, 0xFF, 0xD1, 0xBF, 0xA9, 0x11, 0x58, 0x39 }}', 'AND', '{ 0x26BACCB3, 0x6F42, 0x11D4, { 0xBC, 0xE7, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }}', 'AND', '{ 0x6441F818, 0x6362, 0x4E44, { 0xB5, 0x70, 0x7D, 0xBA, 0x31, 0xDD, 0x24, 0x53 }}', 'AND', '{ 0x1E5668E2, 0x8481, 0x11D4, { 0xBC, 0xF1, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }}', 'AND', '{ 0x665E3FF5, 0x46CC, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }}', ')'] + + + + done! +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +make: Nothing to be done for 'tbuild'. +i915 Message: efi_main(938)Driver starts! +i915 Message: i915ControllerDriverSupported(843)found device 8086-9BCA 0 +i915 Message: i915ControllerDriverStart(498)start +i915 Message: i915ControllerDriverStart(528)set pci attrs +i915 Message: i915ControllerDriverStart(559)made gop path +i915 Message: i915ControllerDriverStart(571)installed child handle +i915 Message: i915ControllerDriverStart(579)before QEMU shenanigans +i915 Message: SetupFwcfgStuff(465)BdsmSize=8388608 +i915 Message: decodeVBT(1068)vbt: 0x7FBFD400, bdb: 0x7FBFD430, sig: $B KLK d0¥í0, bsig: BO_AABOKätþ +i915 Message: find_section(69)finding section 2 +i915 Message: decode_vbt_child_blocks(1028)Boot display type: 0x0000 +i915 Message: decode_vbt_child_blocks(1031)Child device size: 39 +i915 Message: decode_vbt_child_blocks(1032)Child device count: 8 +i915 Message: SetupOpRegion(339)SetupOpRegion: OpRegion @ 0x7FBFD000 size 0x2000 in 2 pages +i915 Message: SetupStolenMemory(408)SetupStolenMemory: : stolen memory @ 0x7E100000 size 0x800000 +i915 Message: i915ControllerDriverStart(597)SetupFwcfgStuff returns 0 +i915 Message: i915ControllerDriverStart(599)after QEMU shenanigans +i915 Message: intel_bios_init(979)VBT signature " $B KLK d0¥í0", BDB version 228 +i915 Message: parse_ddi_port(764)Port A VBT info: CRT:0 DVI:0 HDMI:0 DP:1 eDP:1 USB-Type-C:0 TBT:0 type:1806 +i915 Message: parse_ddi_port(796)VBT HDMI level shift for port A: 0 +i915 Message: parse_ddi_port(861)VBT DP max link rate for port A: 810000 +i915 Message: parse_ddi_port(764)Port B VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 USB-Type-C:0 TBT:0 type:60D6 +i915 Message: parse_ddi_port(796)VBT HDMI level shift for port B: 0 +i915 Message: parse_ddi_port(861)VBT DP max link rate for port B: 810000 +i915 Message: parse_ddi_port(764)Port C VBT info: CRT:0 DVI:0 HDMI:0 DP:1 eDP:0 USB-Type-C:0 TBT:0 type:68C6 +i915 Message: parse_ddi_port(796)VBT HDMI level shift for port C: 0 +i915 Message: parse_ddi_port(861)VBT DP max link rate for port C: 810000 +i915 Message: parse_ddi_port(732)More than one child device for port A in VBT, using the first. +i915 Message: parse_ddi_port(732)More than one child device for port A in VBT, using the first. +i915 Message: parse_ddi_port(732)More than one child device for port A in VBT, using the first. +i915 Message: parse_ddi_port(732)More than one child device for port A in VBT, using the first. +i915 Message: parse_ddi_port(732)More than one child device for port A in VBT, using the first. +i915 Message: DisplayInit(677)power well enabled F00003FF +i915 Message: DisplayInit(709)CDCLK = 080002A1 +i915 Message: DisplayInit(722)DBUF timeout +i915 Message: DisplayInit(743)_PLANE_BUF_CFG_1_A = 00000000 +i915 Message: DisplayInit(746)_PLANE_BUF_CFG_1_A = 035B0000 (after) +i915 Message: DisplayInit(754)SFUSE_STRAP = 00000106 +i915 Message: setOutputPath(380)Port A VBT info: DVI:0 HDMI:0 DP:1 eDP:1 +i915 Message: setOutputPath(390)Port Is Connected! +i915 Message: SetupPPS(3265)Setting up PPS +i915 Message: intel_pps_dump_state(537)cur t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0 +i915 Message: intel_pps_dump_state(537)vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 6000 +i915 Message: intel_dp_init_panel_power_sequencer(598)Assigning val 2000 as cur: 0, vbt: 2000, spec: 2100 +i915 Message: intel_dp_init_panel_power_sequencer(599)Assigning val 10 as cur: 0, vbt: 10, spec: 500 +i915 Message: intel_dp_init_panel_power_sequencer(600)Assigning val 2000 as cur: 0, vbt: 2000, spec: 500 +i915 Message: intel_dp_init_panel_power_sequencer(601)Assigning val 500 as cur: 0, vbt: 500, spec: 5000 +i915 Message: intel_dp_init_panel_power_sequencer(602)Assigning val 6000 as cur: 0, vbt: 6000, spec: 6100 +i915 Message: intel_dp_init_panel_power_sequencer(613)panel power up delay 200, power down delay 50, power cycle delay 600 +i915 Message: intel_dp_init_panel_power_sequencer(617)backlight on delay 1, off delay 200 +i915 Message: intel_dp_init_panel_power_sequencer_registers(733)panel power sequencer register settings: PP_ON #x, PP_OFF #x, PP_DIV #x +i915 Message: intel_bios_port_aux_ch(1145)using AUX A for port A (VBT) +i915 Message: setOutputPath(403)Port is DP/EdP. Aux_ch is 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: wait_panel_power_cycle(1249)Wait for panel power cycle +i915 Message: wait_panel_power_cycle(1261)Panel Power Cycle Delay: 600 +i915 Message: wait_panel_status(1217)mask 380C720F value 00000000 status 00000000 control ABCD0000 +i915 Message: wait_panel_status(1229)Wait complete +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x00000000 PP_CONTROL: 0xABCD0008 +i915 Message: edp_panel_vdd_on(1354)eDP port panel power wasn't enabled +i915 Message: ReadEDIDDP(85)trying DP aux 0 +i915 Message: ReadEDIDDP(159)reading DP aux 0 +00 FF FF FF FF FF FF 00 +0D AE E4 14 00 00 00 00 +27 1C 01 04 A5 1F 11 78 +02 EE 95 A3 54 4C 99 26 +0F 50 54 00 00 00 01 01 +01 01 01 01 01 01 01 01 +01 01 01 01 01 01 B4 3B +80 4A 71 38 34 40 50 3C +68 00 35 AD 10 00 00 18 +00 00 00 FE 00 4E 31 34 +30 48 43 52 2D 47 41 32 +0A 20 00 00 00 FE 00 43 +4D 4E 0A 20 20 20 20 20 +20 20 20 20 00 00 00 FE +00 4E 31 34 30 48 43 52 +2D 47 41 32 0A 20 00 FC +i915 Message: setOutputPath(406)ReadEDIDDP returned 0 +i915 Message: setOutputPath(415)DUsing Connector Mode: 3, On Port 0i915 Message: DisplayInit(801)got EDID: +00 FF FF FF FF FF FF 00 +0D AE E4 14 00 00 00 00 +27 1C 01 04 A5 1F 11 78 +02 EE 95 A3 54 4C 99 26 +0F 50 54 00 00 00 01 01 +01 01 01 01 01 01 01 01 +01 01 01 01 01 01 B4 3B +80 4A 71 38 34 40 50 3C +68 00 35 AD 10 00 00 18 +00 00 00 FE 00 4E 31 34 +30 48 43 52 2D 47 41 32 +0A 20 00 00 00 FE 00 43 +4D 4E 0A 20 20 20 20 20 +20 20 20 20 00 00 00 FE +00 4E 31 34 30 48 43 52 +2D 47 41 32 0A 20 00 FC +i915 Message: i915ControllerDriverStart(626)bar ranges - 810000000 1000000, 800000000 10000000 +i915 Message: i915ControllerDriverStart(634)aperture at 800000000 +i915 Message: i915ControllerDriverStart(642)i915: gmadr = 00000000, size = 00000000, hgmadr = 00000000, hsize = 00000000 +i915 Message: i915ControllerDriverStart(664)1920x1080 clock=152840 +i915 Message: i915ControllerDriverStart(680)i915: ggtt_base at 810800000, entries: 00000000 00000000, backing fb: 7D900000, 7F9E00 bytes +i915 Message: i915ControllerDriverStart(716)progressed to mline 717, status is 0 +i915 Message: setDisplayGraphicsMode(497)set mode 0 +i915 Message: SetupClockeDP(788)DPLL 1 not locked +i915 Message: SetupClockeDP(796)Link Rate: 0 +i915 Message: SetupClockeDP(820)DPLL_CTRL1 = 00000545 +i915 Message: SetupClockeDP(821)_DPLL1_CFGCR1 = 00000000 +i915 Message: SetupClockeDP(822)_DPLL1_CFGCR2 = 00000000 +i915 Message: SetupClockeDP(832)DPLL 1 locked +i915 Message: SetupClockeDP(846)port is 0 +i915 Message: SetupClockeDP(862)DPLL_CTRL2 = 00A00003 +i915 Message: setDisplayGraphicsMode(524)PP_CTL: ABCD0008, PP_STAT 00000000 +i915 Message: edp_panel_on(1366)Turn eDP port panel power on +i915 Message: wait_panel_power_cycle(1249)Wait for panel power cycle +i915 Message: wait_panel_power_cycle(1261)Panel Power Cycle Delay: 600 +i915 Message: wait_panel_status(1217)mask 380C720F value 00000000 status 00000000 control ABCD0008 +i915 Message: wait_panel_status(1229)Wait complete +i915 Message: wait_panel_on(1234)Wait for panel power on +i915 Message: wait_panel_status(1217)mask 300C720F value 000C7208 status 80000008 control ABCD000B +i915 Message: wait_panel_status(1225)Panel status timeout: status 80000008 control ABCD000B +i915 Message: wait_panel_status(1229)Wait complete +i915 Message: i915_dp_get_link_config(2825)max_clock index: 2, common_len: 3, clock rate[0]: 162000, max_link_rate: 540000, clockrate[3]: 0 +i915 Message: i915_dp_get_link_config(2842)DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 152840KHz +i915 Message: intel_dp_link_training_clock_recovery(2245)Using LINK_BW_SET value 6 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_clock_recovery(2305)clock recovery OK +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 80 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2491)Channel equalization failed 5 times +i915 Message: _TrainDisplayPort(2900) Link Training failed at link rate = 162000, lane count = 4 +i915 Message: SetupClockeDP(788)DPLL 1 not locked +i915 Message: SetupClockeDP(796)Link Rate: 162000 +i915 Message: SetupClockeDP(820)DPLL_CTRL1 = 00000545 +i915 Message: SetupClockeDP(821)_DPLL1_CFGCR1 = 00000000 +i915 Message: SetupClockeDP(822)_DPLL1_CFGCR2 = 00000000 +i915 Message: SetupClockeDP(832)DPLL 1 locked +i915 Message: SetupClockeDP(846)port is 0 +i915 Message: SetupClockeDP(862)DPLL_CTRL2 = 00A00003 +i915 Message: intel_dp_link_training_clock_recovery(2245)Using LINK_BW_SET value 6 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_clock_recovery(2305)clock recovery OK +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 80 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 33 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2491)Channel equalization failed 5 times +i915 Message: _TrainDisplayPort(2900) Link Training failed at link rate = 162000, lane count = 4 +i915 Message: intel_dp_can_link_train_fallback_for_edp(2557)Mode: 458520, Max:1080000 +i915 Message: SetupClockeDP(788)DPLL 1 not locked +i915 Message: SetupClockeDP(796)Link Rate: 540000 +i915 Message: SetupClockeDP(820)DPLL_CTRL1 = 000004C5 +i915 Message: SetupClockeDP(821)_DPLL1_CFGCR1 = 00000000 +i915 Message: SetupClockeDP(822)_DPLL1_CFGCR2 = 00000000 +i915 Message: SetupClockeDP(832)DPLL 1 locked +i915 Message: SetupClockeDP(846)port is 0 +i915 Message: SetupClockeDP(862)DPLL_CTRL2 = 00A00003 +i915 Message: intel_dp_link_training_clock_recovery(2245)Using LINK_BW_SET value 20 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_clock_recovery(2305)clock recovery OK +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 0 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 0 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 0 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 0 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 80 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 33 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 0 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 0 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: drm_dp_channel_eq_ok(2405)NO Lane Align +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1938)this_v:0 v:0 this_p:0 p:0 +i915 Message: intel_dp_get_adjust_train(1953)v:0 p:0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[0]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[1]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[2]: 0 +i915 Message: intel_dp_get_adjust_train(1963)TrainSet[3]: 0 +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2491)Channel equalization failed 5 times +i915 Message: _TrainDisplayPort(2900) Link Training failed at link rate = 540000, lane count = 2 +i915 Message: intel_dp_can_link_train_fallback_for_edp(2557)Mode: 458520, Max:540000 +i915 Message: SetupClockeDP(788)DPLL 1 not locked +i915 Message: SetupClockeDP(796)Link Rate: 270000 +i915 Message: SetupClockeDP(820)DPLL_CTRL1 = 000004C5 +i915 Message: SetupClockeDP(821)_DPLL1_CFGCR1 = 00000000 +i915 Message: SetupClockeDP(822)_DPLL1_CFGCR2 = 00000000 +i915 Message: SetupClockeDP(832)DPLL 1 locked +i915 Message: SetupClockeDP(846)port is 0 +i915 Message: SetupClockeDP(862)DPLL_CTRL2 = 00A00003 +i915 Message: intel_dp_link_training_clock_recovery(2245)Using LINK_BW_SET value 10 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: g4x_set_signal_levels(2058)Using signal levels 00000000 +i915 Message: g4x_set_signal_levels(2060)Using vswing level 0, pre-emphasis level 0 +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_clock_recovery(2305)clock recovery OK +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: intel_dp_link_training_channel_equalization(2451)Read Link Status 0: 77 +i915 Message: intel_dp_link_training_channel_equalization(2452)Read Link Status 1: 0 +i915 Message: intel_dp_link_training_channel_equalization(2453)Read Link Status 2: 81 +i915 Message: intel_dp_link_training_channel_equalization(2454)Read Link Status 3: 0 +i915 Message: intel_dp_link_training_channel_equalization(2455)Read Link Status 4: 0 +i915 Message: intel_dp_link_training_channel_equalization(2456)Read Link Status 5: 0 +i915 Message: intel_dp_link_training_channel_equalization(2472)Channel EQ done. DP Training successful +i915 Message: edp_panel_vdd_on(1333)Turning eDP VDD on +i915 Message: edp_panel_vdd_on(1346)PP_STATUS: 0x80000008 PP_CONTROL: 0xABCD000B +i915 Message: _TrainDisplayPort(2893)Link Rate: 270000, lane count: 2 +i915 Message: intel_dp_can_link_train_fallback_for_edp(2557)Mode: 458520, Max:540000 +i915 Message: setDisplayGraphicsMode(527)progressed to line 528, status is 0 +i915 Message: SetupTranscoderAndPipe(112)before TranscoderPipe 3 +i915 Message: intel_link_compute_m_n(3079)intel_link_compute_m_n: bpp: 24, lanes: 2, pclock:152840, link_clock: 270000 +i915 Message: intel_link_compute_m_n(3084)progressed to dpline 3085 +i915 Message: intel_link_compute_m_n(3087)progressed to dpline 3088 +i915 Message: compute_m_n(3052)progressed to dpline 3053 +i915 Message: compute_m_n(3059)progressed to dpline 3060 +i915 Message: compute_m_n(3061)m: 3668160, n: 4320000, ret_n: 8388608 +i915 Message: intel_link_compute_m_n(3093)progressed to dpline 3094 +i915 Message: compute_m_n(3052)progressed to dpline 3053 +i915 Message: compute_m_n(3059)progressed to dpline 3060 +i915 Message: compute_m_n(3061)m: 152840, n: 270000, ret_n: 524288 +i915 Message: intel_link_compute_m_n(3098)progressed to dpline 3099 +i915 Message: SetupTranscoderAndPipeEDP(3235)progressed to dpline 3236 +i915 Message: SetupTranscoderAndPipeEDP(3237)PIPEEDP_DATA_M1 (6F030) = 7E6CAFAC +i915 Message: SetupTranscoderAndPipeEDP(3238)PIPEEDP_DATA_N1 (6F034) = 00800000 +i915 Message: SetupTranscoderAndPipeEDP(3239)PIPEEDP_LINK_M1 (6F040) = 00048751 +i915 Message: SetupTranscoderAndPipeEDP(3240)PIPEEDP_LINK_N1 (6F044) = 00080000 +i915 Message: SetupTranscoderAndPipeEDP(3250)HTOTAL_EDP (6F000) = 08C9077F +i915 Message: SetupTranscoderAndPipeEDP(3251)HBLANK_EDP (6F004) = 08C9077F +i915 Message: SetupTranscoderAndPipeEDP(3252)HSYNC_EDP (6F008) = 080B07CF +i915 Message: SetupTranscoderAndPipeEDP(3253)VTOTAL_EDP (6F00C) = 046B0437 +i915 Message: SetupTranscoderAndPipeEDP(3254)VBLANK_EDP (6F010) = 046B0437 +i915 Message: SetupTranscoderAndPipeEDP(3255)VSYNC_EDP (6F014) = 0445043D +i915 Message: SetupTranscoderAndPipeEDP(3256)PIPEASRC (6001C) = 077F0437 +i915 Message: SetupTranscoderAndPipeEDP(3257)BCLRPAT_EDP (6F020) = 00000000 +i915 Message: SetupTranscoderAndPipeEDP(3258)VSYNCSHIFT_EDP (6F028) = 00000000 +i915 Message: SetupTranscoderAndPipeEDP(3260)before pipe gamma +i915 Message: SetupTranscoderAndPipe(133)after TranscoderPipe +i915 Message: ConfigurePipeGamma(139)before gamma +i915 Message: ConfigurePipeGamma(145)before pipe gamma +i915 Message: ConfigurePipeGamma(152)REGISTER 7F008 +i915 Message: ConfigurePipeGamma(155)Setting _SKL_BOTTOM_COLOR_A to 0 +i915 Message: ConfigurePipeGamma(158)Setting _GAMMA_MODE_A to 0 +i915 Message: ConfigurePipeGamma(161)Finished Pipe Gamma +i915 Message: setDisplayGraphicsMode(565)before DDI +i915 Message: ConfigureTransDDI(179)DDI Port: 0 +i915 Message: ConfigureTransDDI(201)REG TransDDI: 82000002 +i915 Message: setDisplayGraphicsMode(575)after DDI +i915 Message: setDisplayGraphicsMode(601)pipe enabled +i915 Message: EnableDDI(220)DDI_BUF_CTL(port) = 80000013 +i915 Message: EnableDDI(279)SAVED BTIS 00000010 +i915 Message: EnableDDI(285)DDI_BUF_CTL(port) = 80000013 +i915 Message: setDisplayGraphicsMode(611)progressed to line 612, status is0 +i915 Message: SetupAndEnablePlane(320)plane enabled, dspcntr: 84002000, FbBase: 800000000 +i915 Message: PrintReg(456)Reg PP_CONTROL(000C7204), val: 00000007 +i915 Message: PrintReg(456)Reg _BXT_BLC_PWM_FREQ1(000C8254), val: 0001D4C0 +i915 Message: PrintReg(456)Reg _BXT_BLC_PWM_DUTY1(000C8258), val: 0001D4C0 +i915 Message: PrintReg(456)Reg PP_STATUS(000C7200), val: 80000008 +i915 Message: PrintReg(456)Reg DP_TP_CTL(00064040), val: 80040300 +i915 Message: PrintReg(456)Reg _PIPEEDPCONF(0007F008), val: C0000000 +i915 Message: PrintReg(456)Reg _PIPEACONF(00070008), val: 00000000 +i915 Message: PrintReg(456)Reg _DSPAOFFSET(000701A4), val: 00000000 +i915 Message: PrintReg(456)Reg _DSPAPOS(0007018C), val: 00000000 +i915 Message: PrintReg(456)Reg _DSPASTRIDE(00070188), val: 00000078 +i915 Message: PrintReg(456)Reg _DSPASIZE(00070190), val: 0437077F +i915 Message: PrintReg(456)Reg _DSPACNTR(00070180), val: 84002000 +i915 Message: PrintReg(456)Reg _DSPASURF(0007019C), val: 00000000 +i915 Message: PrintReg(456)Reg DDI_BUF_CTL(00064000), val: 80000013 +i915 Message: PrintReg(456)Reg _TRANS_DDI_FUNC_CTL_EDP(0006F400), val: 82000002 +i915 Message: PrintReg(456)Reg _TRANS_EDP_MSA_MISC(0006F410), val: 00000021 +i915 Message: PrintReg(456)Reg _SKL_BOTTOM_COLOR_A(00070034), val: 00000000 +i915 Message: PrintReg(456)Reg _GAMMA_MODE_A(0004A480), val: 00000000 +i915 Message: PrintReg(456)Reg _LGC_PALETTE_A(0004A000), val: 00000000 +i915 Message: PrintReg(456)Reg DISPIO_CR_TX_BMU_CR0(0006C00C), val: 00000000 +i915 Message: PrintReg(456)Reg PP_ON(000C7208), val: 00000000 +i915 Message: PrintReg(456)Reg PP_OFF(000C720C), val: 00000000 +i915 Message: PrintReg(456)Reg PP_DIVISOR(00061210), val: 00000006 +i915 Message: PrintReg(456)Reg DPLL_CTRL1(0006C058), val: 000004C5 +i915 Message: PrintReg(456)Reg LCPLL2_CTL(00046014), val: 80000000 +i915 Message: PrintReg(456)Reg LCPLL1_CTL(00046010), val: C0000000 +i915 Message: PrintReg(456)Reg DPLL_CTRL2(0006C05C), val: 00A00003 +i915 Message: PrintAllRegs(490)Controller: LR: 270000, LC: 2, Port: 0, ContType: 3, DPLL: 1 +i915 Message: i915GraphicsSetupOutput(195)progressed to gopline 196, status is 0 +i915 Message: i915ControllerDriverStart(719)progressed to mline 720, status is 0 +i915 Message: i915ControllerDriverStart(747)gop ready +i915 Message: i915GraphicsOutputQueryMode(33)i915: query mode +[=3hi915 Message: i915GraphicsOutputQueryMode(33)i915: query mode +i915 Message: i915GraphicsOutputQueryMode(33)i915: query mode +i915 Message: i915GraphicsOutputQueryMode(33)i915: query mode +[=3hBdsDxe: failed to load Boot0001 "UEFI QEMU HARDDISK QM00001 " from PciRoot(0x0)/Pci(0x1,0x1)/Ata(Primary,Master,0x0): Not Found +BdsDxe: failed to load Boot0001 "UEFI QEMU HARDDISK QM00001 " from PciRoot(0x0)/Pci(0x1,0x1)/Ata(Primary,Master,0x0): Not Found +BdsDxe: loading Boot0002 "EFI Internal Shell" from Fv(7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1) +BdsDxe: loading Boot0002 "EFI Internal Shell" from Fv(7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1) +BdsDxe: starting Boot0002 "EFI Internal Shell" from Fv(7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1) +BdsDxe: starting Boot0002 "EFI Internal Shell" from Fv(7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1) +UEFI Interactive Shell v2.2 +UEFI Interactive Shell v2.2 +EDK II +EDK II +UEFI v2.70 (EDK II, 0x00010000) +UEFI v2.70 (EDK II, 0x00010000) +Mapping tableMapping table + + FS0: FS0: Alias(s):Alias(s):F0a:;BLK0: + PciRoot(0x0)/Pci(0x1,0x1)/Ata(0x0) +F0a:;BLK0: + PciRoot(0x0)/Pci(0x1,0x1)/Ata(0x0) +Press Press ESCESC in 5 seconds to skip in 5 seconds to skip startup.nshstartup.nsh or any other key to continue. or any other key to continue.Press Press ESCESC in 4 seconds to skip in 4 seconds to skip startup.nshstartup.nsh or any other key to continue. or any other key to continue.Press Press ESCESC in 3 seconds to skip in 3 seconds to skip startup.nshstartup.nsh or any other key to continue. or any other key to continue.Press Press ESCESC in 2 seconds to skip in 2 seconds to skip startup.nshstartup.nsh or any other key to continue. or any other key to continue.Press Press ESCESC in 1 seconds to skip in 1 seconds to skip startup.nshstartup.nsh or any other key to continue. or any other key to continue. + +Shell> Shell>  \ No newline at end of file diff --git a/reg.txt b/reg.txt new file mode 100644 index 0000000..039ae64 --- /dev/null +++ b/reg.txt @@ -0,0 +1,239 @@ + GEN6_RP_CONTROL (0x0000a024): 0x00000d92 (enabled) + GEN6_RPNSWREQ (0x0000a008): 0x09000000 + GEN6_RP_DOWN_TIMEOUT (0x0000a010): 0x00000000 + GEN6_RP_INTERRUPT_LIMITS (0x0000a014): 0x00000000 + GEN6_RP_UP_THRESHOLD (0x0000a02c): 0x00001bd5 + GEN6_RP_UP_EI (0x0000a068): 0x00001d4c + GEN6_RP_DOWN_EI (0x0000a06c): 0x00005dc0 + GEN6_RP_IDLE_HYSTERSIS (0x0000a070): 0x0000000a + GEN6_RC_STATE (0x0000a094): 0x00040000 + GEN6_RC_CONTROL (0x0000a090): 0x00040000 + GEN6_RC1_WAKE_RATE_LIMIT (0x0000a098): 0x00000000 + GEN6_RC6_WAKE_RATE_LIMIT (0x0000a09c): 0x00360000 + GEN6_RC_EVALUATION_INTERVAL (0x0000a0a8): 0x0001e848 + GEN6_RC_IDLE_HYSTERSIS (0x0000a0ac): 0x00000019 + GEN6_RC_SLEEP (0x0000a0b0): 0x00000000 + GEN6_RC1e_THRESHOLD (0x0000a0b4): 0x00000000 + GEN6_RC6_THRESHOLD (0x0000a0b8): 0x0000927c + GEN6_RC_VIDEO_FREQ (0x0000a00c): 0x09000000 + GEN6_PMIER (0x0004402c): 0x00000000 + GEN6_PMIMR (0x00044024): 0x00000000 + GEN6_PMINTRMSK (0x0000a168): 0x00003ffe + FENCE START 0 (0x00100000): 0x00840001 + FENCE END 0 (0x00100004): 0x0104603b + FENCE START 1 (0x00100008): 0x010c0001 + FENCE END 1 (0x0010000c): 0x018c603b + FENCE START 2 (0x00100010): 0x00000000 + FENCE END 2 (0x00100014): 0x00000000 + FENCE START 3 (0x00100018): 0x00000000 + FENCE END 3 (0x0010001c): 0x00000000 + FENCE START 4 (0x00100020): 0x00000000 + FENCE END 4 (0x00100024): 0x00000000 + FENCE START 5 (0x00100028): 0x00000000 + FENCE END 5 (0x0010002c): 0x00000000 + FENCE START 6 (0x00100030): 0x00000000 + FENCE END 6 (0x00100034): 0x00000000 + FENCE START 7 (0x00100038): 0x00000000 + FENCE END 7 (0x0010003c): 0x00000000 + FENCE START 8 (0x00100040): 0x00000000 + FENCE END 8 (0x00100044): 0x00000000 + FENCE START 9 (0x00100048): 0x00000000 + FENCE END 9 (0x0010004c): 0x00000000 + FENCE START 10 (0x00100050): 0x00000000 + FENCE END 10 (0x00100054): 0x00000000 + FENCE START 11 (0x00100058): 0x00000000 + FENCE END 11 (0x0010005c): 0x00000000 + FENCE START 12 (0x00100060): 0x00000000 + FENCE END 12 (0x00100064): 0x00000000 + FENCE START 13 (0x00100068): 0x00000000 + FENCE END 13 (0x0010006c): 0x00000000 + FENCE START 14 (0x00100070): 0x00000000 + FENCE END 14 (0x00100074): 0x00000000 + FENCE START 15 (0x00100078): 0x00000000 + FENCE END 15 (0x0010007c): 0x00000000 + FENCE START 16 (0x00100080): 0x00000000 + FENCE END 16 (0x00100084): 0x00000000 + FENCE START 17 (0x00100088): 0x00000000 + FENCE END 17 (0x0010008c): 0x00000000 + FENCE START 18 (0x00100090): 0x00000000 + FENCE END 18 (0x00100094): 0x00000000 + FENCE START 19 (0x00100098): 0x00000000 + FENCE END 19 (0x0010009c): 0x00000000 + FENCE START 20 (0x001000a0): 0x00000000 + FENCE END 20 (0x001000a4): 0x00000000 + FENCE START 20 (0x001000a0): 0x00000000 + FENCE END 20 (0x001000a4): 0x00000000 + FENCE START 21 (0x001000a8): 0x00000000 + FENCE END 21 (0x001000ac): 0x00000000 + FENCE START 22 (0x001000b0): 0x00000000 + FENCE END 22 (0x001000b4): 0x00000000 + FENCE START 23 (0x001000b8): 0x00000000 + FENCE END 23 (0x001000bc): 0x00000000 + FENCE START 24 (0x001000c0): 0x00000000 + FENCE END 24 (0x001000c4): 0x00000000 + FENCE START 25 (0x001000c8): 0x00000000 + FENCE END 25 (0x001000cc): 0x00000000 + FENCE START 26 (0x001000d0): 0x00000000 + FENCE END 26 (0x001000d4): 0x00000000 + FENCE START 27 (0x001000d8): 0x00000000 + FENCE END 27 (0x001000dc): 0x00000000 + FENCE START 28 (0x001000e0): 0x00000000 + FENCE END 28 (0x001000e4): 0x00000000 + FENCE START 29 (0x001000e8): 0x00000000 + FENCE END 29 (0x001000ec): 0x00000000 + FENCE START 30 (0x001000f0): 0x00000000 + FENCE END 30 (0x001000f4): 0x00000000 + FENCE START 31 (0x001000f8): 0x00000000 + FENCE END 31 (0x001000fc): 0x00000000 + HSW_PWR_WELL_CTL1 (0x00045400): 0x10000005 + HSW_PWR_WELL_CTL2 (0x00045404): 0x3000000f + HSW_PWR_WELL_CTL3 (0x00045408): 0x00000000 + HSW_PWR_WELL_CTL4 (0x0004540c): 0x10000005 + HSW_PWR_WELL_CTL5 (0x00045410): 0x050f0000 + HSW_PWR_WELL_CTL6 (0x00045414): 0x0000050f + PIPE_DDI_FUNC_CTL_A (0x00060400): 0x00000000 (disabled, no port, HDMI, 8 bpc, -VSync, -HSync, EDP A ON, x1) + PIPE_DDI_FUNC_CTL_B (0x00061400): 0x00000000 (disabled, no port, HDMI, 8 bpc, -VSync, -HSync, EDP A ON, x1) + PIPE_DDI_FUNC_CTL_C (0x00062400): 0x00000000 (disabled, no port, HDMI, 8 bpc, -VSync, -HSync, EDP A ON, x1) + PIPE_DDI_FUNC_CTL_EDP (0x0006f400): 0x82000002 (enabled, no port, DP SST, 8 bpc, -VSync, -HSync, EDP A ON, x2) + DP_TP_CTL_A (0x00064040): 0x80040300 + DP_TP_CTL_B (0x00064140): 0x00000000 + DP_TP_CTL_C (0x00064240): 0x00000000 + DP_TP_CTL_D (0x00064340): 0x00000000 + DP_TP_CTL_E (0x00064440): 0x00000000 + DP_TP_STATUS_B (0x00064144): 0x00000000 + DP_TP_STATUS_C (0x00064244): 0x00000000 + DP_TP_STATUS_D (0x00064344): 0x00000000 + DP_TP_STATUS_E (0x00064444): 0x00000000 + DDI_BUF_CTL_A (0x00064000): 0x80000003 (enabled not reversed x2 detected) + DDI_BUF_CTL_B (0x00064100): 0x00000000 (disabled not reversed x1 not detected) + DDI_BUF_CTL_C (0x00064200): 0x00000000 (disabled not reversed x1 not detected) + DDI_BUF_CTL_D (0x00064300): 0x00000000 (disabled not reversed x1 not detected) + DDI_BUF_CTL_E (0x00064400): 0x00000000 (disabled not reversed x1 not detected) + SPLL_CTL (0x00046020): 0x00000000 + LCPLL_CTL (0x00130040): 0x00000000 + WRPLL_CTL1 (0x00046040): 0x00202418 + WRPLL_CTL2 (0x00046060): 0x00202418 + PORT_CLK_SEL_A (0x00046100): 0x70000000 (SPLL) + PORT_CLK_SEL_B (0x00046104): 0x70000000 (SPLL) + PORT_CLK_SEL_C (0x00046108): 0x70000000 (SPLL) + PORT_CLK_SEL_D (0x0004610c): 0x70000000 (SPLL) + PORT_CLK_SEL_E (0x00046110): 0x70000000 (SPLL) + PIPE_CLK_SEL_A (0x00046140): 0x00000000 (None) + PIPE_CLK_SEL_B (0x00046144): 0x00000000 (None) + PIPE_CLK_SEL_C (0x00046148): 0x00000000 (None) + WM_PIPE_A (0x00045100): 0x00000000 (primary 0, sprite 0, pipe 0) + WM_PIPE_B (0x00045104): 0x00000000 (primary 0, sprite 0, pipe 0) + WM_PIPE_C (0x00045200): 0x00000000 (primary 0, sprite 0, pipe 0) + WM_LP1 (0x00045108): 0x00000000 (disabled, latency 0, fbc 0, pri 0, cur 0) + WM_LP2 (0x0004510c): 0x00000000 (disabled, latency 0, fbc 0, pri 0, cur 0) + WM_LP3 (0x00045110): 0x00000000 (disabled, latency 0, fbc 0, pri 0, cur 0) + WM_LP1_SPR (0x00045120): 0x00000000 + WM_LP2_SPR (0x00045124): 0x00000000 + WM_LP3_SPR (0x00045128): 0x00000000 + WM_MISC (0x00045260): 0x20000000 + WM_SR_CNT (0x00045264): 0x51c3af16 + PIPE_WM_LINETIME_A (0x00045270): 0x00000076 + PIPE_WM_LINETIME_B (0x00045274): 0x00000000 + PIPE_WM_LINETIME_C (0x00045278): 0x00000000 + WM_DBG (0x00045280): 0x4c000000 + SFUSE_STRAP (0x000c2014): 0x00000106 (display enabled, crt no, lane reversal no, port b yes, port c yes, port d no) + PIPEASRC (0x0006001c): 0x077f0437 (1920, 1080) + DSPACNTR (0x00070180): 0xc4042400 (enabled) + DSPASTRIDE (0x00070188): 0x0000000f (0) + DSPASURF (0x0007019c): 0x010c0000 + DSPATILEOFF (0x000701a4): 0x00000000 (0, 0) + PIPEBSRC (0x0006101c): 0x00000000 (1, 1) + DSPBCNTR (0x00071180): 0x00000000 (disabled) + DSPBSTRIDE (0x00071188): 0x00000000 (0) + DSPBSURF (0x0007119c): 0x00000000 + DSPBTILEOFF (0x000711a4): 0x00000000 (0, 0) + PIPECSRC (0x0006201c): 0x00000000 (1, 1) + DSPCCNTR (0x00072180): 0x00000000 (disabled) + DSPCSTRIDE (0x00072188): 0x00000000 (0) + DSPCSURF (0x0007219c): 0x00000000 + DSPCTILEOFF (0x000721a4): 0x00000000 (0, 0) + PIPEACONF (0x00070008): 0x00000000 (disabled, inactive, pf-pd) + HTOTAL_A (0x00060000): 0x00000000 (1 active, 1 total) + HBLANK_A (0x00060004): 0x00000000 (1 start, 1 end) + HSYNC_A (0x00060008): 0x00000000 (1 start, 1 end) + VTOTAL_A (0x0006000c): 0x00000000 (1 active, 1 total) + VBLANK_A (0x00060010): 0x00000000 (1 start, 1 end) + VSYNC_A (0x00060014): 0x00000000 (1 start, 1 end) + VSYNCSHIFT_A (0x00060028): 0x00000000 + PIPEA_DATA_M1 (0x00060030): 0x00000000 (TU 1, val 0x0 0) + PIPEA_DATA_N1 (0x00060034): 0x00000000 (val 0x0 0) + PIPEA_LINK_M1 (0x00060040): 0x00000000 (val 0x0 0) + PIPEA_LINK_N1 (0x00060044): 0x00000000 (val 0x0 0) + PIPEBCONF (0x00071008): 0x00000000 (disabled, inactive, pf-pd) + HTOTAL_B (0x00061000): 0x00000000 (1 active, 1 total) + HBLANK_B (0x00061004): 0x00000000 (1 start, 1 end) + HSYNC_B (0x00061008): 0x00000000 (1 start, 1 end) + VTOTAL_B (0x0006100c): 0x00000000 (1 active, 1 total) + VBLANK_B (0x00061010): 0x00000000 (1 start, 1 end) + VSYNC_B (0x00061014): 0x00000000 (1 start, 1 end) + VSYNCSHIFT_B (0x00061028): 0x00000000 + PIPEB_DATA_M1 (0x00061030): 0x00000000 (TU 1, val 0x0 0) + PIPEB_DATA_N1 (0x00061034): 0x00000000 (val 0x0 0) + PIPEB_LINK_M1 (0x00061040): 0x00000000 (val 0x0 0) + PIPEB_LINK_N1 (0x00061044): 0x00000000 (val 0x0 0) + PIPECCONF (0x00072008): 0x00000000 (disabled, inactive, pf-pd) + HTOTAL_C (0x00062000): 0x00000000 (1 active, 1 total) + HBLANK_C (0x00062004): 0x00000000 (1 start, 1 end) + HSYNC_C (0x00062008): 0x00000000 (1 start, 1 end) + VTOTAL_C (0x0006200c): 0x00000000 (1 active, 1 total) + VBLANK_C (0x00062010): 0x00000000 (1 start, 1 end) + VSYNC_C (0x00062014): 0x00000000 (1 start, 1 end) + VSYNCSHIFT_C (0x00062028): 0x00000000 + PIPEC_DATA_M1 (0x00062030): 0x00000000 (TU 1, val 0x0 0) + PIPEC_DATA_N1 (0x00062034): 0x00000000 (val 0x0 0) + PIPEC_LINK_M1 (0x00062040): 0x00000000 (val 0x0 0) + PIPEC_LINK_N1 (0x00062044): 0x00000000 (val 0x0 0) + PIPEEDPCONF (0x0007f008): 0xc0000000 (enabled, active, pf-pd) + HTOTAL_EDP (0x0006f000): 0x08c9077f (1920 active, 2250 total) + HBLANK_EDP (0x0006f004): 0x08c9077f (1920 start, 2250 end) + HSYNC_EDP (0x0006f008): 0x080b07cf (2000 start, 2060 end) + VTOTAL_EDP (0x0006f00c): 0x046b0437 (1080 active, 1132 total) + VBLANK_EDP (0x0006f010): 0x046b0437 (1080 start, 1132 end) + VSYNC_EDP (0x0006f014): 0x0445043d (1086 start, 1094 end) + VSYNCSHIFT_EDP (0x0006f028): 0x00000000 + PIPEEDP_DATA_M1 (0x0006f030): 0x7e6cafac (TU 64, val 0x6cafac 7122860) + PIPEEDP_DATA_N1 (0x0006f034): 0x00800000 (val 0x800000 8388608) + PIPEEDP_LINK_M1 (0x0006f040): 0x00048751 (val 0x48751 296785) + PIPEEDP_LINK_N1 (0x0006f044): 0x00080000 (val 0x80000 524288) + PFA_CTL_1 (0x00068080): 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) + PFA_WIN_POS (0x00068070): 0x00000000 (0, 0) + PFA_WIN_SIZE (0x00068074): 0x00000000 (0, 0) + PFB_CTL_1 (0x00068880): 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) + PFB_WIN_POS (0x00068870): 0x00000000 (0, 0) + PFB_WIN_SIZE (0x00068874): 0x00000000 (0, 0) + PFC_CTL_1 (0x00069080): 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) + PFC_WIN_POS (0x00069070): 0x00000000 (0, 0) + PFC_WIN_SIZE (0x00069074): 0x00000000 (0, 0) + TRANS_HTOTAL_A (0x000e0000): 0xffffffff (65536 active, 65536 total) + TRANS_HBLANK_A (0x000e0004): 0xffffffff (65536 start, 65536 end) + TRANS_HSYNC_A (0x000e0008): 0xffffffff (65536 start, 65536 end) + TRANS_VTOTAL_A (0x000e000c): 0xffffffff (65536 active, 65536 total) + TRANS_VBLANK_A (0x000e0010): 0xffffffff (65536 start, 65536 end) + TRANS_VSYNC_A (0x000e0014): 0xffffffff (65536 start, 65536 end) + TRANS_VSYNCSHIFT_A (0x000e0028): 0xffffffff + TRANSACONF (0x000f0008): 0xffffffff (enable, active, rsvd) + FDI_RXA_MISC (0x000f0010): 0xffffffff (FDI Delay 8191) + FDI_RXA_TUSIZE1 (0x000f0030): 0xffffffff + FDI_RXA_IIR (0x000f0014): 0xffffffff + FDI_RXA_IMR (0x000f0018): 0xffffffff + BLC_PWM_CPU_CTL2 (0x00048250): 0x00000000 (enable 0, pipe A, blinking 0, granularity 128) + BLC_PWM_CPU_CTL (0x00048254): 0x00000000 (cycle 0, freq 0) + BLC_PWM2_CPU_CTL2 (0x00048350): 0x00000000 (enable 0, pipe A, blinking 0, granularity 128) + BLC_PWM2_CPU_CTL (0x00048354): 0x00000000 (cycle 0, freq 0) + BLC_MISC_CTL (0x00048360): 0x00000000 (PWM1-PCH PWM2-CPU) + BLC_PWM_PCH_CTL1 (0x000c8250): 0x80000000 (enable 1, override 0, inverted polarity 0) + BLC_PWM_PCH_CTL2 (0x000c8254): 0x00005eb2 (freq 0, cycle 24242) + UTIL_PIN_CTL (0x00048400): 0x00000000 (enable 0, transcoder A, mode data, data 0 inverted polarity 0) + PCH_PP_STATUS (0x000c7200): 0x80000008 (on, not ready, sequencing idle) + PCH_PP_CONTROL (0x000c7204): 0x00000067 (blacklight enabled, power down on reset, panel on) + PCH_PP_ON_DELAYS (0x000c7208): 0x07d00001 + PCH_PP_OFF_DELAYS (0x000c720c): 0x01f40001 + PCH_PP_DIVISOR (0x000c7210): 0xffffffff + PIXCLK_GATE (0x000c6020): 0xffffffff + SDEISR (0x000c4000): 0x01000000 (port d:0, port c:0, port b:0, crt:0) + RC6_RESIDENCY_TIME (0x00138108): 0x1ac55c0f diff --git a/shutdown.c b/shutdown.c index af63b26..0d5173e 100755 --- a/shutdown.c +++ b/shutdown.c @@ -1,12 +1,17 @@ #include "../edk2/MdePkg/Include/Uefi.h" EFI_STATUS -EFIAPI + EFIAPI efi_main ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) + IN +EFI_HANDLE ImageHandle, + IN +EFI_SYSTEM_TABLE *SystemTable +) { - SystemTable->RuntimeServices->ResetSystem(EfiResetShutdown,0,0,NULL); - return EFI_SUCCESS; +SystemTable->RuntimeServices-> +ResetSystem(EfiResetShutdown, +0,0,NULL); +return +EFI_SUCCESS; } diff --git a/target.txt b/target.txt new file mode 100644 index 0000000..bbc6228 --- /dev/null +++ b/target.txt @@ -0,0 +1,70 @@ +# +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +# ALL Paths are Relative to WORKSPACE + +# Separate multiple LIST entries with a SINGLE SPACE character, do not use comma characters. +# Un-set an option by either commenting out the line, or not setting a value. + +# +# PROPERTY Type Use Description +# ---------------- -------- -------- ----------------------------------------------------------- +# ACTIVE_PLATFORM Filename Recommended Specify the WORKSPACE relative Path and Filename +# of the platform description file that will be used for the +# build. This line is required if and only if the current +# working directory does not contain one or more description +# files. +ACTIVE_PLATFORM = EmulatorPkg/EmulatorPkg.dsc + +# TARGET List Optional Zero or more of the following: DEBUG, RELEASE, NOOPT +# UserDefined; separated by a space character. +# If the line is missing or no value is specified, all +# valid targets specified in the platform description file +# will attempt to be built. The following line will build +# DEBUG platform target. +TARGET = DEBUG + +# TARGET_ARCH List Optional What kind of architecture is the binary being target for. +# One, or more, of the following, IA32, IPF, X64, EBC, ARM +# or AArch64. +# Multiple values can be specified on a single line, using +# space characters to separate the values. These are used +# during the parsing of a platform description file, +# restricting the build output target(s.) +# The Build Target ARCH is determined by (precedence high to low): +# Command-line: -a ARCH option +# target.txt: TARGET_ARCH values +# DSC file: [Defines] SUPPORTED_ARCHITECTURES tag +# If not specified, then all valid architectures specified +# in the platform file, for which tools are available, will be +# built. +TARGET_ARCH = X64 + +# TOOL_DEFINITION_FILE Filename Optional Specify the name of the filename to use for specifying +# the tools to use for the build. If not specified, +# WORKSPACE/Conf/tools_def.txt will be used for the build. +TOOL_CHAIN_CONF = Conf/tools_def.txt + +# TAGNAME List Optional Specify the name(s) of the tools_def.txt TagName to use. +# If not specified, all applicable TagName tools will be +# used for the build. The list uses space character separation. +TOOL_CHAIN_TAG = GCC5 + +# MAX_CONCURRENT_THREAD_NUMBER NUMBER Optional The number of concurrent threads. If not specified or set +# to zero, tool automatically detect number of processor +# threads. Recommend to set this value to one less than the +# number of your computer cores or CPUs. When value set to 1, +# means disable multi-thread build, value set to more than 1, +# means user specify the thread number to build. Not specify +# the default value in this file. +# MAX_CONCURRENT_THREAD_NUMBER = 1 + + +# BUILD_RULE_CONF Filename Optional Specify the file name to use for the build rules that are followed +# when generating Makefiles. If not specified, the file: +# WORKSPACE/Conf/build_rule.txt will be used +BUILD_RULE_CONF = Conf/build_rule.txt + diff --git a/test b/test deleted file mode 100755 index 7c65320..0000000 --- a/test +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/bash -cd ../edk2 -. ../edk2/edksetup.sh -#build -b DEBUG -p i915ovmfPkg/i915ovmf.dsc || exit -build -b RELEASE -p i915ovmfPkg/i915ovmf.dsc || exit -cd ../i915_simple -cp ../edk2/Build/i915ovmf/RELEASE_GCC5/X64/i915ovmf.rom ./ || exit -#cp ../edk2/Build/i915ovmf/DEBUG_GCC5/X64/i915ovmf.rom ./ || exit - -if [ -e /sys/bus/pci/devices/0000:00:02.0/2aee154e-7d0d-11e8-88b8-6f45320c7162 ] -then - true -else - modprobe kvmgt || exit - #sudo dd if=/sys/class/drm/card0-HDMI-A-1/edid of=/sys/class/drm/card0/gvt_edid bs=128 count=1 - echo 2aee154e-7d0d-11e8-88b8-6f45320c7162 > /sys/bus/pci/devices/0000:00:02.0/mdev_supported_types/i915-GVTg_V5_4/create || exit -fi - -# Create an UEFI disk that immediately shuts down the VM when booted -mkdir -p tmpfat -mount disk tmpfat -mkdir -p tmpfat/EFI/BOOT -cp shutdown.efi tmpfat/EFI/BOOT/BOOTX64.EFI -umount tmpfat -rmdir tmpfat - -qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -serial stdio -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios /home/hqm/gpdvm/bin/ovmf.fd -display gtk,gl=on,grab-on-hover=on -full-screen -vga none -device vfio-pci,sysfsdev=/sys/bus/pci/devices/0000:00:02.0/2aee154e-7d0d-11e8-88b8-6f45320c7162,addr=02.0,display=on,x-igd-opregion=on,romfile=`pwd`/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk diff --git a/test-gvt-d.sh b/test-gvt-d.sh new file mode 100755 index 0000000..f683413 --- /dev/null +++ b/test-gvt-d.sh @@ -0,0 +1,33 @@ +#!/bin/bash +source ./config + +export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms + +cd $WORKSPACE +. edk2/edksetup.sh +if [ ! -f "$WORKSPACE/edk2/BaseTools/Source/C/bin" ]; then + make -C edk2/BaseTools +fi +build -v -b DEBUG -p i915ovmfPkg/i915ovmf.dsc || exit +#build -b RELEASE -p i915ovmfPkg/i915ovmf.dsc || exit +mkdir -p i915_simple +cd ./i915_simple +#cp ../Build/i915ovmf/RELEASE_GCC5/X64/i915ovmf.rom ./ || exit +cp ../Build/i915ovmf/DEBUG_GCC5/X64/i915ovmf.rom ./ || exit + +# Create an UEFI disk that immediately shuts down the VM when booted +mkdir -p tmpfat +mount disk tmpfat +mkdir -p tmpfat/EFI/BOOT +umount tmpfat +rmdir tmpfat +systemctl stop display-manager.service + echo $PCIID > /sys/bus/pci/drivers/vfio-pci/new_id + echo $PCILOC> /sys/bus/pci/devices/$PCILOC/driver/unbind + echo $PCILOC > /sys/bus/pci/drivers/vfio-pci/bind + echo 0 > /sys/class/vtconsole/vtcon0/bind + echo 0 > /sys/class/vtconsole/vtcon1/bind + echo efi-framebuffer.0 > /sys/bus/platform/drivers/efi-framebuffer/unbind +#qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -nographic -vga none -serial stdio -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios $WORKSPACE/OVMF_CODE.fd -device vfio-pci,host=$PCILOC,romfile=`pwd`/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk -usb +timeout --foreground -k 1 15 qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -nographic -vga none -chardev stdio,id=char0,logfile=serial.log,signal=off \ + -serial chardev:char0 -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios $WORKSPACE/OVMF_CODE.fd -device vfio-pci,host=$PCILOC,romfile=`pwd`/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk -usb diff --git a/test-gvt-g.sh b/test-gvt-g.sh new file mode 100644 index 0000000..9bc0239 --- /dev/null +++ b/test-gvt-g.sh @@ -0,0 +1,35 @@ +#!/bin/bash +source ./config + +export GVTMODE=i915-GVTg_V5_4 +export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms + +cd $WORKSPACE +. edk2/edksetup.sh +if [ ! -f "$WORKSPACE/edk2/BaseTools/Source/C/bin" ]; then + make -C edk2/BaseTools +fi +build -v -b DEBUG -p i915ovmfPkg/i915ovmf.dsc || exit +#build -b RELEASE -p i915ovmfPkg/i915ovmf.dsc || exit +mkdir i915_simple +cd ./i915_simple +#cp ../Build/i915ovmf/RELEASE_GCC5/X64/i915ovmf.rom ./ || exit +cp ../Build/i915ovmf/DEBUG_GCC5/X64/i915ovmf.rom ./ || exit + +if [ -e /sys/bus/pci/devices/$PCILOC/2aee154e-7d0d-11e8-88b8-6f45320c7162 ] +then + true +else + modprobe kvmgt || exit + #sudo dd if=/sys/class/drm/card0-HDMI-A-1/edid of=/sys/class/drm/card0/gvt_edid bs=128 count=1 + echo 2aee154e-7d0d-11e8-88b8-6f45320c7162 > /sys/bus/pci/devices/$PCILOC/mdev_supported_types/$GVTMODE/create || exit +fi + +# Create an UEFI disk that immediately shuts down the VM when booted +mkdir -p tmpfat +mount disk tmpfat +mkdir -p tmpfat/EFI/BOOT +umount tmpfat +rmdir tmpfat + +qemu-system-x86_64 -k en-us -name uefitest,debug-threads=on -serial stdio -m 2048 -M pc -cpu host -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -machine kernel_irqchip=on -nodefaults -rtc base=localtime,driftfix=slew -no-hpet -global kvm-pit.lost_tick_policy=discard -enable-kvm -bios $WORKSPACE/OVMF_CODE.fd -display gtk,gl=on,grab-on-hover=on -full-screen -vga none -device vfio-pci,sysfsdev=/sys/bus/pci/devices/$PCILOC/2aee154e-7d0d-11e8-88b8-6f45320c7162,addr=02.0,display=on,x-igd-opregion=on,romfile=`pwd`/i915ovmf.rom -device qemu-xhci,p2=8,p3=8 -device usb-kbd -device usb-tablet -drive format=raw,file=disk diff --git a/unbind.sh b/unbind.sh new file mode 100755 index 0000000..4a1d445 --- /dev/null +++ b/unbind.sh @@ -0,0 +1,9 @@ +#!/bin/bash +source ./config +systemctl stop display-manager.service + echo $PCIID > /sys/bus/pci/drivers/vfio-pci/new_id + echo $PCILOC> /sys/bus/pci/devices/$PCILOC/driver/unbind + echo $PCILOC > /sys/bus/pci/drivers/vfio-pci/bind + echo 0 > /sys/class/vtconsole/vtcon0/bind + echo 0 > /sys/class/vtconsole/vtcon1/bind + echo efi-framebuffer.0 > /sys/bus/platform/drivers/efi-framebuffer/unbind diff --git a/vm.xml b/vm.xml new file mode 100644 index 0000000..6cc9689 --- /dev/null +++ b/vm.xml @@ -0,0 +1,107 @@ + + + vm1 + 9e036e99-b113-442e-9c9e-9da9a5e77eee + 1048576 + 1048576 + 1 + + hvm + /usr/share/edk2/ovmf/OVMF_CODE.fd + /var/lib/libvirt/qemu/nvram/vm1_VARS.fd + + + + + + + + + + + + + + destroy + restart + destroy + + + + + + + +
+ + + + + /usr/bin/qemu-system-x86_64 + + + + +
+ + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + +
+ + + + + + + + + + + +
+ + +
+ + + + + + + + +
+ +