diff --git a/syn/gsi_pexp/sdr/pexp_control_sdr.qpf b/syn/gsi_pexp/sdr/pexp_control_sdr.qpf new file mode 100644 index 000000000..ce2b8caec --- /dev/null +++ b/syn/gsi_pexp/sdr/pexp_control_sdr.qpf @@ -0,0 +1 @@ +PROJECT_REVISION = "pexp_control_sdr" diff --git a/syn/gsi_pexp/sdr/pexp_control_sdr.qsf b/syn/gsi_pexp/sdr/pexp_control_sdr.qsf new file mode 100644 index 000000000..f51272324 --- /dev/null +++ b/syn/gsi_pexp/sdr/pexp_control_sdr.qsf @@ -0,0 +1,1136 @@ +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF +set_global_assignment -name AHDL_FILE ../../../modules/modulbus/i2c.tdf +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name DEVICE 5agxma3d4f27i3 +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_board_design_boundary_scan +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name ENABLE_BOOT_SEL_PIN ON +set_global_assignment -name ENABLE_CONFIGURATION_PINS ON +set_global_assignment -name ENABLE_NCE_PIN ON +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 +set_global_assignment -name FAMILY "Arria V" +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION AUTOMATICALLY +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name INI_VARS "fitter_optimize_bias_for_pci = on" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" +set_global_assignment -name LL_AUTO_SIZE OFF -section_id flash +set_global_assignment -name LL_AUTO_SIZE OFF -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_AUTO_SIZE OFF -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_AUTO_SIZE OFF -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_AUTO_SIZE OFF -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_AUTO_SIZE OFF -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_CORE_ONLY OFF -section_id flash +set_global_assignment -name LL_CORE_ONLY OFF -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_CORE_ONLY OFF -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_CORE_ONLY OFF -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_CORE_ONLY OFF -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_CORE_ONLY OFF -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_ENABLED ON -section_id flash +set_global_assignment -name LL_ENABLED ON -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_ENABLED ON -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_ENABLED ON -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_ENABLED ON -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_ENABLED ON -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_HEIGHT 1 -section_id flash +set_global_assignment -name LL_HEIGHT 1 -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_HEIGHT 1 -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_HEIGHT 1 -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_HEIGHT 1 -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_HEIGHT 1 -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id flash +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_ORIGIN X28_Y1 -section_id flash +set_global_assignment -name LL_ORIGIN X36_Y88 -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_ORIGIN X37_Y87 -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_ORIGIN X37_Y88 -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_ORIGIN X39_Y88 -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_ORIGIN X41_Y87 -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_PR_REGION OFF -section_id flash +set_global_assignment -name LL_PR_REGION OFF -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_PR_REGION OFF -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_PR_REGION OFF -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_PR_REGION OFF -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_PR_REGION OFF -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_RESERVED OFF -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_RESERVED OFF -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_RESERVED OFF -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_RESERVED OFF -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_RESERVED OFF -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_RESERVED ON -section_id flash +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id flash +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id flash +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_STATE LOCKED -section_id flash +set_global_assignment -name LL_STATE LOCKED -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_STATE LOCKED -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_STATE LOCKED -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_STATE LOCKED -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_STATE LOCKED -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name LL_WIDTH 1 -section_id flash +set_global_assignment -name LL_WIDTH 2 -section_id ref_pll_out0_125mhz +set_global_assignment -name LL_WIDTH 2 -section_id ref_pll_out1_200mhz +set_global_assignment -name LL_WIDTH 2 -section_id ref_pll_out2_25mhz +set_global_assignment -name LL_WIDTH 2 -section_id ref_pll_out3_1000mhz +set_global_assignment -name LL_WIDTH 2 -section_id ref_pll_out4_125mhz_p1_8 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "NORMAL COMPILATION" +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1 +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10 +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:pexp_control_sdr.tcl" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:00:25 FEBRUARY 13, 2012" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria5/dual_region.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria5/global_region.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria5_networks.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria5/single_region.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/arria5_pcie_hip.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/arria5_pcie.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/arria5_pcie_reconf.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/arria5_phy16.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/arria5_phy8.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/arria5_phy_reconf.qip" +set_global_assignment -name QIP_FILE ../../../modules/nau8811/src/hdl/altera_pll/audio_pll_ref.qip +set_global_assignment -name QIP_FILE ../../../modules/pll/arria5/arria5_pll.qip +set_global_assignment -name QIP_FILE ../../../modules/pll/arria5/dmtd_pll5.qip +set_global_assignment -name QIP_FILE ../../../modules/pll/arria5/ref_pll5.qip +set_global_assignment -name QIP_FILE ../../../modules/pll/arria5/sys_pll5.qip +set_global_assignment -name QSYS_FILE ../../../modules/temp_sens/temp_sens.qsys +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES ON +set_global_assignment -name SDC_FILE ../../../top/common/arria5.sdc +set_global_assignment -name SEED 191 +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL" +set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL ON +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON +set_global_assignment -name TOP_LEVEL_ENTITY pexp_control_sdr +set_global_assignment -name TRI_STATE_SPI_PINS ON +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_slave.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_gdoqleq.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_svbigkq.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/submodules/asmi5_asmi_parallel_0.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/submodules/asmi_arriaII_asmi_parallel_0.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/temp_sens/synthesis/submodules/temp_sens_temp_sense_0.v -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Access_Decode.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Am_Match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_bus.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CRAM.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_CSR_Space.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CSR_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Funct_Match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Init.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_IRQ_Controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_SharedComps.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_swapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_master_eb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_reset.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_remapper/xwb_remapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/ad7606.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_modul_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/aux_functions_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Debounce.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/div_n.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/IO_4x8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/led_n.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/lemo_io.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_125_to_12p5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_20_to_12p5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_16_4.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_256_8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_64_6.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/slave_clk_switch.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/tmr_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Zeitbasis.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/beam_dump/beam_dump_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/beam_dump/beam_dump.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/BuTis_T0_generator.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/crc8_data8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampDecoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampEncoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/wr_serialtimestamp_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/cfi_flash_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/xwb_cfi_wrapper.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Bus_io.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Debounce_Skal.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Independent_Clk.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/K12_K23_Logik_Leds.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kanal.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kicker_Leds.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cpri_phy_reconf/cpri_phy_reconf_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cpri_phy_reconf/cpri_phy_reconf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/crc5x16.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq_chan_reg_logic.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/Zeitbasis_daq.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ddr3/ddr3_wrapper.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/hw_interlock.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/quench_detection.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/spill_abort.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/flash_loader/flash_loader_v01.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32_cluster.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/time_clk_cross.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_datapath.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_statistics.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/ring_buffer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen_regs.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/xwb_serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pathfinder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_top.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_writer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/xwb_heap.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/i2c_wrapper/src/hdl/wb_i2c_wrapper_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/led_blink.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/i8042_kbc.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_peripheral.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/postcode.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_ibuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_obuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_rx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_tx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria10_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5/arria5_lvds_ibuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5/arria5_lvds_obuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5/arria5_lvds_rx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5/arria5_lvds_tx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/eca_lvds_channel.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/hw6408_vhdl.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_bipol_dec.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_dec_edge_timed.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_Enc_Vhdl.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_en_decoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_hw_or_soft_ip.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/PLL_SIO.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/PU_Reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/SysClock.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Epcs_spi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/f_divider.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/global_reg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/I2C_Cntrl.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/K_EPCS_IF.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/led.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Loader_MB.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modul2spi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_loader.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_v5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Rd_mb_ld.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/rdram.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_iodir.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/generic_iis_master_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/generic_iis_master.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/wb_nau8811_audio_driver_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/wb_nau8811_audio_driver.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/char_render.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/display_console.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/Display_RAM_Ini_v01.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_display_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/spi_master.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/wb_console.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_butis.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_phase.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/pll_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/pwm.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/row_array.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/row.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/arbiter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min3.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min9_64.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/queue_unit.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/psram/psram_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/psram/psram.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/synth/asmi10.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/asmi5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/asmi_arriaII.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_asmi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_remote_update.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/reverse_lpb/reverse_lpb.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/housekeeping.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_to_wb.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_irq_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/temp_sens/hdl/temp_sensor_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/temp_sens/hdl/wb_temp_sense_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/temp_sens/hdl/wb_temp_sense.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/temp_sens/synthesis/temp_sens.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_loop.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_rcfg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/trans_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/trans_pll/trans_pll.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_clock_div.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_counter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_edge_detect.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_fifo.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_filter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_sync.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_mv_filter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_16750.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_baudgen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_interrupt.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_receiver.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_transmitter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/altera_remote_update_181/synth/arria10_reset_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/synth/arria10_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria5_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/event_processing.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/mil_pll.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../top/gsi_pexp/sdr/pexp_control_sdr.vhd -library work +set_global_assignment -name VHDL_FILE ../../../top/gsi_pexp/sdr/ramsize_pkg.vhd -library work +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ctl +set_instance_assignment -name FAST_INPUT_REGISTER ON -to fd +set_instance_assignment -name FAST_INPUT_REGISTER ON -to pa +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to fd +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to fd +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pa +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to slrd +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to slwr +set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "monster:main|altera_reset:reset|nresets[1][0]" +set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "monster:main|altera_reset:reset|nresets[3][0]" +set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "monster:main|xwr_core:U_WR_CORE|wr_core:WRPC|wrc_periph:PERIPH|rst_wrc_n_o~0" +set_instance_assignment -name GLOBAL_SIGNAL PERIPHERY_CLOCK -to "monster:main|eb_master_slave_wrapper:eb|eb_master_top:\\MS1:U_ebm|s_rst_n" +set_instance_assignment -name GLOBAL_SIGNAL REGIONAL_CLOCK -to "monster:main|ez_usb:\\usb_y:usb|nreset" +set_instance_assignment -name GLOBAL_SIGNAL REGIONAL_CLOCK -to "monster:main|global_region:phase_clk|global_region_altclkctrl_bdh:global_region_altclkctrl_bdh_component|wire_sd1_outclk" +set_instance_assignment -name GLOBAL_SIGNAL REGIONAL_CLOCK -to "monster:main|xwr_core:U_WR_CORE|wr_core:WRPC|wrc_periph:PERIPH|rst_net_n_o" +set_instance_assignment -name GLOBAL_SIGNAL REGIONAL_CLOCK -to pcie_refclk_i* +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to clk_125m_local_i +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to clk_125m_pllref_i +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to clk_lvtio_i +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_n_i[1] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_n_i[2] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_n_i[3] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_n_i[4] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_n_i[5] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_p_i[1] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_p_i[2] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_p_i[3] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_p_i[4] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to lvtio_in_p_i[5] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[0] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[1] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[2] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[0] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[1] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[2] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[3] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to sfp_rxp_i +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to sfp_txp_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to con[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to con[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to con[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to con[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to con[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ctl[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ctl[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ctl[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_ai_i[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_ai_i[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_di_o[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_di_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_di_o[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_di_o[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_di_o[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_di_o[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_di_o[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_do_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_rst_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dis_wr_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fd[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fd[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fd[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fd[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fd[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fd[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fd[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fd[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_res_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpw[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hpwck +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hswf_i[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hswf_i[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hswf_i[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hswf_i[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ifclk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_status_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_status_o[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_status_o[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_status_o[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_status_o[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_status_o[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_user_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_user_o[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_user_o[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_user_o[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_user_o[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_user_o[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_user_o[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_user_o[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nres_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pa[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pa[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pa[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pa[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pa[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pa[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pa[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pa[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rom_data_io +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to slrd +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to slwr +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uclk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ures +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to wakeup +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to wr_dac_din_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to wr_dac_sclk_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to wr_ndac_cs_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to wr_ndac_cs_o[2] +set_instance_assignment -name IO_STANDARD LVDS -to clk_125m_local_i +set_instance_assignment -name IO_STANDARD LVDS -to clk_125m_pllref_i +set_instance_assignment -name IO_STANDARD LVDS -to clk_lvtio_i +set_instance_assignment -name IO_STANDARD LVDS -to clk_sfp_ref_i +set_instance_assignment -name IO_STANDARD LVDS -to "clk_sfp_ref_i(n)" +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_n_i[1] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_n_i[2] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_n_i[3] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_n_i[4] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_n_i[5] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_p_i[1] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_p_i[2] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_p_i[3] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_p_i[4] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_in_p_i[5] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_n_o[1] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_n_o[2] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_n_o[3] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_n_o[4] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_n_o[5] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_p_o[1] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_p_o[2] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_p_o[3] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_p_o[4] +set_instance_assignment -name IO_STANDARD LVDS -to lvtio_out_p_o[5] +set_instance_assignment -name IO_STANDARD LVDS -to pcie_refclk_i +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_data_i[0]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_data_i[1]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_data_i[2]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_data_i[3]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_ncs" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_oe[0]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_oe[1]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_oe[2]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_oe[3]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_shift_o[28]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_shift_o[29]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_shift_o[30]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF flash -to "monster:main|flash_top:\\flash_a5:flash|wb_spi_flash:wb|r_shift_o[31]" -section_id flash +set_instance_assignment -name LL_MEMBER_OF ref_pll_out0_125mhz -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0|combout" -section_id ref_pll_out0_125mhz +set_instance_assignment -name LL_MEMBER_OF ref_pll_out1_200mhz -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1|combout" -section_id ref_pll_out1_200mhz +set_instance_assignment -name LL_MEMBER_OF ref_pll_out2_25mhz -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2|combout" -section_id ref_pll_out2_25mhz +set_instance_assignment -name LL_MEMBER_OF ref_pll_out3_1000mhz -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3|combout" -section_id ref_pll_out3_1000mhz +set_instance_assignment -name LL_MEMBER_OF ref_pll_out4_125mhz_p1_8 -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4|combout" -section_id ref_pll_out4_125mhz_p1_8 +set_instance_assignment -name MAX_FANOUT 64 -to "monster:main|eca_ac_wbm:c1" +set_instance_assignment -name MAX_FANOUT 64 -to "monster:main|eca_queue:c0" +set_instance_assignment -name MAX_FANOUT 64 -to "monster:main|eca_queue:c2" +set_instance_assignment -name MAX_FANOUT 64 -to "monster:main|eca_tlu:ecatlu" +set_instance_assignment -name MAX_FANOUT 64 -to "monster:main|eca_wb_event:ecawb" +set_instance_assignment -name MAX_FANOUT 64 -to "monster:main|ftm_lm32_cluster:lm32*" +set_instance_assignment -name MAX_FANOUT 64 -to "monster:main|wr_eca:eca" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_location_assignment FRACTIONALPLL_X0_Y18_N0 -to "monster:main|dmtd_pll5:\\dmtd_a5:dmtd_inst|dmtd_pll5_0002:dmtd_pll5_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL" +set_location_assignment FRACTIONALPLL_X0_Y60_N0 -to "monster:main|sys_pll5:\\sys_a5:sys_inst|sys_pll5_0002:sys_pll5_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL" +set_location_assignment FRACTIONALPLL_X43_Y65_N0 -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|altera_arriav_pll_base:fpll_0|cntnen" +set_location_assignment PIN_A11 -to sfp_mod1_io +set_location_assignment PIN_A12 -to sfp_mod0_i +set_location_assignment PIN_A5 -to lvtio_in_p_i[1] +set_location_assignment PIN_A6 -to lvtio_in_n_i[1] +set_location_assignment PIN_A8 -to lvtio_out_p_o[1] +set_location_assignment PIN_A9 -to lvtio_out_n_o[1] +set_location_assignment PIN_AA1 -to dis_di_o[5] +set_location_assignment PIN_AA20 -to led_status_o[6] +set_location_assignment PIN_AA21 -to led_user_o[7] +set_location_assignment PIN_AA24 -to pcie_tx_o[0] +set_location_assignment PIN_AA2 -to rom_data_io +set_location_assignment PIN_AA3 -to dis_rst_o +set_location_assignment PIN_AA4 -to dis_di_o[0] +set_location_assignment PIN_AA5 -to dis_di_o[3] +set_location_assignment PIN_AA6 -to dis_di_o[4] +set_location_assignment PIN_AA7 -to pa[0] +set_location_assignment PIN_AA8 -to wakeup +set_location_assignment PIN_AA9 -to ifclk +set_location_assignment PIN_AB19 -to led_status_o[4] +set_location_assignment PIN_AB1 -to dis_di_o[6] +set_location_assignment PIN_AB21 -to led_user_o[6] +set_location_assignment PIN_AB26 -to pcie_rx_i[0] +set_location_assignment PIN_AB2 -to pa[4] +set_location_assignment PIN_AB3 -to pa[6] +set_location_assignment PIN_AB4 -to ures +set_location_assignment PIN_AB6 -to pa[5] +set_location_assignment PIN_AC19 -to led_status_o[3] +set_location_assignment PIN_AC1 -to pa[2] +set_location_assignment PIN_AC20 -to led_status_o[5] +set_location_assignment PIN_AC21 -to led_user_o[2] +set_location_assignment PIN_AC22 -to led_user_o[1] +set_location_assignment PIN_AC3 -to pa[7] +set_location_assignment PIN_AC5 -to fd[6] +set_location_assignment PIN_AC6 -to ctl[1] +set_location_assignment PIN_AC7 -to nres_i +set_location_assignment PIN_AC8 -to wr_dac_sclk_o +set_location_assignment PIN_AD23 -to led_user_o[3] +set_location_assignment PIN_AD3 -to ctl[0] +set_location_assignment PIN_AD4 -to pa[1] +set_location_assignment PIN_AD5 -to fd[7] +set_location_assignment PIN_AD6 -to ctl[2] +set_location_assignment PIN_AD7 -to pa[3] +set_location_assignment PIN_AD8 -to wr_dac_din_o +set_location_assignment PIN_AE19 -to led_status_o[1] +set_location_assignment PIN_AE23 -to led_user_o[4] +set_location_assignment PIN_AE3 -to fd[5] +set_location_assignment PIN_AE4 -to fd[3] +set_location_assignment PIN_AE6 -to fd[1] +set_location_assignment PIN_AF18 -to pbs_f_i +set_location_assignment PIN_AF19 -to led_status_o[2] +set_location_assignment PIN_AF21 -to clk_20m_vcxo_i +set_location_assignment PIN_AF23 -to led_user_o[5] +set_location_assignment PIN_AF3 -to fd[4] +set_location_assignment PIN_AF5 -to fd[2] +set_location_assignment PIN_AF6 -to fd[0] +set_location_assignment PIN_AF7 -to wr_ndac_cs_o[2] +set_location_assignment PIN_AF8 -to wr_ndac_cs_o[1] +set_location_assignment PIN_B10 -to pe_snclk +set_location_assignment PIN_B12 -to sfp_los_i +set_location_assignment PIN_B16 -to clk_lvtio_i +set_location_assignment PIN_B1 -to hpw[7] +set_location_assignment PIN_B6 -to lvtio_in_p_i[2] +set_location_assignment PIN_B7 -to lvtio_out_p_o[2] +set_location_assignment PIN_C10 -to pe_smdat +set_location_assignment PIN_C12 -to sfp_tx_fault_i +set_location_assignment PIN_C17 -to "clk_lvtio_i(n)" +set_location_assignment PIN_C1 -to con[1] +set_location_assignment PIN_C22 -to "clk_125m_local_i(n)" +set_location_assignment PIN_C23 -to clk_125m_local_i +set_location_assignment PIN_C5 -to lvtio_out_p_o[3] +set_location_assignment PIN_C6 -to lvtio_in_n_i[2] +set_location_assignment PIN_C7 -to lvtio_out_n_o[2] +set_location_assignment PIN_D1 -to hpw[5] +set_location_assignment PIN_D2 -to hpw[6] +set_location_assignment PIN_D5 -to lvtio_out_n_o[3] +set_location_assignment PIN_D6 -to lvtio_in_p_i[3] +set_location_assignment PIN_E1 -to con[2] +set_location_assignment PIN_E3 -to hpw[15] +set_location_assignment PIN_E6 -to lvtio_in_n_i[3] +set_location_assignment PIN_E7 -to lvtio_in_p_i[4] +set_location_assignment PIN_F1 -to hpw[3] +set_location_assignment PIN_F2 -to hpw[4] +set_location_assignment PIN_F3 -to hpw[14] +set_location_assignment PIN_F6 -to nPCI_RESET +set_location_assignment PIN_F7 -to lvtio_in_n_i[4] +set_location_assignment PIN_F8 -to lvtio_out_p_o[4] +set_location_assignment PIN_G15 -to clk_125m_pllref_i +set_location_assignment PIN_G2 -to hpw[12] +set_location_assignment PIN_G3 -to hpw[13] +set_location_assignment PIN_G8 -to lvtio_out_n_o[4] +set_location_assignment PIN_G9 -to lvtio_in_p_i[5] +set_location_assignment PIN_H12 -to sfp_tx_dis_o +set_location_assignment PIN_H15 -to "clk_125m_pllref_i(n)" +set_location_assignment PIN_H1 -to hswf_i[2] +set_location_assignment PIN_H3 -to hpw[2] +set_location_assignment PIN_H9 -to lvtio_in_n_i[5] +set_location_assignment PIN_J12 -to sfp_mod2_io +set_location_assignment PIN_J1 -to hswf_i[1] +set_location_assignment PIN_J23 -to "sfp_txp_o(n)" +set_location_assignment PIN_J24 -to sfp_txp_o +set_location_assignment PIN_J2 -to hpw[0] +set_location_assignment PIN_J3 -to hpw[11] +set_location_assignment PIN_J4 -to hpw[1] +set_location_assignment PIN_J5 -to con[3] +set_location_assignment PIN_J8 -to lvtio_out_n_o[5] +set_location_assignment PIN_J9 -to lvtio_out_p_o[5] +set_location_assignment PIN_K12 -to pe_waken +set_location_assignment PIN_K25 -to "sfp_rxp_i(n)" +set_location_assignment PIN_K26 -to sfp_rxp_i +set_location_assignment PIN_K3 -to hpwck +set_location_assignment PIN_K4 -to hpw[10] +set_location_assignment PIN_K6 -to hpw[8] +set_location_assignment PIN_K7 -to con[4] +set_location_assignment PIN_L1 -to hswf_i[3] +set_location_assignment PIN_L3 -to hpw[9] +set_location_assignment PIN_L4 -to con[5] +set_location_assignment PIN_M2 -to hswf_i[4] +set_location_assignment PIN_N18 -to clk_sfp_ref_i +set_location_assignment PIN_N19 -to "clk_sfp_ref_i(n)" +set_location_assignment PIN_N5 -to lvtio_oe_n_o[1] +set_location_assignment PIN_N6 -to lvtio_led_act_o[5] +set_location_assignment PIN_P1 -to lvtio_term_en_o[1] +set_location_assignment PIN_P3 -to lvtio_led_act_o[1] +set_location_assignment PIN_P4 -to lvtio_led_dir_o[5] +set_location_assignment PIN_P6 -to lvt_in_clk_en_n_o +set_location_assignment PIN_R24 -to pcie_tx_o[3] +set_location_assignment PIN_R2 -to lvtio_led_dir_o[1] +set_location_assignment PIN_R3 -to lvtio_oe_n_o[2] +set_location_assignment PIN_R6 -to lvtio_term_en_o[2] +set_location_assignment PIN_T1 -to lvtio_led_act_o[2] +set_location_assignment PIN_T26 -to pcie_rx_i[3] +set_location_assignment PIN_T2 -to lvtio_led_dir_o[2] +set_location_assignment PIN_T3 -to lvtio_oe_n_o[3] +set_location_assignment PIN_T6 -to lvtio_term_en_o[3] +set_location_assignment PIN_T7 -to lvtio_led_act_o[3] +set_location_assignment PIN_U18 -to pcie_refclk_i +set_location_assignment PIN_U1 -to lvtio_led_dir_o[3] +set_location_assignment PIN_U24 -to pcie_tx_o[2] +set_location_assignment PIN_U5 -to lvtio_oe_n_o[4] +set_location_assignment PIN_V1 -to lvtio_term_en_o[4] +set_location_assignment PIN_V26 -to pcie_rx_i[2] +set_location_assignment PIN_V4 -to lvtio_led_act_o[4] +set_location_assignment PIN_V5 -to lvtio_led_dir_o[4] +set_location_assignment PIN_V9 -to uclk +set_location_assignment PIN_W1 -to lvtio_oe_n_o[5] +set_location_assignment PIN_W24 -to pcie_tx_o[1] +set_location_assignment PIN_W2 -to lvtio_term_en_o[5] +set_location_assignment PIN_W3 -to dis_ai_i[1] +set_location_assignment PIN_W4 -to dis_ai_i[0] +set_location_assignment PIN_W6 -to dis_di_o[1] +set_location_assignment PIN_W7 -to dis_wr_o +set_location_assignment PIN_W9 -to slrd +set_location_assignment PIN_Y1 -to fpga_res_i +set_location_assignment PIN_Y21 -to led_user_o[8] +set_location_assignment PIN_Y26 -to pcie_rx_i[1] +set_location_assignment PIN_Y4 -to dis_di_o[2] +set_location_assignment PIN_Y5 -to dis_do_i +set_location_assignment PIN_Y9 -to slwr +set_location_assignment PLLOUTPUTCOUNTER_X0_Y20_N1 -to "monster:main|dmtd_pll5:\\dmtd_a5:dmtd_inst|dmtd_pll5_0002:dmtd_pll5_inst|altera_pll:altera_pll_i|outclk_wire[0]" +set_location_assignment PLLOUTPUTCOUNTER_X0_Y64_N1 -to "monster:main|sys_pll5:\\sys_a5:sys_inst|sys_pll5_0002:sys_pll5_inst|altera_pll:altera_pll_i|outclk_wire[3]" +set_location_assignment PLLOUTPUTCOUNTER_X0_Y65_N1 -to "monster:main|sys_pll5:\\sys_a5:sys_inst|sys_pll5_0002:sys_pll5_inst|altera_pll:altera_pll_i|outclk_wire[2]" +set_location_assignment PLLOUTPUTCOUNTER_X0_Y66_N1 -to "monster:main|sys_pll5:\\sys_a5:sys_inst|sys_pll5_0002:sys_pll5_inst|altera_pll:altera_pll_i|outclk_wire[1]" +set_location_assignment PLLOUTPUTCOUNTER_X0_Y67_N1 -to "monster:main|sys_pll5:\\sys_a5:sys_inst|sys_pll5_0002:sys_pll5_inst|altera_pll:altera_pll_i|outclk_wire[0]" +set_location_assignment PLLOUTPUTCOUNTER_X43_Y61_N1 -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|cascade_wire[2]" +set_location_assignment PLLOUTPUTCOUNTER_X43_Y62_N1 -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|cascade_wire[1]" +set_location_assignment PLLOUTPUTCOUNTER_X43_Y63_N1 -to "monster:main|ref_pll5:\\ref_a5:ref_inst|ref_pll5_0002:ref_pll5_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|cascade_wire[0]" diff --git a/syn/gsi_pexp/sdr/pexp_control_sdr.tcl b/syn/gsi_pexp/sdr/pexp_control_sdr.tcl new file mode 100644 index 000000000..fe950db56 --- /dev/null +++ b/syn/gsi_pexp/sdr/pexp_control_sdr.tcl @@ -0,0 +1,9 @@ +set platform "pexp_sdr" +source ../../autogen.tcl +source ../../../modules/build_id/build_id.tcl +source ../../../ip_cores/general-cores/platform/altera/networks/arria5.tcl +source ../../../ip_cores/general-cores/platform/altera/wb_pcie/arria5.tcl +source ../../../modules/pll/arria5/arria5_pll.tcl +source ../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.tcl +source ../../common/arria5_legacy_flash_patch.tcl +source ../../common/arria5_serdes_lvds_patch.tcl