From 715851999efc3417551e631a02cdea576a4f2306 Mon Sep 17 00:00:00 2001 From: Connal de Souza Date: Fri, 27 Sep 2024 12:39:31 -0400 Subject: [PATCH] fix formatting --- clients/drcachesim/simulator/prefetcher.cpp | 11 ++++++----- clients/drcachesim/tests/drcachesim_unit_tests.cpp | 12 ++++++------ 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/clients/drcachesim/simulator/prefetcher.cpp b/clients/drcachesim/simulator/prefetcher.cpp index 33a859690b1..e48a8f2449b 100644 --- a/clients/drcachesim/simulator/prefetcher.cpp +++ b/clients/drcachesim/simulator/prefetcher.cpp @@ -48,14 +48,15 @@ prefetcher_t::prefetcher_t(int block_size) } void -prefetcher_t::prefetch(caching_device_t *cache, const memref_t &memref_in, const bool missed) +prefetcher_t::prefetch(caching_device_t *cache, const memref_t &memref_in, + const bool missed) { // We implement a simple next-line prefetcher. if (missed && !type_is_prefetch(memref_in.data.type)) { - memref_t memref = memref_in; - memref.data.addr += block_size_; - memref.data.type = TRACE_TYPE_HARDWARE_PREFETCH; - cache->request(memref); + memref_t memref = memref_in; + memref.data.addr += block_size_; + memref.data.type = TRACE_TYPE_HARDWARE_PREFETCH; + cache->request(memref); } } } // namespace drmemtrace diff --git a/clients/drcachesim/tests/drcachesim_unit_tests.cpp b/clients/drcachesim/tests/drcachesim_unit_tests.cpp index 7b2b323a25a..d0432060ace 100644 --- a/clients/drcachesim/tests/drcachesim_unit_tests.cpp +++ b/clients/drcachesim/tests/drcachesim_unit_tests.cpp @@ -331,12 +331,12 @@ class next2line_prefetcher_factory_t : public prefetcher_factory_t { { // We implement a simple 2 next-line prefetcher.i if (missed && !type_is_prefetch(memref_in.data.type)) { - memref_t memref = memref_in; - memref.data.addr += block_size_; - memref.data.type = TRACE_TYPE_HARDWARE_PREFETCH; - cache->request(memref); - memref.data.addr += block_size_; - cache->request(memref); + memref_t memref = memref_in; + memref.data.addr += block_size_; + memref.data.type = TRACE_TYPE_HARDWARE_PREFETCH; + cache->request(memref); + memref.data.addr += block_size_; + cache->request(memref); } } };