Improve setting of configurable Flash + RAM sizes

[maxgerhardt]

Very sneakily, some CH32V20x and CH32V30x chips have the capability for different Flash+SRAM configurations.

These seem to be programmed into the option bytes (through the flash peripheral).

Original linker scripts.

/* CH32V30x_D8C - CH32V307VC-CH32V307WC-CH32V307RC
   CH32V30x_D8 - CH32V303VC-CH32V303RC
   FLASH + RAM supports the following configuration
   FLASH-192K + RAM-128K
   FLASH-224K + RAM-96K
   FLASH-256K + RAM-64K  
   FLASH-288K + RAM-32K  
*/
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
}

/* CH32V20x_D8 - CH32V203RB
   CH32V20x_D8W - CH32V208x
   FLASH + RAM supports the following configuration
   FLASH-128K + RAM-64K
   FLASH-144K + RAM-48K
   FLASH-160K + RAM-32K
*/
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K

}

Currently we only hint at this in the platformio.ini for one chip

platform-ch32v/examples/blinky-none-os/platformio.ini

Lines 28 to 43 in f1eb50c

	board = ch32v307_evt
	; some V30x and V20x chips can have configurable flash and SRAM sizes. These need to be programmed
	; *beforehand* into the flash option registers and synchronized with the settings here, otherwise
	; your chip WILL NOT BOOT!
	; flash 288K + SRAM 32K
	board_upload.maximum_size = 294912
	board_upload.maximum_ram_size = 32768
	; flash 256K + SRAM 64K
	;board_upload.maximum_size = 262144
	;board_upload.maximum_ram_size = 65536
	; flash 224K + SRAM 96K
	;board_upload.maximum_size = 229376
	;board_upload.maximum_ram_size = 98304
	; flash 192 + SRAM 128K
	;board_upload.maximum_size = 196608
	;board_upload.maximum_ram_size = 131072

If the chip was configured to have one configuration (e.g., "FLASH-288K + RAM-32K") but the platformio.ini configuration builds a firmware for the "FLASH-256K + RAM-64K" configuration, the chip will fail too boot properly, because the linker script and startup file will place the initial stack pointer (SP) at the end of RAM (so e.g. 0x200000 + 64K) which is not RAM in the current configuration, so at the first usage of the stack (like a jal instruction), the chip HardFault's.

We need a way for these chips to readout the current Flash+SRAM configuration and check them against the used build config, then either throw a really big warning or straightup fail the build or upload process.

It would also be good if we had a way to set a desired configuration and have that available as a PlatformIO task (together with removing read/write protection locks).

Currently I've been doing this via the official W.CH ISP Programmer tools.