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Invalid bank state error in LPDDR5 #66

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tommarin opened this issue Oct 11, 2024 · 0 comments
Open

Invalid bank state error in LPDDR5 #66

tommarin opened this issue Oct 11, 2024 · 0 comments

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@tommarin
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tommarin commented Oct 11, 2024 •
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Setup

Frontend:
  impl: SimpleO3
  clock_ratio: 8
  num_expected_insts: 500000
  traces:
    - ../ramulator/cputraces/429.mcf

  Translation:
    impl: RandomTranslation
    max_addr: 2147483648

MemorySystem:
  impl: GenericDRAM
  clock_ratio: 3

  DRAM:
    impl: LPDDR5
    org:
      preset: LPDDR5_4Gb_x16
    timing:
      preset: LPDDR5_6400

  Controller:
    impl: Generic
    Scheduler:
      impl: FRFCFS
    RefreshManager:
      impl: AllBank
    RowPolicy:
      impl: OpenRowPolicy
      cap: 4
    plugins:

  AddrMapper:
    impl: RoBaRaCoCh

Issue description

Simulation fails with this error:

[error] [RowHit::Bank] Invalid bank state for an RD/WR command!
tommarin added a commit to tommarin/ramulator2 that referenced this issue Oct 11, 2024
@tommarin
Fix RowHit/RowOpen lambdas in LPDDR5
06d2125 
The use of the RowOpen/RowHit lambdas to detect the
bank state during a RD/WR operation does not consider
the Pre-Opened state, specific to LPDDR5. This results
in assuming the default case, which provokes an execution
error.
This commit fixes this behavior by using custom lambdas
for LPDDR5, to include the additional state.

A similar fix was provided by the PSAL-POSTECH group in
https://github.com/PSAL-POSTECH/ramulator2, commit
bb1d54f.

Fixes issue CMU-SAFARI#66.
@tommarin tommarin mentioned this issue Oct 11, 2024
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@tommarin