Preconditioning error

[tmnvnbl]

When preconditioning an SSD device (<Enabled_Preconditioning>true</Enabled_Preconditioning>), the preconditioning code very often results in an error:
"It is not possible to assign PPA to all LPAs in Allocate_address_for_preconditioning! It is not safe to continue preconditioning."

Depending on the workload (Initial_Occupancy_Percentage, but also type such as STREAMING or RANDOM_UNIFORM), this error shows up or does not show up. This makes a little sense, as the workload defines the distribution of addresses used in the preconditioning, but does not explain why preconditioning fails.

How can this error be avoided?

[SAM-ZY-2019]

I got the same error.
"It is not possible to assign PPA to all LPAs in Allocate_address_for_preconditioning! It is not safe to continue preconditioning"

My SSD config is:
<?xml version="1.0" encoding="us-ascii"?> <Execution_Parameter_Set> <Host_Parameter_Set> <PCIe_Lane_Bandwidth>1.00000</PCIe_Lane_Bandwidth> <PCIe_Lane_Count>4</PCIe_Lane_Count> <SATA_Processing_Delay>400000</SATA_Processing_Delay> <Enable_ResponseTime_Logging>false</Enable_ResponseTime_Logging> <ResponseTime_Logging_Period_Length>1000000</ResponseTime_Logging_Period_Length> </Host_Parameter_Set> <Device_Parameter_Set> <Seed>321</Seed> <Enabled_Preconditioning>true</Enabled_Preconditioning> <Memory_Type>FLASH</Memory_Type> <HostInterface_Type>NVME</HostInterface_Type> <IO_Queue_Depth>65535</IO_Queue_Depth> <Queue_Fetch_Size>16</Queue_Fetch_Size> <Caching_Mechanism>ADVANCED</Caching_Mechanism> <Data_Cache_Sharing_Mode>SHARED</Data_Cache_Sharing_Mode> <Data_Cache_Capacity>268435456</Data_Cache_Capacity> <Data_Cache_DRAM_Row_Size>8192</Data_Cache_DRAM_Row_Size> <Data_Cache_DRAM_Data_Rate>400</Data_Cache_DRAM_Data_Rate> <Data_Cache_DRAM_Data_Busrt_Size>2</Data_Cache_DRAM_Data_Busrt_Size> <Data_Cache_DRAM_tRCD>13</Data_Cache_DRAM_tRCD> <Data_Cache_DRAM_tCL>13</Data_Cache_DRAM_tCL> <Data_Cache_DRAM_tRP>13</Data_Cache_DRAM_tRP> <Address_Mapping>PAGE_LEVEL</Address_Mapping> <Ideal_Mapping_Table>true</Ideal_Mapping_Table> <CMT_Capacity>2097152</CMT_Capacity> <CMT_Sharing_Mode>SHARED</CMT_Sharing_Mode> <Plane_Allocation_Scheme>CWDP</Plane_Allocation_Scheme> <Transaction_Scheduling_Policy>OUT_OF_ORDER</Transaction_Scheduling_Policy> <Overprovisioning_Ratio>0.07</Overprovisioning_Ratio> <GC_Exec_Threshold>0.05000</GC_Exec_Threshold> <GC_Block_Selection_Policy>RGA</GC_Block_Selection_Policy> <Use_Copyback_for_GC>false</Use_Copyback_for_GC> <Preemptible_GC_Enabled>false</Preemptible_GC_Enabled> <GC_Hard_Threshold>0.005000</GC_Hard_Threshold> <Dynamic_Wearleveling_Enabled>true</Dynamic_Wearleveling_Enabled> <Static_Wearleveling_Enabled>true</Static_Wearleveling_Enabled> <Static_Wearleveling_Threshold>100</Static_Wearleveling_Threshold> <Preferred_suspend_erase_time_for_read>700000</Preferred_suspend_erase_time_for_read> <Preferred_suspend_erase_time_for_write>700000</Preferred_suspend_erase_time_for_write> <Preferred_suspend_write_time_for_read>100000</Preferred_suspend_write_time_for_read> <Flash_Channel_Count>2</Flash_Channel_Count> <Flash_Channel_Width>1</Flash_Channel_Width> <Channel_Transfer_Rate>333</Channel_Transfer_Rate> <Chip_No_Per_Channel>4</Chip_No_Per_Channel> <Flash_Comm_Protocol>NVDDR2</Flash_Comm_Protocol> <Flash_Parameter_Set> <Flash_Technology>MLC</Flash_Technology> <CMD_Suspension_Support>ERASE</CMD_Suspension_Support> <Page_Read_Latency_LSB>75000</Page_Read_Latency_LSB> <Page_Read_Latency_CSB>75000</Page_Read_Latency_CSB> <Page_Read_Latency_MSB>75000</Page_Read_Latency_MSB> <Page_Program_Latency_LSB>750000</Page_Program_Latency_LSB> <Page_Program_Latency_CSB>750000</Page_Program_Latency_CSB> <Page_Program_Latency_MSB>750000</Page_Program_Latency_MSB> <Block_Erase_Latency>3800000</Block_Erase_Latency> <Block_PE_Cycles_Limit>10000</Block_PE_Cycles_Limit> <Suspend_Erase_Time>700000</Suspend_Erase_Time> <Suspend_Program_Time>100000</Suspend_Program_Time> <Die_No_Per_Chip>2</Die_No_Per_Chip> <Plane_No_Per_Die>2</Plane_No_Per_Die> <Block_No_Per_Plane>2048</Block_No_Per_Plane> <Page_No_Per_Block>256</Page_No_Per_Block> <Page_Capacity>8192</Page_Capacity> <Page_Metadat_Capacity>448</Page_Metadat_Capacity> </Flash_Parameter_Set> </Device_Parameter_Set> </Execution_Parameter_Set>

My workload config is:

<?xml version="1.0" encoding="us-ascii"?> <MQSim_IO_Scenarios> <IO_Scenario> <IO_Flow_Parameter_Set_Synthetic> <Priority_Class>HIGH</Priority_Class> <Device_Level_Data_Caching_Mode>WRITE_CACHE</Device_Level_Data_Caching_Mode> <Channel_IDs>0,1</Channel_IDs> <Chip_IDs>0,1</Chip_IDs> <Die_IDs>0,1</Die_IDs> <Plane_IDs>0,1</Plane_IDs> <Initial_Occupancy_Percentage>100</Initial_Occupancy_Percentage> <Working_Set_Percentage>100</Working_Set_Percentage> <Synthetic_Generator_Type>QUEUE_DEPTH</Synthetic_Generator_Type> <Read_Percentage>0</Read_Percentage> <Address_Distribution>RANDOM_HOTCOLD</Address_Distribution> <Percentage_of_Hot_Region>30</Percentage_of_Hot_Region> <Generated_Aligned_Addresses>true</Generated_Aligned_Addresses> <Address_Alignment_Unit>16</Address_Alignment_Unit> <Request_Size_Distribution>FIXED</Request_Size_Distribution> <Average_Request_Size>8</Average_Request_Size> <Variance_Request_Size>0</Variance_Request_Size> <Seed>798</Seed> <Average_No_of_Reqs_in_Queue>8</Average_No_of_Reqs_in_Queue> <Stop_Time>10000000000000</Stop_Time> <Total_Requests_To_Generate>0</Total_Requests_To_Generate> </IO_Flow_Parameter_Set_Synthetic> </IO_Scenario> </MQSim_IO_Scenarios>